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424 lines
16 KiB
Verilog
424 lines
16 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: Pervasive Core Thread Controls
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module pcq_ctrl(
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// Include model build parameters
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`include "tri_a2o.vh"
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inout vdd,
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inout gnd,
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input clk,
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input rst,
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input scan_dis_dc_b,
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input lcb_clkoff_dc_b,
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input lcb_mpw1_dc_b,
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input lcb_mpw2_dc_b,
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input lcb_delay_lclkr_dc,
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input lcb_act_dis_dc,
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input pc_pc_func_slp_sl_thold_0,
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input pc_pc_sg_0,
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input func_scan_in,
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output func_scan_out,
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// Reset Related
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output pc_lq_init_reset,
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output pc_iu_init_reset,
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output ct_rg_hold_during_init,
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// Power Management
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output [0:`THREADS-1] ct_rg_power_managed,
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output ac_an_power_managed,
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output ac_an_rvwinkle_mode,
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output pc_xu_pm_hold_thread,
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output ct_ck_pm_ccflush_disable,
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output ct_ck_pm_raise_tholds,
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input rg_ct_dis_pwr_savings,
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input [0:1] xu_pc_spr_ccr0_pme,
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input [0:`THREADS-1] xu_pc_spr_ccr0_we,
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// Trace/Trigger Signals
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output [0:14] dbg_ctrls
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);
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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parameter INITACTIVE_SIZE = 1;
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parameter HOLDCNTR_SIZE = 3;
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parameter INITCNTR_SIZE = 9;
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parameter INITERAT_SIZE = 1;
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parameter PMCTRLS_T0_SIZE = 15;
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parameter PMCTRLS_T1_SIZE = 2 * (`THREADS - 1);
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parameter SPARECTRL_SIZE = 6;
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//---------------------------------------------------------------------
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// Scan Ring Ordering:
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// start of func scan chain ordering
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parameter INITACTIVE_OFFSET = 0;
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parameter HOLDCNTR_OFFSET = INITACTIVE_OFFSET + INITACTIVE_SIZE;
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parameter INITCNTR_OFFSET = HOLDCNTR_OFFSET + HOLDCNTR_SIZE;
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parameter INITERAT_OFFSET = INITCNTR_OFFSET + INITCNTR_SIZE;
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parameter PMCTRLS_T0_OFFSET = INITERAT_OFFSET + INITERAT_SIZE;
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parameter PMCTRLS_T1_OFFSET = PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE;
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parameter SPARECTRL_OFFSET = PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE;
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parameter FUNC_RIGHT = SPARECTRL_OFFSET + SPARECTRL_SIZE - 1;
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// end of func scan chain ordering
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//---------------------------------------------------------------------
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// Array Initialization Controls:
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parameter HOLDCNT_IDLE = 0;
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parameter HOLDCNT_DONE = 7;
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parameter INITCNT_START = 15+(`INIT_BHT*496); // sets INITCNTR to 15 or 511
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parameter INITCNT_DONE = 0;
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//---------------------------------------------------------------------
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// Basic/Misc signals
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wire tiup;
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wire [0:FUNC_RIGHT] func_siv;
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wire [0:FUNC_RIGHT] func_sov;
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wire pc_pc_func_slp_sl_thold_0_b;
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wire force_funcslp;
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// Reset Signals
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wire initcntr_enabled;
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// Power management Signals
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wire [0:1] spr_ccr0_pme_q;
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wire [0:`THREADS-1] spr_ccr0_we_q;
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wire pm_sleep_enable;
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wire pm_rvw_enable;
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wire [0:`THREADS-1] thread_stopped;
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wire pmstate_q_anded;
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// Latch definitions begin
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wire [0:HOLDCNTR_SIZE-1] holdcntr_d;
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wire [0:HOLDCNTR_SIZE-1] holdcntr_q;
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wire [0:INITCNTR_SIZE-1] initcntr_d;
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wire [0:INITCNTR_SIZE-1] initcntr_q;
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wire init_active_d;
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wire init_active_q;
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wire initerat_d;
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wire initerat_q;
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wire pmstate_enab;
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wire [0:`THREADS-1] pmstate_d;
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wire [0:`THREADS-1] pmstate_q;
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wire pmstate_all_d;
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wire pmstate_all_q;
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wire [0:7] pmclkctrl_dly_d;
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wire [0:7] pmclkctrl_dly_q;
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wire power_managed_d;
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wire power_managed_q;
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wire rvwinkled_d;
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wire rvwinkled_q;
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wire pm_ccflush_disable_int;
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wire pm_raise_tholds_int;
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wire [0:SPARECTRL_SIZE-1] spare_ctrl_wrapped_q;
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//!! Bugspray Include: pcq_ctrl;
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assign tiup = 1'b1;
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//=====================================================================
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// Reset State Machine
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//=====================================================================
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// HOLDCNTR: Delays start of array initialization for 7 cycles. Provides some time
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// after clock start to ensure clock controls have propagated to LCBs. .
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assign holdcntr_d = init_active_q == 1'b0 ? HOLDCNT_IDLE :
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holdcntr_q == HOLDCNT_DONE ? HOLDCNT_DONE :
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holdcntr_q + 3'b001;
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// Latch ACT control: Goes inactive once array initialization is over.
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assign initcntr_enabled = init_active_q | (|holdcntr_q);
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// INITCNTR: Initialized to a value; counts down while array init signal held active.
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// Default time is 16 cycles, which is long enough for the ERATs to initialize.
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// To initialize the BHT, the array init signal is kept active for 512 cycles.
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// Controlled by `INIT_BHT (0=16 cycles; 1=512 cycles)
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assign initcntr_d = holdcntr_q != HOLDCNT_DONE ? initcntr_q :
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initcntr_q == INITCNT_DONE ? INITCNT_DONE :
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initcntr_q - 9'b000000001;
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// INITERAT: The initerat latch controls the init_reset signals to IU and XU.
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// Goes active when HOLDCNTR=7, and shuts off when INITCNTR counts down to 0.
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assign initerat_d = ( holdcntr_q < HOLDCNT_DONE-1) ? 1'b0 :
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(|initcntr_q);
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// INIT_ACTIVE: init_active_q initializes to '1'; cleared after INITCNTR counts down to 0.
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assign init_active_d = (initcntr_q == INITCNT_DONE) ? 1'b0 :
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init_active_q;
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//=====================================================================
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// Power Management Latches
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//=====================================================================
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// XU signals indicate when power-savings is enabled (sleep or rvw modes), and which
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// THREADS are stopped.
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// The pmstate latch tracks which THREADS are stopped when either power-savings mode
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// is enabled. The rvwinkled latch only when pm_rvw_enable is set.
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// If all THREADS are stopped when power-savings is enabled, then signals to the
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// clock control macro will initiate power savings actions. These controls force
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// ccflush_dc inactive to ensure all PLATs are clocking. After a delay period, the
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// run tholds will be raised to stop clocks.
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// When coming out of power-savings, the tholds will be disabled prior to deactivating
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// ccflush_dc.
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assign pm_sleep_enable = (~spr_ccr0_pme_q[0]) & spr_ccr0_pme_q[1];
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assign pm_rvw_enable = spr_ccr0_pme_q[0] & (~spr_ccr0_pme_q[1]);
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assign thread_stopped = spr_ccr0_we_q;
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assign pmstate_enab = (pm_sleep_enable | pm_rvw_enable) & (~initcntr_enabled);
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assign pmstate_d = {`THREADS{pmstate_enab}} & thread_stopped[0:`THREADS - 1];
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// Once all CCR0[WE] bits are set, pmstate_all_q is held active until pmclkctrl_dly_q(7).
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// Forces an orderly sequence through PM controls, even if one thread wakes-up right away.
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assign pmstate_q_anded = (&pmstate_q);
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assign pmstate_all_d = ((~pmclkctrl_dly_q[7]) & (pmstate_q_anded | pmstate_all_q)) |
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(pmstate_q_anded & pmstate_all_q);
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assign power_managed_d = pmstate_all_d | pmclkctrl_dly_q[6];
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assign rvwinkled_d = (pmstate_all_d | pmclkctrl_dly_q[6]) & pm_rvw_enable;
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assign pmclkctrl_dly_d[0:7] = {pmstate_all_q, pmclkctrl_dly_q[0:6]};
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//=====================================================================
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// Outputs
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//=====================================================================
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// Used as part of thread stop signal to XU.
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// Keeps THREADS stopped until after the Reset SM completes count.
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assign ct_rg_hold_during_init = init_active_q;
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// Init pulse to IU and XU to force initialization of IERAT, DERAT and BHT.
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// IU also holds instruction fetch until init signal released.
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assign pc_iu_init_reset = initerat_q;
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assign pc_lq_init_reset = initerat_q;
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// To THRCTL[Tx_PM]; indicates core power-managed via software actions.
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assign ct_rg_power_managed = pmstate_q[0:`THREADS - 1];
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// Core in rvwinkle power-savings state. L2 can prepare for Chiplet power-down.
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assign ac_an_rvwinkle_mode = rvwinkled_q;
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// Core in power-savings state due to any combination of power-savings instructions
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assign ac_an_power_managed = power_managed_q;
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assign pc_xu_pm_hold_thread = power_managed_q;
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// Goes to clock controls to disable plat flush controls
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assign pm_ccflush_disable_int = pmstate_all_q | pmclkctrl_dly_q[7];
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assign ct_ck_pm_ccflush_disable = pm_ccflush_disable_int & (~rg_ct_dis_pwr_savings);
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// Goes to clock controls to activate run tholds
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assign pm_raise_tholds_int = pmstate_all_q & pmclkctrl_dly_q[7];
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assign ct_ck_pm_raise_tholds = pm_raise_tholds_int & (~rg_ct_dis_pwr_savings);
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//=====================================================================
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// Trace/Trigger Signals
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//=====================================================================
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assign dbg_ctrls = { pmstate_q_anded, // 0
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pmstate_all_q, // 1
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power_managed_q, // 2
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rvwinkled_q, // 3
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pmclkctrl_dly_q[0:7], // 4:11
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rg_ct_dis_pwr_savings, // 12
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pm_ccflush_disable_int, // 13
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pm_raise_tholds_int // 14
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};
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//=====================================================================
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// Latches
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//=====================================================================
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// func ring registers start
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tri_rlmlatch_p #(.INIT(1)) initactive(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ INITACTIVE_OFFSET]),
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.scout(func_sov[INITACTIVE_OFFSET]),
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.din(init_active_d),
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.dout(init_active_q)
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);
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tri_rlmreg_p #(.WIDTH(HOLDCNTR_SIZE), .INIT(0)) holdcntr(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(initcntr_enabled),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ HOLDCNTR_OFFSET:HOLDCNTR_OFFSET + HOLDCNTR_SIZE - 1]),
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.scout(func_sov[HOLDCNTR_OFFSET:HOLDCNTR_OFFSET + HOLDCNTR_SIZE - 1]),
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.din(holdcntr_d),
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.dout(holdcntr_q)
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);
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tri_rlmreg_p #(.WIDTH(INITCNTR_SIZE), .INIT(INITCNT_START)) initcntr(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(initcntr_enabled),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ INITCNTR_OFFSET:INITCNTR_OFFSET + INITCNTR_SIZE - 1]),
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.scout(func_sov[INITCNTR_OFFSET:INITCNTR_OFFSET + INITCNTR_SIZE - 1]),
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.din(initcntr_d),
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.dout(initcntr_q)
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);
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tri_rlmlatch_p #(.INIT(0)) initerat(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(initcntr_enabled),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ INITERAT_OFFSET]),
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.scout(func_sov[INITERAT_OFFSET]),
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.din(initerat_d),
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.dout(initerat_q)
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);
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tri_rlmreg_p #(.WIDTH(PMCTRLS_T0_SIZE), .INIT(0)) pmctrls_t0(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ PMCTRLS_T0_OFFSET:PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE - 1]),
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.scout(func_sov[PMCTRLS_T0_OFFSET:PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE - 1]),
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.din( {pmclkctrl_dly_d, xu_pc_spr_ccr0_pme, xu_pc_spr_ccr0_we[0], pmstate_d[0],
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pmstate_all_d, rvwinkled_d, power_managed_d}),
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.dout({pmclkctrl_dly_q, spr_ccr0_pme_q, spr_ccr0_we_q[0], pmstate_q[0],
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pmstate_all_q, rvwinkled_q, power_managed_q})
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);
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generate
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if (`THREADS > 1)
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begin : T1_pmctrls
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tri_rlmreg_p #(.WIDTH(PMCTRLS_T1_SIZE), .INIT(0)) pmctrls_t1(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ PMCTRLS_T1_OFFSET:PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE - 1]),
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.scout(func_sov[PMCTRLS_T1_OFFSET:PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE - 1]),
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.din({xu_pc_spr_ccr0_we[1], pmstate_d[1]}),
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.dout({spr_ccr0_we_q[1], pmstate_q[1]})
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);
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end
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endgenerate
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tri_rlmreg_p #(.WIDTH(SPARECTRL_SIZE), .INIT(0)) sparectrl(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.act(tiup),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_funcslp),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[ SPARECTRL_OFFSET:SPARECTRL_OFFSET + SPARECTRL_SIZE - 1]),
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.scout(func_sov[SPARECTRL_OFFSET:SPARECTRL_OFFSET + SPARECTRL_SIZE - 1]),
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.din(spare_ctrl_wrapped_q),
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.dout(spare_ctrl_wrapped_q)
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);
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// func ring registers end
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//=====================================================================
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// Thold/SG Staging
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//=====================================================================
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// func_slp lcbor
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tri_lcbor lcbor_funcslp(
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.clkoff_b(lcb_clkoff_dc_b),
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.thold(pc_pc_func_slp_sl_thold_0),
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.sg(pc_pc_sg_0),
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.act_dis(lcb_act_dis_dc),
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.force_t(force_funcslp),
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.thold_b(pc_pc_func_slp_sl_thold_0_b)
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);
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//=====================================================================
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// Scan Connections
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//=====================================================================
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// Func ring
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assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
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assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
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endmodule
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