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782 lines
33 KiB
Verilog
782 lines
33 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_add_glbc(
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ex4_g16,
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ex4_t16,
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ex4_inc_all1,
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ex4_effsub,
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ex4_effsub_npz,
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ex4_effadd_npz,
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f_alg_ex4_frc_sel_p1,
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f_alg_ex4_sticky,
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f_pic_ex4_is_nan,
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f_pic_ex4_is_gt,
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f_pic_ex4_is_lt,
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f_pic_ex4_is_eq,
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f_pic_ex4_cmp_sgnpos,
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f_pic_ex4_cmp_sgnneg,
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ex4_g128,
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ex4_g128_b,
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ex4_t128,
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ex4_t128_b,
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ex4_flip_inc_p0,
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ex4_flip_inc_p1,
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ex4_inc_sel_p0,
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ex4_inc_sel_p1,
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ex4_eac_sel_p0n,
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ex4_eac_sel_p0,
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ex4_eac_sel_p1,
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ex4_sign_carry,
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ex4_flag_nan_cp1,
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ex4_flag_gt_cp1,
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ex4_flag_lt_cp1,
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ex4_flag_eq_cp1,
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ex4_flag_nan,
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ex4_flag_gt,
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ex4_flag_lt,
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ex4_flag_eq
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);
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input [0:6] ex4_g16; // from each byte section
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input [0:6] ex4_t16; // from each byte section
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input ex4_inc_all1;
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input ex4_effsub;
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input ex4_effsub_npz;
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input ex4_effadd_npz;
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input f_alg_ex4_frc_sel_p1;
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input f_alg_ex4_sticky;
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input f_pic_ex4_is_nan;
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input f_pic_ex4_is_gt;
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input f_pic_ex4_is_lt;
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input f_pic_ex4_is_eq;
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input f_pic_ex4_cmp_sgnpos;
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input f_pic_ex4_cmp_sgnneg;
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//------------------
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output [1:6] ex4_g128; // to each byte section
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output [1:6] ex4_g128_b; // to each byte section
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output [1:6] ex4_t128; // to each byte section
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output [1:6] ex4_t128_b; // to each byte section
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//------------------
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output ex4_flip_inc_p0;
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output ex4_flip_inc_p1;
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output ex4_inc_sel_p0;
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output ex4_inc_sel_p1;
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output [0:6] ex4_eac_sel_p0n;
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output [0:6] ex4_eac_sel_p0;
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output [0:6] ex4_eac_sel_p1;
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output ex4_sign_carry;
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output ex4_flag_nan_cp1;
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output ex4_flag_gt_cp1;
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output ex4_flag_lt_cp1;
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output ex4_flag_eq_cp1;
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output ex4_flag_nan;
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output ex4_flag_gt;
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output ex4_flag_lt;
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output ex4_flag_eq;
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire cp0_g32_01_b;
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wire cp0_g32_23_b;
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wire cp0_g32_45_b;
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wire cp0_g32_66_b;
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wire cp0_t32_01_b;
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wire cp0_t32_23_b;
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wire cp0_t32_45_b;
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wire cp0_t32_66_b;
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wire cp0_g64_03;
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wire cp0_g64_46;
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wire cp0_t64_03;
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wire cp0_t64_46;
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wire cp0_g128_06_b;
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wire cp0_t128_06_b;
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wire cp0_all1_b;
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wire cp0_all1_p;
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wire cp0_co_p0;
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wire cp0_co_p1;
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wire cp0_flip_inc_p1_b;
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wire ex4_inc_sel_p0_b;
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wire ex4_sign_carry_b;
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wire ex4_my_gt_b;
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wire ex4_my_lt;
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wire ex4_my_eq_b;
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wire ex4_my_gt;
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wire ex4_my_eq;
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wire ex4_gt_pos_b;
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wire ex4_gt_neg_b;
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wire ex4_lt_pos_b;
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wire ex4_lt_neg_b;
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wire ex4_eq_eq_b;
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wire ex4_is_gt_b;
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wire ex4_is_lt_b;
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wire ex4_is_eq_b;
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wire ex4_sgn_eq;
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wire cp7_g32_00_b;
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wire cp7_g32_12_b;
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wire cp7_g32_34_b;
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wire cp7_g32_56_b;
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wire cp7_t32_00_b;
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wire cp7_t32_12_b;
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wire cp7_t32_34_b;
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wire cp7_g64_02;
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wire cp7_g64_36;
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wire cp7_t64_02;
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wire cp7_g128_06_b;
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wire cp7_all1_b;
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wire cp7_all1_p;
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wire cp7_co_p0;
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wire cp7_sel_p0n_x_b;
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wire cp7_sel_p0n_y_b;
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wire cp7_sel_p0_b;
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wire cp7_sel_p1_b;
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wire cp7_sub_sticky;
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wire cp7_sub_stickyn;
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wire cp7_add_frcp1_b;
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wire cp7_add_frcp0_b;
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wire cp6_g32_00_b;
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wire cp6_g32_12_b;
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wire cp6_g32_34_b;
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wire cp6_g32_56_b;
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wire cp6_t32_00_b;
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wire cp6_t32_12_b;
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wire cp6_t32_34_b;
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wire cp6_g64_02;
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wire cp6_g64_36;
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wire cp6_t64_02;
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wire cp6_g128_06_b;
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wire cp6_all1_b;
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wire cp6_all1_p;
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wire cp6_co_p0;
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wire cp6_sel_p0n_x_b;
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wire cp6_sel_p0n_y_b;
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wire cp6_sel_p0_b;
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wire cp6_sel_p1_b;
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wire cp6_sub_sticky;
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wire cp6_sub_stickyn;
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wire cp6_add_frcp1_b;
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wire cp6_add_frcp0_b;
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wire cp5_g32_00_b;
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wire cp5_g32_12_b;
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wire cp5_g32_34_b;
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wire cp5_g32_56_b;
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wire cp5_t32_00_b;
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wire cp5_t32_12_b;
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wire cp5_t32_34_b;
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wire cp5_t32_56_b;
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wire cp5_g64_02;
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wire cp5_g64_36;
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wire cp5_t64_02;
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wire cp5_g128_06_b;
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wire cp5_all1_b;
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wire cp5_all1_p;
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wire cp5_co_p0;
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wire cp5_sel_p0n_x_b;
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wire cp5_sel_p0n_y_b;
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wire cp5_sel_p0_b;
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wire cp5_sel_p1_b;
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wire cp5_sub_sticky;
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wire cp5_sub_stickyn;
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wire cp5_add_frcp1_b;
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wire cp5_add_frcp0_b;
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wire cp4_g32_01_b;
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wire cp4_g32_23_b;
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wire cp4_g32_45_b;
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wire cp4_g32_66_b;
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wire cp4_t32_01_b;
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wire cp4_t32_23_b;
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wire cp4_t32_45_b;
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wire cp4_t32_66_b;
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wire cp4_g64_03;
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wire cp4_g64_46;
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wire cp4_t64_03;
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wire cp4_t64_46;
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wire cp4_g128_06_b;
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wire cp4_all1_b;
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wire cp4_all1_p;
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wire cp4_co_p0;
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wire cp4_sel_p0n_x_b;
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wire cp4_sel_p0n_y_b;
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wire cp4_sel_p0_b;
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wire cp4_sel_p1_b;
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wire cp4_sub_sticky;
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wire cp4_sub_stickyn;
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wire cp4_add_frcp1_b;
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wire cp4_add_frcp0_b;
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wire cp3_g32_00_b;
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wire cp3_g32_12_b;
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wire cp3_g32_34_b;
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wire cp3_g32_56_b;
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wire cp3_t32_00_b;
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wire cp3_t32_12_b;
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wire cp3_t32_34_b;
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wire cp3_t32_56_b;
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wire cp3_g64_02;
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wire cp3_g64_36;
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wire cp3_t64_02;
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wire cp3_t64_36;
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wire cp3_g128_06_b;
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wire cp3_all1_b;
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wire cp3_all1_p;
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wire cp3_co_p0;
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wire cp3_sel_p0n_x_b;
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wire cp3_sel_p0n_y_b;
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wire cp3_sel_p0_b;
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wire cp3_sel_p1_b;
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wire cp3_sub_sticky;
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wire cp3_sub_stickyn;
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wire cp3_add_frcp1_b;
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wire cp3_add_frcp0_b;
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wire cp2_g32_01_b;
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wire cp2_g32_23_b;
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wire cp2_g32_45_b;
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wire cp2_g32_66_b;
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wire cp2_t32_01_b;
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wire cp2_t32_23_b;
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wire cp2_t32_45_b;
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wire cp2_t32_66_b;
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wire cp2_g64_03;
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wire cp2_g64_46;
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wire cp2_t64_03;
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wire cp2_t64_46;
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wire cp2_g128_06_b;
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wire cp2_all1_b;
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wire cp2_all1_p;
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wire cp2_co_p0;
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wire cp2_sel_p0n_x_b;
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wire cp2_sel_p0n_y_b;
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wire cp2_sel_p0_b;
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wire cp2_sel_p1_b;
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wire cp2_sub_sticky;
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wire cp2_sub_stickyn;
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wire cp2_add_frcp1_b;
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wire cp2_add_frcp0_b;
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wire cp1_g32_01_b;
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wire cp1_g32_23_b;
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wire cp1_g32_45_b;
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wire cp1_g32_66_b;
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wire cp1_t32_01_b;
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wire cp1_t32_23_b;
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wire cp1_t32_45_b;
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wire cp1_t32_66_b;
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wire cp1_g64_03;
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wire cp1_g64_46;
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wire cp1_t64_03;
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wire cp1_t64_46;
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wire cp1_g128_06_b;
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wire cp1_all1_b;
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wire cp1_all1_p;
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wire cp1_co_p0;
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wire cp1_sel_p0n_x_b;
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wire cp1_sel_p0n_y_b;
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wire cp1_sel_p0_b;
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wire cp1_sel_p1_b;
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wire cp1_sub_sticky;
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wire cp1_sub_stickyn;
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wire cp1_add_frcp1_b;
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wire cp1_add_frcp0_b;
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wire cp1_g32_11_b; //EXTRA
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wire cp1_t32_11_b;
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wire cp1_g64_13;
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wire cp1_t64_13;
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wire cp1_g128_16_b;
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wire cp1_t128_16_b;
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wire cp2_g64_23;
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wire cp2_t64_23;
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wire cp2_g128_26_b;
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wire cp2_t128_26_b;
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wire cp3_g128_36_b;
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wire cp3_t128_36_b;
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wire cp4_g128_46_b;
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wire cp4_t128_46_b;
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wire cp5_g64_56;
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wire cp5_t64_56;
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wire cp5_g128_56_b;
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wire cp5_t128_56_b;
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wire cp6_g32_66_b;
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wire cp6_t32_66_b;
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wire cp1_g128_16; //DRIVER
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wire cp1_t128_16;
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wire cp2_g128_26;
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wire cp2_t128_26;
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wire cp3_g128_36;
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wire cp3_t128_36;
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wire cp4_g128_46;
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wire cp4_t128_46;
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wire cp5_g128_56;
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wire cp5_t128_56;
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wire cp6_g128_66;
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wire cp6_t128_66;
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//=#########################################
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//= global carry chain <PARALLEL VERSIONS>
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//=#########################################
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// try to put all long wire from BYT to global
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// parallel copies should allow for smaller aoi/oai blocks
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//=#########################################
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//= CMP COPY
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//=#########################################
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// --compare stuff----
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// -- c0 : gt
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// -- c1 : ge
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//
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// ex4_my_eq <= (ex4_add_co_p1 and ex4_inc_all1 ) and not ex4_add_co_p0; -- ge * !gt
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// ex4_my_gt <= (ex4_add_co_p0 and ex4_inc_all1 ) ; -- gt
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// ex4_my_lt <= not(ex4_add_co_p1 and ex4_inc_all1 ) ; -- !ge
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//
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// ex4_flag_nan <= f_pic_ex4_is_nan;
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// ex4_flag_gt <= f_pic_ex4_is_gt or (f_pic_ex4_cmp_sgnpos and ex4_my_gt) or (f_pic_ex4_cmp_sgnneg and ex4_my_lt) ;
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// ex4_flag_lt <= f_pic_ex4_is_lt or (f_pic_ex4_cmp_sgnpos and ex4_my_lt) or (f_pic_ex4_cmp_sgnneg and ex4_my_gt) ;
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// ex4_flag_eq <= f_pic_ex4_is_eq or (f_pic_ex4_cmp_sgnpos and ex4_my_eq) or (f_pic_ex4_cmp_sgnneg and ex4_my_eq) ;
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assign cp0_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
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assign cp0_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
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assign cp0_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
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assign cp0_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
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assign cp0_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
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assign cp0_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
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assign cp0_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
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assign cp0_t32_66_b = (~(ex4_t16[6])); //cw_invert
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assign cp0_g64_03 = (~(cp0_g32_01_b & (cp0_t32_01_b | cp0_g32_23_b))); //cw_oai21
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assign cp0_g64_46 = (~(cp0_g32_45_b & (cp0_t32_45_b | cp0_g32_66_b))); //cw_oai21
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assign cp0_t64_03 = (~(cp0_t32_01_b | cp0_t32_23_b)); //cw_nor2
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assign cp0_t64_46 = (~(cp0_g32_45_b & (cp0_t32_45_b | cp0_t32_66_b))); //cw_oai21
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assign cp0_g128_06_b = (~(cp0_g64_03 | (cp0_t64_03 & cp0_g64_46))); //cw_aoi21
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assign cp0_t128_06_b = (~(cp0_g64_03 | (cp0_t64_03 & cp0_t64_46))); //cw_aoi21
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assign cp0_all1_b = (~ex4_inc_all1); //cw_invert
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assign cp0_all1_p = (~cp0_all1_b); //cw_invert
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assign cp0_co_p0 = (~(cp0_g128_06_b)); //cw_invert
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assign cp0_co_p1 = (~(cp0_t128_06_b)); //cw_invert
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//-------------- incr eac selects --------------------
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assign ex4_flip_inc_p0 = ex4_effsub; //NOT MAPPED --output--
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assign cp0_flip_inc_p1_b = (~(ex4_effsub & cp0_all1_b)); //cw_nand2
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assign ex4_flip_inc_p1 = (~(cp0_flip_inc_p1_b)); //cw_invert --output--
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assign ex4_inc_sel_p1 = (~cp0_g128_06_b); //cw_invert --OUTPUT--
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assign ex4_inc_sel_p0_b = (~cp0_g128_06_b); //cw_invert
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assign ex4_inc_sel_p0 = (~ex4_inc_sel_p0_b); //cw_invert --OUTPUT--
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//-------------- sign selects --------------------
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assign ex4_sign_carry_b = (~(ex4_effsub & cp0_all1_p & cp0_co_p0)); //cw_nand3
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assign ex4_sign_carry = (~(ex4_sign_carry_b)); //cw_invert --OUTPUT--
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//--------------- compares ---------------------------
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assign ex4_my_gt_b = (~(cp0_co_p0 & cp0_all1_p)); //cw_nand2
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assign ex4_my_lt = (~(cp0_co_p1 & cp0_all1_p)); //cw_nand2
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assign ex4_my_eq_b = (~(cp0_co_p1 & cp0_all1_p & cp0_g128_06_b)); //cw_nand3
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assign ex4_my_gt = (~ex4_my_gt_b); //cw_invert
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assign ex4_my_eq = (~ex4_my_eq_b); //cw_invert
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assign ex4_gt_pos_b = (~(ex4_my_gt & f_pic_ex4_cmp_sgnpos)); //cw_nand2
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assign ex4_gt_neg_b = (~(ex4_my_lt & f_pic_ex4_cmp_sgnneg)); //cw_nand2
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assign ex4_lt_pos_b = (~(ex4_my_lt & f_pic_ex4_cmp_sgnpos)); //cw_nand2
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assign ex4_lt_neg_b = (~(ex4_my_gt & f_pic_ex4_cmp_sgnneg)); //cw_nand2
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assign ex4_eq_eq_b = (~(ex4_my_eq & ex4_sgn_eq)); //cw_nand3
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assign ex4_flag_gt = (~(ex4_gt_pos_b & ex4_gt_neg_b & ex4_is_gt_b)); //cw_nand3 --output--
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assign ex4_flag_gt_cp1 = (~(ex4_gt_pos_b & ex4_gt_neg_b & ex4_is_gt_b)); //cw_nand3 --output--
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assign ex4_flag_lt = (~(ex4_lt_pos_b & ex4_lt_neg_b & ex4_is_lt_b)); //cw_nand3 --output--
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assign ex4_flag_lt_cp1 = (~(ex4_lt_pos_b & ex4_lt_neg_b & ex4_is_lt_b)); //cw_nand3 --output--
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assign ex4_flag_eq = (~(ex4_eq_eq_b & ex4_is_eq_b)); //cw_nand2 --output--
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assign ex4_flag_eq_cp1 = (~(ex4_eq_eq_b & ex4_is_eq_b)); //cw_nand2 --output--
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assign ex4_flag_nan = f_pic_ex4_is_nan; //NOT MAPPED --output--
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assign ex4_flag_nan_cp1 = f_pic_ex4_is_nan; //NOT MAPPED --output--
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assign ex4_is_gt_b = (~(f_pic_ex4_is_gt)); //NOT MAPPED
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assign ex4_is_lt_b = (~(f_pic_ex4_is_lt)); //NOT MAPPED
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assign ex4_is_eq_b = (~(f_pic_ex4_is_eq)); //NOT MAPPED
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assign ex4_sgn_eq = f_pic_ex4_cmp_sgnpos | f_pic_ex4_cmp_sgnneg; //NOT MAPPED
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//=#########################################
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//= BYT_0 MSB COPY
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//=#########################################
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assign cp1_g32_11_b = (~(ex4_g16[1])); //cw_aoi21 --EXTRA
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assign cp1_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
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assign cp1_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
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assign cp1_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
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assign cp1_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
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assign cp1_t32_11_b = (~(ex4_t16[1])); //cw_invert --EXTRA
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assign cp1_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
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assign cp1_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
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assign cp1_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
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assign cp1_t32_66_b = (~(ex4_t16[6])); //cw_invert
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assign cp1_g64_03 = (~(cp1_g32_01_b & (cp1_t32_01_b | cp1_g32_23_b))); //cw_oai21
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assign cp1_g64_13 = (~(cp1_g32_11_b & (cp1_t32_11_b | cp1_g32_23_b))); //cw_oai21 --EXTRA
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assign cp1_g64_46 = (~(cp1_g32_45_b & (cp1_t32_45_b | cp1_g32_66_b))); //cw_oai21
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assign cp1_t64_03 = (~(cp1_t32_01_b | cp1_t32_23_b)); //cw_nor2
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assign cp1_t64_13 = (~(cp1_t32_11_b | cp1_t32_23_b)); //cw_nor2 --EXTRA
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assign cp1_t64_46 = (~(cp1_g32_45_b & (cp1_t32_45_b | cp1_t32_66_b))); //cw_oai21
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assign cp1_g128_06_b = (~(cp1_g64_03 | (cp1_t64_03 & cp1_g64_46))); //cw_aoi21
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assign cp1_g128_16_b = (~(cp1_g64_13 | (cp1_t64_13 & cp1_g64_46))); //cw_aoi21 --EXTRA
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assign cp1_t128_16_b = (~(cp1_g64_13 | (cp1_t64_13 & cp1_t64_46))); //cw_aoi21 --EXTRA
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assign ex4_g128[1] = (~(cp1_g128_16_b)); //cw_invert --OUTPUT--
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assign cp1_g128_16 = (~(cp1_g128_16_b)); //cw_invert
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assign ex4_g128_b[1] = (~(cp1_g128_16)); //cw_invert --OUTPUT--
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assign ex4_t128[1] = (~(cp1_t128_16_b)); //cw_invert --OUTPUT--
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assign cp1_t128_16 = (~(cp1_t128_16_b)); //cw_invert
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assign ex4_t128_b[1] = (~(cp1_t128_16)); //cw_invert --OUTPUT--
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assign cp1_all1_b = (~ex4_inc_all1); //cw_invert
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assign cp1_all1_p = (~cp1_all1_b); //cw_invert
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assign cp1_co_p0 = (~(cp1_g128_06_b)); //cw_invert
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assign cp1_sel_p0n_x_b = (~(cp1_all1_b & ex4_effsub_npz)); //cw_nand2
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assign cp1_sel_p0n_y_b = (~(cp1_g128_06_b & ex4_effsub_npz)); //cw_nand2
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assign cp1_sel_p0_b = (~(cp1_co_p0 & cp1_all1_p & cp1_sub_sticky)); //cw_nand3
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assign cp1_sel_p1_b = (~(cp1_co_p0 & cp1_all1_p & cp1_sub_stickyn)); //cw_nand3
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assign ex4_eac_sel_p0n[0] = (~(cp1_sel_p0n_x_b & cp1_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p0[0] = (~(cp1_sel_p0_b & cp1_add_frcp0_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p1[0] = (~(cp1_sel_p1_b & cp1_add_frcp1_b)); //cw_nand2 --OUTPUT--
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assign cp1_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
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assign cp1_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
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assign cp1_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
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assign cp1_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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//=#########################################
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//= BYT_1 MSB COPY
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//=#########################################
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assign cp2_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
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assign cp2_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
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assign cp2_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
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assign cp2_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
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assign cp2_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
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assign cp2_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
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assign cp2_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
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assign cp2_t32_66_b = (~(ex4_t16[6])); //cw_invert
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assign cp2_g64_23 = (~(cp2_g32_23_b)); //cw_invert --EXTRA
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assign cp2_g64_03 = (~(cp2_g32_01_b & (cp2_t32_01_b | cp2_g32_23_b))); //cw_oai21
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assign cp2_g64_46 = (~(cp2_g32_45_b & (cp2_t32_45_b | cp2_g32_66_b))); //cw_oai21
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assign cp2_t64_23 = (~(cp2_t32_23_b)); //cw_invert --EXTRA
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assign cp2_t64_03 = (~(cp2_t32_01_b | cp2_t32_23_b)); //cw_nor2
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assign cp2_t64_46 = (~(cp2_g32_45_b & (cp2_t32_45_b | cp2_t32_66_b))); //cw_oai21
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assign cp2_g128_06_b = (~(cp2_g64_03 | (cp2_t64_03 & cp2_g64_46))); //cw_aoi21
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assign cp2_g128_26_b = (~(cp2_g64_23 | (cp2_t64_23 & cp2_g64_46))); //cw_aoi21 --EXTRA
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assign cp2_t128_26_b = (~(cp2_g64_23 | (cp2_t64_23 & cp2_t64_46))); //cw_aoi21 --EXTRA
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assign ex4_g128[2] = (~(cp2_g128_26_b)); //cw_invert --OUTPUT--
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assign cp2_g128_26 = (~(cp2_g128_26_b)); //cw_invert
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assign ex4_g128_b[2] = (~(cp2_g128_26)); //cw_invert --OUTPUT--
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assign ex4_t128[2] = (~(cp2_t128_26_b)); //cw_invert --OUTPUT--
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assign cp2_t128_26 = (~(cp2_t128_26_b)); //cw_invert
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assign ex4_t128_b[2] = (~(cp2_t128_26)); //cw_invert --OUTPUT--
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assign cp2_all1_b = (~ex4_inc_all1); //cw_invert
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assign cp2_all1_p = (~cp2_all1_b); //cw_invert
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assign cp2_co_p0 = (~(cp2_g128_06_b)); //cw_invert
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assign cp2_sel_p0n_x_b = (~(cp2_all1_b & ex4_effsub_npz)); //cw_nand2
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assign cp2_sel_p0n_y_b = (~(cp2_g128_06_b & ex4_effsub_npz)); //cw_nand2
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assign cp2_sel_p0_b = (~(cp2_co_p0 & cp2_all1_p & cp2_sub_sticky)); //cw_nand3
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assign cp2_sel_p1_b = (~(cp2_co_p0 & cp2_all1_p & cp2_sub_stickyn)); //cw_nand3
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assign ex4_eac_sel_p0n[1] = (~(cp2_sel_p0n_x_b & cp2_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p0[1] = (~(cp2_sel_p0_b & cp2_add_frcp0_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p1[1] = (~(cp2_sel_p1_b & cp2_add_frcp1_b)); //cw_nand2 --OUTPUT--
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assign cp2_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
|
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assign cp2_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
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assign cp2_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
|
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assign cp2_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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|
|
//=#########################################
|
|
//= BYT_2 MSB COPY
|
|
//=#########################################
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|
|
|
assign cp3_g32_00_b = (~(ex4_g16[0])); //cw_invert
|
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assign cp3_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
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assign cp3_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
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assign cp3_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
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assign cp3_t32_00_b = (~(ex4_t16[0])); //cw_invert
|
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assign cp3_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
|
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assign cp3_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
|
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assign cp3_t32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_t16[6]))); //cw_aoi21
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assign cp3_g64_02 = (~(cp3_g32_00_b & (cp3_t32_00_b | cp3_g32_12_b))); //cw_oai21
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assign cp3_g64_36 = (~(cp3_g32_34_b & (cp3_t32_34_b | cp3_g32_56_b))); //cw_oai21
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assign cp3_t64_02 = (~(cp3_t32_00_b | cp3_t32_12_b)); //cw_nor2
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assign cp3_t64_36 = (~(cp3_g32_34_b & (cp3_t32_34_b | cp3_t32_56_b))); //cw_oai21
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assign cp3_g128_06_b = (~(cp3_g64_02 | (cp3_t64_02 & cp3_g64_36))); //cw_aoi21
|
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assign cp3_g128_36_b = (~(cp3_g64_36)); //cw_invert --EXTRA
|
|
assign cp3_t128_36_b = (~(cp3_t64_36)); //cw_invert --EXTRA
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|
assign ex4_g128[3] = (~(cp3_g128_36_b)); //cw_invert --OUTPUT--
|
|
assign cp3_g128_36 = (~(cp3_g128_36_b)); //cw_invert
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assign ex4_g128_b[3] = (~(cp3_g128_36)); //cw_invert --OUTPUT--
|
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assign ex4_t128[3] = (~(cp3_t128_36_b)); //cw_invert --OUTPUT--
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assign cp3_t128_36 = (~(cp3_t128_36_b)); //cw_invert
|
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assign ex4_t128_b[3] = (~(cp3_t128_36)); //cw_invert --OUTPUT--
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|
assign cp3_all1_b = (~ex4_inc_all1); //cw_invert
|
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assign cp3_all1_p = (~cp3_all1_b); //cw_invert
|
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assign cp3_co_p0 = (~(cp3_g128_06_b)); //cw_invert
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|
assign cp3_sel_p0n_x_b = (~(cp3_all1_b & ex4_effsub_npz)); //cw_nand2
|
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assign cp3_sel_p0n_y_b = (~(cp3_g128_06_b & ex4_effsub_npz)); //cw_nand2
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assign cp3_sel_p0_b = (~(cp3_co_p0 & cp3_all1_p & cp3_sub_sticky)); //cw_nand3
|
|
assign cp3_sel_p1_b = (~(cp3_co_p0 & cp3_all1_p & cp3_sub_stickyn)); //cw_nand3
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|
assign ex4_eac_sel_p0n[2] = (~(cp3_sel_p0n_x_b & cp3_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
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|
assign ex4_eac_sel_p0[2] = (~(cp3_sel_p0_b & cp3_add_frcp0_b)); //cw_nand2 --OUTPUT--
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|
assign ex4_eac_sel_p1[2] = (~(cp3_sel_p1_b & cp3_add_frcp1_b)); //cw_nand2 --OUTPUT--
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|
|
|
assign cp3_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
|
|
assign cp3_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
|
|
assign cp3_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
|
|
assign cp3_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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|
|
//=#########################################
|
|
//= BYT_3 MSB COPY
|
|
//=#########################################
|
|
|
|
assign cp4_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21
|
|
assign cp4_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21
|
|
assign cp4_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21
|
|
assign cp4_g32_66_b = (~(ex4_g16[6])); //cw_invert --done
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|
assign cp4_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2
|
|
assign cp4_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2
|
|
assign cp4_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2
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|
assign cp4_t32_66_b = (~(ex4_t16[6])); //cw_invert
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|
assign cp4_g64_03 = (~(cp4_g32_01_b & (cp4_t32_01_b | cp4_g32_23_b))); //cw_oai21
|
|
assign cp4_g64_46 = (~(cp4_g32_45_b & (cp4_t32_45_b | cp4_g32_66_b))); //cw_oai21
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|
assign cp4_t64_03 = (~(cp4_t32_01_b | cp4_t32_23_b)); //cw_nor2
|
|
assign cp4_t64_46 = (~(cp4_g32_45_b & (cp4_t32_45_b | cp4_t32_66_b))); //cw_oai21
|
|
|
|
assign cp4_g128_06_b = (~(cp4_g64_03 | (cp4_t64_03 & cp4_g64_46))); //cw_aoi21
|
|
assign cp4_g128_46_b = (~(cp4_g64_46)); //cw_invert --EXTRA
|
|
assign cp4_t128_46_b = (~(cp4_t64_46)); //cw_invert --EXTRA
|
|
|
|
assign ex4_g128[4] = (~(cp4_g128_46_b)); //cw_invert --OUTPUT--
|
|
assign cp4_g128_46 = (~(cp4_g128_46_b)); //cw_invert
|
|
assign ex4_g128_b[4] = (~(cp4_g128_46)); //cw_invert --OUTPUT--
|
|
assign ex4_t128[4] = (~(cp4_t128_46_b)); //cw_invert --OUTPUT--
|
|
assign cp4_t128_46 = (~(cp4_t128_46_b)); //cw_invert
|
|
assign ex4_t128_b[4] = (~(cp4_t128_46)); //cw_invert --OUTPUT--
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|
|
|
assign cp4_all1_b = (~ex4_inc_all1); //cw_invert
|
|
assign cp4_all1_p = (~cp4_all1_b); //cw_invert
|
|
assign cp4_co_p0 = (~(cp4_g128_06_b)); //cw_invert
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|
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|
assign cp4_sel_p0n_x_b = (~(cp4_all1_b & ex4_effsub_npz)); //cw_nand2
|
|
assign cp4_sel_p0n_y_b = (~(cp4_g128_06_b & ex4_effsub_npz)); //cw_nand2
|
|
assign cp4_sel_p0_b = (~(cp4_co_p0 & cp4_all1_p & cp4_sub_sticky)); //cw_nand3
|
|
assign cp4_sel_p1_b = (~(cp4_co_p0 & cp4_all1_p & cp4_sub_stickyn)); //cw_nand3
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|
assign ex4_eac_sel_p0n[3] = (~(cp4_sel_p0n_x_b & cp4_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
|
|
assign ex4_eac_sel_p0[3] = (~(cp4_sel_p0_b & cp4_add_frcp0_b)); //cw_nand2 --OUTPUT--
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|
assign ex4_eac_sel_p1[3] = (~(cp4_sel_p1_b & cp4_add_frcp1_b)); //cw_nand2 --OUTPUT--
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|
|
|
assign cp4_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
|
|
assign cp4_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
|
|
assign cp4_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
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assign cp4_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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//=#########################################
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//= BYT_4
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//=#########################################
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assign cp5_g32_00_b = (~(ex4_g16[0])); //cw_invert
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assign cp5_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
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assign cp5_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
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assign cp5_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
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assign cp5_t32_00_b = (~(ex4_t16[0])); //cw_invert
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assign cp5_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
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assign cp5_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
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assign cp5_t32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_t16[6]))); //cw_aoi21
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assign cp5_g64_02 = (~(cp5_g32_00_b & (cp5_t32_00_b | cp5_g32_12_b))); //cw_oai21
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assign cp5_g64_36 = (~(cp5_g32_34_b & (cp5_t32_34_b | cp5_g32_56_b))); //cw_oai21
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assign cp5_g64_56 = (~(cp5_g32_56_b)); //cw_invert --EXTRA
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assign cp5_t64_02 = (~(cp5_t32_00_b | cp5_t32_12_b)); //cw_nor2
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assign cp5_t64_56 = (~(cp5_t32_56_b)); //cw_invert --EXTRA
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assign cp5_g128_06_b = (~(cp5_g64_02 | (cp5_t64_02 & cp5_g64_36))); //cw_aoi21
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assign cp5_g128_56_b = (~(cp5_g64_56)); //cw_invert --EXTRA
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assign cp5_t128_56_b = (~(cp5_t64_56)); //cw_invert --EXTRA
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assign ex4_g128[5] = (~(cp5_g128_56_b)); //cw_invert --OUTPUT--
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assign cp5_g128_56 = (~(cp5_g128_56_b)); //cw_invert
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assign ex4_g128_b[5] = (~(cp5_g128_56)); //cw_invert --OUTPUT--
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assign ex4_t128[5] = (~(cp5_t128_56_b)); //cw_invert --OUTPUT--
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assign cp5_t128_56 = (~(cp5_t128_56_b)); //cw_invert
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assign ex4_t128_b[5] = (~(cp5_t128_56)); //cw_invert --OUTPUT--
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assign cp5_all1_b = (~ex4_inc_all1); //cw_invert
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assign cp5_all1_p = (~cp5_all1_b); //cw_invert
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assign cp5_co_p0 = (~(cp5_g128_06_b)); //cw_invert
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assign cp5_sel_p0n_x_b = (~(cp5_all1_b & ex4_effsub_npz)); //cw_nand2
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assign cp5_sel_p0n_y_b = (~(cp5_g128_06_b & ex4_effsub_npz)); //cw_nand2
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assign cp5_sel_p0_b = (~(cp5_co_p0 & cp5_all1_p & cp5_sub_sticky)); //cw_nand3
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assign cp5_sel_p1_b = (~(cp5_co_p0 & cp5_all1_p & cp5_sub_stickyn)); //cw_nand3
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assign ex4_eac_sel_p0n[4] = (~(cp5_sel_p0n_x_b & cp5_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p0[4] = (~(cp5_sel_p0_b & cp5_add_frcp0_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p1[4] = (~(cp5_sel_p1_b & cp5_add_frcp1_b)); //cw_nand2 --OUTPUT--
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assign cp5_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
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assign cp5_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
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assign cp5_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
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assign cp5_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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//=#########################################
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//= BYT_5
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//=#########################################
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assign cp6_g32_00_b = (~(ex4_g16[0])); //cw_invert
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assign cp6_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
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assign cp6_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
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assign cp6_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
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assign cp6_g32_66_b = (~(ex4_g16[6])); //cw_invert EXTRA
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assign cp6_t32_00_b = (~(ex4_t16[0])); //cw_invert
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assign cp6_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
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assign cp6_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
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assign cp6_t32_66_b = (~(ex4_t16[6])); //cw_invert EXTRA
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assign cp6_g64_02 = (~(cp6_g32_00_b & (cp6_t32_00_b | cp6_g32_12_b))); //cw_oai21
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assign cp6_g64_36 = (~(cp6_g32_34_b & (cp6_t32_34_b | cp6_g32_56_b))); //cw_oai21
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assign cp6_t64_02 = (~(cp6_t32_00_b | cp6_t32_12_b)); //cw_nor2
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assign cp6_g128_06_b = (~(cp6_g64_02 | (cp6_t64_02 & cp6_g64_36))); //cw_aoi21
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assign ex4_g128[6] = (~(cp6_g32_66_b)); //cw_invert --OUTPUT--
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assign cp6_g128_66 = (~(cp6_g32_66_b)); //cw_invert
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assign ex4_g128_b[6] = (~(cp6_g128_66)); //cw_invert --OUTPUT--
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assign ex4_t128[6] = (~(cp6_t32_66_b)); //cw_invert --OUTPUT--
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assign cp6_t128_66 = (~(cp6_t32_66_b)); //cw_invert
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assign ex4_t128_b[6] = (~(cp6_t128_66)); //cw_invert --OUTPUT--
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assign cp6_all1_b = (~ex4_inc_all1); //cw_invert
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assign cp6_all1_p = (~cp6_all1_b); //cw_invert
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assign cp6_co_p0 = (~(cp6_g128_06_b)); //cw_invert
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assign cp6_sel_p0n_x_b = (~(cp6_all1_b & ex4_effsub_npz)); //cw_nand2
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assign cp6_sel_p0n_y_b = (~(cp6_g128_06_b & ex4_effsub_npz)); //cw_nand2
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assign cp6_sel_p0_b = (~(cp6_co_p0 & cp6_all1_p & cp6_sub_sticky)); //cw_nand3
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assign cp6_sel_p1_b = (~(cp6_co_p0 & cp6_all1_p & cp6_sub_stickyn)); //cw_nand3
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assign ex4_eac_sel_p0n[5] = (~(cp6_sel_p0n_x_b & cp6_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p0[5] = (~(cp6_sel_p0_b & cp6_add_frcp0_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p1[5] = (~(cp6_sel_p1_b & cp6_add_frcp1_b)); //cw_nand2 --OUTPUT--
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assign cp6_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
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assign cp6_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
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assign cp6_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
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assign cp6_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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//=#########################################
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//= BYT_6 LSB COPY
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//=#########################################
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assign cp7_g32_00_b = (~(ex4_g16[0])); //cw_invert
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assign cp7_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21
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assign cp7_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21
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assign cp7_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21
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assign cp7_t32_00_b = (~(ex4_t16[0])); //cw_invert
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assign cp7_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2
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assign cp7_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2
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assign cp7_g64_02 = (~(cp7_g32_00_b & (cp7_t32_00_b | cp7_g32_12_b))); //cw_oai21
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assign cp7_g64_36 = (~(cp7_g32_34_b & (cp7_t32_34_b | cp7_g32_56_b))); //cw_oai21
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assign cp7_t64_02 = (~(cp7_t32_00_b | cp7_t32_12_b)); //cw_nor2
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assign cp7_g128_06_b = (~(cp7_g64_02 | (cp7_t64_02 & cp7_g64_36))); //cw_aoi21
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assign cp7_all1_b = (~ex4_inc_all1); //cw_invert
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assign cp7_all1_p = (~cp7_all1_b); //cw_invert
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assign cp7_co_p0 = (~(cp7_g128_06_b)); //cw_invert
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assign cp7_sel_p0n_x_b = (~(cp7_all1_b & ex4_effsub_npz)); //cw_nand2
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assign cp7_sel_p0n_y_b = (~(cp7_g128_06_b & ex4_effsub_npz)); //cw_nand2
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assign cp7_sel_p0_b = (~(cp7_co_p0 & cp7_all1_p & cp7_sub_sticky)); //cw_nand3
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assign cp7_sel_p1_b = (~(cp7_co_p0 & cp7_all1_p & cp7_sub_stickyn)); //cw_nand3
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assign ex4_eac_sel_p0n[6] = (~(cp7_sel_p0n_x_b & cp7_sel_p0n_y_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p0[6] = (~(cp7_sel_p0_b & cp7_add_frcp0_b)); //cw_nand2 --OUTPUT--
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assign ex4_eac_sel_p1[6] = (~(cp7_sel_p1_b & cp7_add_frcp1_b)); //cw_nand2 --OUTPUT--
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assign cp7_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED
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assign cp7_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED
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assign cp7_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED
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assign cp7_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED
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endmodule
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