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194 lines
3.9 KiB
Verilog
194 lines
3.9 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: XU Population Count - Word Phase
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//
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//*****************************************************************************
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module tri_st_popcnt_word(
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b0,
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b1,
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b2,
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b3,
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y,
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vdd,
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gnd
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);
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input [0:3] b0;
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input [0:3] b1;
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input [0:3] b2;
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input [0:3] b3;
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output [0:5] y;
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inout vdd;
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inout gnd;
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wire [0:0] s0;
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wire [0:1] c1;
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wire [0:1] s1;
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wire [0:2] c2;
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wire [0:1] s2;
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wire [0:2] c3;
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wire [0:1] s3;
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wire [0:2] c4;
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// Level 0
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tri_csa32 csa_l0_0(
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.vd(vdd),
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.gd(gnd),
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.a(b0[0]),
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.b(b0[1]),
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.c(b0[2]),
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.sum(s0[0]),
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.car(c1[0])
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);
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tri_csa22 csa_l0_1(
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.a(b0[3]),
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.b(s0[0]),
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.sum(y[5]),
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.car(c1[1])
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);
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// Level 1
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tri_csa32 csa_l1_0(
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.vd(vdd),
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.gd(gnd),
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.a(b1[0]),
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.b(b1[1]),
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.c(b1[2]),
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.sum(s1[0]),
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.car(c2[0])
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);
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tri_csa32 csa_l1_1(
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.vd(vdd),
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.gd(gnd),
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.a(b1[3]),
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.b(c1[0]),
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.c(c1[1]),
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.sum(s1[1]),
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.car(c2[1])
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);
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tri_csa22 csa_l1_2(
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.a(s1[0]),
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.b(s1[1]),
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.sum(y[4]),
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.car(c2[2])
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);
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// Level 2
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tri_csa32 csa_l2_0(
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.vd(vdd),
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.gd(gnd),
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.a(b2[0]),
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.b(b2[1]),
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.c(b2[2]),
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.sum(s2[0]),
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.car(c3[0])
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);
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tri_csa32 csa_l2_1(
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.vd(vdd),
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.gd(gnd),
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.a(b2[3]),
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.b(c2[0]),
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.c(c2[1]),
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.sum(s2[1]),
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.car(c3[1])
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);
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tri_csa32 csa_l2_2(
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.vd(vdd),
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.gd(gnd),
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.a(c2[2]),
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.b(s2[0]),
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.c(s2[1]),
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.sum(y[3]),
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.car(c3[2])
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);
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// Level 3
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tri_csa32 csa_l3_0(
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.vd(vdd),
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.gd(gnd),
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.a(b3[0]),
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.b(b3[1]),
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.c(b3[2]),
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.sum(s3[0]),
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.car(c4[0])
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);
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tri_csa32 csa_l3_1(
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.vd(vdd),
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.gd(gnd),
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.a(b3[3]),
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.b(c3[0]),
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.c(c3[1]),
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.sum(s3[1]),
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.car(c4[1])
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);
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tri_csa32 csa_l3_2(
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.vd(vdd),
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.gd(gnd),
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.a(c3[2]),
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.b(s3[0]),
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.c(s3[1]),
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.sum(y[2]),
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.car(c4[2])
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);
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// Level 4
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tri_csa32 csa_l4_0(
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.vd(vdd),
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.gd(gnd),
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.a(c4[0]),
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.b(c4[1]),
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.c(c4[2]),
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.sum(y[1]),
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.car(y[0])
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);
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endmodule
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