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92 lines
3.5 KiB
Verilog
92 lines
3.5 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_regs.v
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// *! DESCRIPTION : Multi-bit scan-only latch, LCB included
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_regs(
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vd,
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gd,
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nclk,
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force_t,
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thold_b,
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delay_lclkr,
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scin,
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scout,
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dout
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);
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parameter WIDTH = 4;
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parameter OFFSET = 0; //starting bit
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parameter INIT = 0; // will be converted to the least signficant
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// 31 bits of init_v
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parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
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parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius
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parameter NEEDS_SRESET = 1; // for inferred latches
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parameter DOMAIN_CROSSING = 0;
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inout vd;
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inout gd;
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input [0:`NCLK_WIDTH-1] nclk;
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input force_t; // 1: force LCB active
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input thold_b; // 1: functional, 0: no clock
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input delay_lclkr; // 0: functional
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input [OFFSET:OFFSET+WIDTH-1] scin; // scan in
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output [OFFSET:OFFSET+WIDTH-1] scout;
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output [OFFSET:OFFSET+WIDTH-1] dout;
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parameter [0:WIDTH-1] init_v = INIT;
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generate
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wire sreset;
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reg [0:WIDTH-1] int_dout;
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(* analysis_not_referenced="true" *)
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wire unused;
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assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0;
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always @(posedge nclk[0]) begin: l
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if (sreset)
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int_dout <= init_v;
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end
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assign dout = (IBUF == 1'b1) ? ~int_dout : int_dout;
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assign scout = {WIDTH{1'b0}};
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assign unused = |{vd, gd, delay_lclkr, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]);
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endgenerate
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endmodule
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