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80 lines
3.0 KiB
Verilog
80 lines
3.0 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: XU Bit Permute
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//
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//*****************************************************************************
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module xu0_bprm(
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a,
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s,
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y
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);
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// IOs
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input [0:63] a;
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input [0:7] s;
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output y;
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// Signals
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wire [0:7] mh;
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wire [0:7] ml;
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wire [0:63] a1;
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wire [0:63] a2;
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assign mh[0:7] = (s[0:4] == 5'b00000) ? 8'b10000000 :
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(s[0:4] == 5'b00001) ? 8'b01000000 :
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(s[0:4] == 5'b00010) ? 8'b00100000 :
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(s[0:4] == 5'b00011) ? 8'b00010000 :
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(s[0:4] == 5'b00100) ? 8'b00001000 :
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(s[0:4] == 5'b00101) ? 8'b00000100 :
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(s[0:4] == 5'b00110) ? 8'b00000010 :
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(s[0:4] == 5'b00111) ? 8'b00000001 :
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8'b00000000 ;
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assign ml[0:7] = (s[5:7] == 3'b000) ? 8'b10000000 :
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(s[5:7] == 3'b001) ? 8'b01000000 :
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(s[5:7] == 3'b010) ? 8'b00100000 :
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(s[5:7] == 3'b011) ? 8'b00010000 :
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(s[5:7] == 3'b100) ? 8'b00001000 :
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(s[5:7] == 3'b101) ? 8'b00000100 :
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(s[5:7] == 3'b110) ? 8'b00000010 :
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8'b00000001;
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genvar i;
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generate for (i=0; i<=7; i=i+1)
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begin : msk
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assign a1[8*i:8*i+7] = a[8*i:8*i+7] & ml[0:7];
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assign a2[8*i:8*i+7] = a1[8*i:8*i+7] & {8{mh[i]}};
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end
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endgenerate
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assign y = |a2;
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endmodule
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