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444 lines
19 KiB
Verilog
444 lines
19 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: Pervasive Core Debug/Event Bus Controls
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module pcq_dbg(
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// Include model build parameters
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`include "tri_a2o.vh"
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inout vdd,
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inout gnd,
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input [0:`NCLK_WIDTH-1] nclk,
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input scan_dis_dc_b,
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input lcb_clkoff_dc_b,
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input lcb_mpw1_dc_b,
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input lcb_mpw2_dc_b,
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input lcb_delay_lclkr_dc,
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input lcb_act_dis_dc,
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input pc_pc_func_slp_sl_thold_0,
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input pc_pc_sg_0,
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input func_scan_in,
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output func_scan_out,
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// Trace/Trigger Bus
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output [0:31] debug_bus_out,
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input [0:31] debug_bus_in,
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input rg_db_trace_bus_enable,
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input [0:10] rg_db_debug_mux_ctrls,
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input [0:3] coretrace_ctrls_in,
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output [0:3] coretrace_ctrls_out,
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//PC Unit internal debug signals
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input [0:11] rg_db_dbg_scom,
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input [0:24] rg_db_dbg_thrctls,
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input [0:15] rg_db_dbg_ram,
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input [0:27] rg_db_dbg_fir0_err,
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input [0:19] rg_db_dbg_fir1_err,
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input [0:19] rg_db_dbg_fir2_err,
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input [0:14] rg_db_dbg_fir_misc,
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input [0:14] ct_db_dbg_ctrls,
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input [0:7] rg_db_dbg_spr
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);
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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parameter RAMCTRL_SIZE = 2;
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parameter SCMISC_SIZE = 7;
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parameter FIRMISC_SIZE = 2;
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parameter TRACEOUT_SIZE = 32;
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parameter CORETRACE_SIZE = 4;
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//---------------------------------------------------------------------
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// Scan Ring Ordering:
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// start of func scan chain ordering
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parameter RAMCTRL_OFFSET = 0;
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parameter SCMISC_OFFSET = RAMCTRL_OFFSET + RAMCTRL_SIZE;
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parameter FIRMISC_OFFSET = SCMISC_OFFSET + SCMISC_SIZE;
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parameter TRACEOUT_OFFSET = FIRMISC_OFFSET + FIRMISC_SIZE;
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parameter CORETRACE_OFFSET = TRACEOUT_OFFSET + TRACEOUT_SIZE;
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parameter FUNC_RIGHT = CORETRACE_OFFSET + CORETRACE_SIZE - 1;
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// end of func scan chain ordering
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//---------------------------------------------------------------------
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// Basic/Misc signals
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wire [0:FUNC_RIGHT] func_siv;
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wire [0:FUNC_RIGHT] func_sov;
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wire pc_pc_func_slp_sl_thold_0_b;
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wire force_func;
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// Trace/Trigger/Event Mux signals
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wire [0:TRACEOUT_SIZE-1] debug_group_0;
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wire [0:TRACEOUT_SIZE-1] debug_group_1;
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wire [0:TRACEOUT_SIZE-1] debug_group_2;
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wire [0:TRACEOUT_SIZE-1] debug_group_3;
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wire [0:TRACEOUT_SIZE-1] debug_group_4;
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wire [0:TRACEOUT_SIZE-1] debug_group_5;
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wire [0:TRACEOUT_SIZE-1] debug_group_6;
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wire [0:TRACEOUT_SIZE-1] debug_group_7;
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// Trace/Trigger input signals
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wire [0:31] fir0_errors_q;
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wire [0:31] fir1_errors_q;
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wire [0:31] fir2_errors_q;
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wire [0:2] fir_xstop_err_q;
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wire [0:2] fir_lxstop_err_q;
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wire [0:2] fir_recov_err_q;
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wire fir0_recov_err_pulse_q;
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wire fir1_recov_err_pulse_q;
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wire fir2_recov_err_pulse_q;
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wire fir_block_ram_mode_q;
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wire [0:1] fir_xstop_per_thread_d;
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wire [0:1] fir_xstop_per_thread_q;
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//
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wire scmisc_sc_act_d;
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wire scmisc_sc_act_q;
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wire scmisc_sc_req_q;
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wire scmisc_sc_wr_q;
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wire [0:5] scmisc_scaddr_predecode_d;
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wire [0:5] scmisc_scaddr_predecode_q;
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wire scmisc_scaddr_nvld_q;
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wire scmisc_sc_wr_nvld_q;
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wire scmisc_sc_rd_nvld_q;
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//
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wire ram_mode_q;
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wire [0:1] ram_active_q;
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wire ram_execute_q;
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wire ram_msrovren_q;
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wire ram_msrovrpr_q;
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wire ram_msrovrgs_q;
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wire ram_msrovrde_q;
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wire ram_unsupported_q;
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wire ram_instr_overrun_d;
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wire ram_instr_overrun_q;
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wire ram_interrupt_q;
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wire ram_mode_xstop_d;
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wire ram_mode_xstop_q;
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wire ram_done_q;
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wire ram_xu_ram_data_val_q;
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wire ram_fu_ram_data_val_q;
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wire ram_lq_ram_data_val_q;
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//
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wire regs_xstop_report_ovrid;
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wire regs_dis_pwr_savings;
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wire regs_dis_overrun_chks;
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wire regs_maxRecErrCntrValue;
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wire regs_ext_debug_stop_q;
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wire [0:1] regs_spattn_data_q;
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wire [0:1] regs_power_managed_q;
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wire [0:1] regs_pm_thread_stop_q;
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wire [0:1] regs_stop_dbg_event_q;
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wire [0:1] regs_stop_dbg_dnh_q;
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wire [0:1] regs_tx_stop_q;
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wire [0:1] regs_thread_running_q;
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wire [0:1] regs_tx_step_q;
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wire [0:1] regs_tx_step_done_q;
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wire [0:1] regs_tx_step_req_q;
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//
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wire ctrls_pmstate_q_anded;
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wire ctrls_pmstate_all_q;
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wire ctrls_power_managed_q;
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wire ctrls_pm_rvwinkled_q;
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wire [0:7] ctrls_pmclkctrl_dly_q;
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wire ctrls_dis_pwr_sav_q;
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wire ctrls_ccflush_dis_q;
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wire ctrls_raise_tholds_q;
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//
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wire spr_cesr1_wren;
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wire spr_sramd_wren;
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wire [0:1] spr_perfmon_alert_q;
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wire [0:1] spr_cesr1_is0_l2;
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wire [0:1] spr_cesr1_is1_l2;
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// Latch definitions begin
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wire [0:TRACEOUT_SIZE-1] trace_data_out_d;
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wire [0:TRACEOUT_SIZE-1] trace_data_out_q;
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wire [0:3] coretrace_ctrls_out_d;
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wire [0:3] coretrace_ctrls_out_q;
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//=====================================================================
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// Trace/Trigger Bus - Sort out input debug signals
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//=====================================================================
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// FIR/Error related signals.
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assign fir0_errors_q[0:31] = {rg_db_dbg_fir0_err, { 4 {1'b0}} };
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assign fir1_errors_q[0:31] = {rg_db_dbg_fir1_err, {12 {1'b0}} };
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assign fir2_errors_q[0:31] = {rg_db_dbg_fir2_err, {12 {1'b0}} };
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assign fir_xstop_err_q = rg_db_dbg_fir_misc[0:2];
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assign fir_lxstop_err_q = rg_db_dbg_fir_misc[3:5];
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assign fir_recov_err_q = rg_db_dbg_fir_misc[6:8];
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assign fir0_recov_err_pulse_q = rg_db_dbg_fir_misc[9];
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assign fir1_recov_err_pulse_q = rg_db_dbg_fir_misc[10];
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assign fir2_recov_err_pulse_q = rg_db_dbg_fir_misc[11];
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assign fir_block_ram_mode_q = rg_db_dbg_fir_misc[12];
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assign fir_xstop_per_thread_d = rg_db_dbg_fir_misc[13:14];
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// SCOM error; control signals
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assign scmisc_sc_act_d = rg_db_dbg_scom[0];
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assign scmisc_sc_req_q = rg_db_dbg_scom[1];
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assign scmisc_sc_wr_q = rg_db_dbg_scom[2];
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assign scmisc_scaddr_predecode_d = rg_db_dbg_scom[3:8];
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assign scmisc_scaddr_nvld_q = rg_db_dbg_scom[9];
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assign scmisc_sc_wr_nvld_q = rg_db_dbg_scom[10];
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assign scmisc_sc_rd_nvld_q = rg_db_dbg_scom[11];
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// RAM control signals
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assign ram_mode_q = rg_db_dbg_ram[0];
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assign ram_active_q = rg_db_dbg_ram[1:2];
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assign ram_execute_q = rg_db_dbg_ram[3];
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assign ram_msrovren_q = rg_db_dbg_ram[4];
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assign ram_msrovrpr_q = rg_db_dbg_ram[5];
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assign ram_msrovrgs_q = rg_db_dbg_ram[6];
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assign ram_msrovrde_q = rg_db_dbg_ram[7];
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assign ram_unsupported_q = rg_db_dbg_ram[8];
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assign ram_instr_overrun_d = rg_db_dbg_ram[9];
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assign ram_interrupt_q = rg_db_dbg_ram[10];
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assign ram_mode_xstop_d = rg_db_dbg_ram[11];
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assign ram_done_q = rg_db_dbg_ram[12];
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assign ram_xu_ram_data_val_q = rg_db_dbg_ram[13];
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assign ram_fu_ram_data_val_q = rg_db_dbg_ram[14];
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assign ram_lq_ram_data_val_q = rg_db_dbg_ram[15];
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// THRCTL and misc control signals
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assign regs_xstop_report_ovrid = rg_db_dbg_thrctls[0];
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assign regs_dis_pwr_savings = rg_db_dbg_thrctls[1];
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assign regs_dis_overrun_chks = rg_db_dbg_thrctls[2];
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assign regs_maxRecErrCntrValue = rg_db_dbg_thrctls[3];
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assign regs_ext_debug_stop_q = rg_db_dbg_thrctls[4];
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assign regs_spattn_data_q = rg_db_dbg_thrctls[5:6];
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assign regs_power_managed_q = rg_db_dbg_thrctls[7:8];
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assign regs_pm_thread_stop_q = rg_db_dbg_thrctls[9:10];
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assign regs_stop_dbg_event_q = rg_db_dbg_thrctls[11:12];
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assign regs_stop_dbg_dnh_q = rg_db_dbg_thrctls[13:14];
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assign regs_tx_stop_q = rg_db_dbg_thrctls[15:16];
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assign regs_thread_running_q = rg_db_dbg_thrctls[17:18];
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assign regs_tx_step_q = rg_db_dbg_thrctls[19:20];
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assign regs_tx_step_done_q = rg_db_dbg_thrctls[21:22];
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assign regs_tx_step_req_q = rg_db_dbg_thrctls[23:24];
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// Power Management signals
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assign ctrls_pmstate_q_anded = ct_db_dbg_ctrls[0];
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assign ctrls_pmstate_all_q = ct_db_dbg_ctrls[1];
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assign ctrls_power_managed_q = ct_db_dbg_ctrls[2];
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assign ctrls_pm_rvwinkled_q = ct_db_dbg_ctrls[3];
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assign ctrls_pmclkctrl_dly_q = ct_db_dbg_ctrls[4:11];
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assign ctrls_dis_pwr_sav_q = ct_db_dbg_ctrls[12];
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assign ctrls_ccflush_dis_q = ct_db_dbg_ctrls[13];
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assign ctrls_raise_tholds_q = ct_db_dbg_ctrls[14];
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// SPRs signals
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assign spr_cesr1_wren = rg_db_dbg_spr[0];
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assign spr_sramd_wren = rg_db_dbg_spr[1];
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assign spr_perfmon_alert_q = rg_db_dbg_spr[2:3];
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assign spr_cesr1_is0_l2 = rg_db_dbg_spr[4:5];
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assign spr_cesr1_is1_l2 = rg_db_dbg_spr[6:7];
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//=====================================================================
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// Trace/Trigger Bus - Form trace bus groups from input debug signals
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//=====================================================================
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// FIR0[32:59] errors not connected: max_recov_err_cntr_value (32), spare (59)
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// FIR1[32:51] errors not connected: wdt_reset (45), debug_event (46), spare (47:51)
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// FIR2[32:51] errors not connected: wdt_reset (45), debug_event (46), spare (47:51)
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assign debug_group_0[0:TRACEOUT_SIZE-1] = { fir0_errors_q[0:31] }; // 0:31
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assign debug_group_1[0:TRACEOUT_SIZE-1] = { fir1_errors_q[0:31] }; // 0:31
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assign debug_group_2[0:TRACEOUT_SIZE-1] = { fir2_errors_q[0:31] }; // 0:31
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assign debug_group_3[0:TRACEOUT_SIZE-1] = {
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fir_recov_err_q[0:2], fir_xstop_err_q[0:2], fir_lxstop_err_q[0:2], fir_xstop_per_thread_q[0:1], // 0:15
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fir_block_ram_mode_q, fir0_recov_err_pulse_q, fir1_recov_err_pulse_q, fir2_recov_err_pulse_q,
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scmisc_sc_act_q, scmisc_sc_req_q, scmisc_sc_wr_q, scmisc_scaddr_nvld_q, // 16:31
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scmisc_sc_wr_nvld_q, scmisc_sc_rd_nvld_q, scmisc_scaddr_predecode_q[0:5], 5'b00000
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};
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assign debug_group_4[0:TRACEOUT_SIZE-1] = {
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regs_maxRecErrCntrValue, regs_xstop_report_ovrid, regs_spattn_data_q[0:1], // 0:15
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regs_ext_debug_stop_q, regs_stop_dbg_event_q[0:1], regs_stop_dbg_dnh_q[0:1],
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regs_pm_thread_stop_q[0:1], regs_thread_running_q[0:1], regs_power_managed_q[0:1],
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regs_dis_pwr_savings,
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regs_tx_stop_q[0:1], regs_tx_step_q[0:1], regs_tx_step_done_q[0:1], regs_tx_step_req_q[0:1], // 16:31
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spr_perfmon_alert_q[0:1], spr_cesr1_is0_l2[0:1], spr_cesr1_is1_l2[0:1],
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spr_sramd_wren, spr_cesr1_wren
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};
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assign debug_group_5[0:TRACEOUT_SIZE-1] = {
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ctrls_pmstate_q_anded, ctrls_pmstate_all_q, ctrls_power_managed_q, ctrls_pm_rvwinkled_q, // 0:15
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ctrls_pmclkctrl_dly_q[0:7], ctrls_dis_pwr_sav_q, ctrls_ccflush_dis_q, ctrls_raise_tholds_q,
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regs_dis_overrun_chks,
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ram_mode_q, ram_active_q[0:1], ram_execute_q, ram_done_q, ram_xu_ram_data_val_q, // 16:31
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ram_fu_ram_data_val_q, ram_lq_ram_data_val_q, ram_msrovren_q, ram_msrovrpr_q, ram_msrovrgs_q,
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ram_msrovrde_q, ram_unsupported_q, ram_instr_overrun_q, ram_interrupt_q, ram_mode_xstop_q
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};
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assign debug_group_6[0:TRACEOUT_SIZE-1] = { {32 {1'b0}} };
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assign debug_group_7[0:TRACEOUT_SIZE-1] = { {32 {1'b0}} };
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//=====================================================================
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// Trace Bus Mux
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//=====================================================================
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tri_debug_mux8 debug_mux(
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.select_bits(rg_db_debug_mux_ctrls),
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.dbg_group0(debug_group_0),
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.dbg_group1(debug_group_1),
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.dbg_group2(debug_group_2),
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.dbg_group3(debug_group_3),
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.dbg_group4(debug_group_4),
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.dbg_group5(debug_group_5),
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.dbg_group6(debug_group_6),
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.dbg_group7(debug_group_7),
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.trace_data_in(debug_bus_in),
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.trace_data_out(trace_data_out_d),
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.coretrace_ctrls_in(coretrace_ctrls_in),
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.coretrace_ctrls_out(coretrace_ctrls_out_d)
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);
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//=====================================================================
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// Outputs
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//=====================================================================
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assign debug_bus_out = trace_data_out_q;
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assign coretrace_ctrls_out = coretrace_ctrls_out_q;
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//=====================================================================
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// Latches
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//=====================================================================
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// func ring registers start
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tri_rlmreg_p #(.WIDTH(RAMCTRL_SIZE), .INIT(0)) ramctrl(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(rg_db_trace_bus_enable),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_func),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[RAMCTRL_OFFSET:RAMCTRL_OFFSET + RAMCTRL_SIZE - 1]),
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.scout(func_sov[RAMCTRL_OFFSET:RAMCTRL_OFFSET + RAMCTRL_SIZE - 1]),
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.din( {ram_instr_overrun_d, ram_mode_xstop_d}),
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.dout({ram_instr_overrun_q, ram_mode_xstop_q})
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);
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tri_rlmreg_p #(.WIDTH(SCMISC_SIZE), .INIT(0)) scmisc(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(rg_db_trace_bus_enable),
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.thold_b(pc_pc_func_slp_sl_thold_0_b),
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.sg(pc_pc_sg_0),
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.force_t(force_func),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.scin(func_siv[SCMISC_OFFSET:SCMISC_OFFSET + SCMISC_SIZE - 1]),
|
|
.scout(func_sov[SCMISC_OFFSET:SCMISC_OFFSET + SCMISC_SIZE - 1]),
|
|
.din( {scmisc_sc_act_d, scmisc_scaddr_predecode_d}),
|
|
.dout({scmisc_sc_act_q, scmisc_scaddr_predecode_q})
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(FIRMISC_SIZE), .INIT(0)) firmisc(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rg_db_trace_bus_enable),
|
|
.thold_b(pc_pc_func_slp_sl_thold_0_b),
|
|
.sg(pc_pc_sg_0),
|
|
.force_t(force_func),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.scin(func_siv[FIRMISC_OFFSET:FIRMISC_OFFSET + FIRMISC_SIZE - 1]),
|
|
.scout(func_sov[FIRMISC_OFFSET:FIRMISC_OFFSET + FIRMISC_SIZE - 1]),
|
|
.din( fir_xstop_per_thread_d),
|
|
.dout(fir_xstop_per_thread_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(TRACEOUT_SIZE), .INIT(0)) traceout(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rg_db_trace_bus_enable),
|
|
.thold_b(pc_pc_func_slp_sl_thold_0_b),
|
|
.sg(pc_pc_sg_0),
|
|
.force_t(force_func),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.scin(func_siv[TRACEOUT_OFFSET:TRACEOUT_OFFSET + TRACEOUT_SIZE - 1]),
|
|
.scout(func_sov[TRACEOUT_OFFSET:TRACEOUT_OFFSET + TRACEOUT_SIZE - 1]),
|
|
.din( trace_data_out_d),
|
|
.dout(trace_data_out_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(CORETRACE_SIZE), .INIT(0)) coretrace(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rg_db_trace_bus_enable),
|
|
.thold_b(pc_pc_func_slp_sl_thold_0_b),
|
|
.sg(pc_pc_sg_0),
|
|
.force_t(force_func),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.scin(func_siv[CORETRACE_OFFSET:CORETRACE_OFFSET + CORETRACE_SIZE - 1]),
|
|
.scout(func_sov[CORETRACE_OFFSET:CORETRACE_OFFSET + CORETRACE_SIZE - 1]),
|
|
.din( coretrace_ctrls_out_d),
|
|
.dout(coretrace_ctrls_out_q)
|
|
);
|
|
// func ring registers end
|
|
|
|
//=====================================================================
|
|
// Thold/SG Staging
|
|
//=====================================================================
|
|
// func lcbor
|
|
tri_lcbor lcbor_func0(
|
|
.clkoff_b(lcb_clkoff_dc_b),
|
|
.thold(pc_pc_func_slp_sl_thold_0),
|
|
.sg(pc_pc_sg_0),
|
|
.act_dis(lcb_act_dis_dc),
|
|
.force_t(force_func),
|
|
.thold_b(pc_pc_func_slp_sl_thold_0_b)
|
|
);
|
|
|
|
//=====================================================================
|
|
// Scan Connections
|
|
//=====================================================================
|
|
// Func ring
|
|
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
|
|
assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
|
|
|
|
|
|
endmodule
|