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431 lines
14 KiB
Verilog
431 lines
14 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *********************************************************************
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//
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// This is the ENTITY for iuq_btb
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//
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// *********************************************************************
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`include "tri_a2o.vh"
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module iuq_btb(
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// power pins
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inout gnd,
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inout vdd,
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inout vcs,
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// clock and clockcontrol ports
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input [0:`NCLK_WIDTH-1] nclk,
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input pc_iu_func_sl_thold_2,
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input pc_iu_sg_2,
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input pc_iu_fce_2,
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input tc_ac_ccflush_dc,
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input clkoff_b,
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input act_dis,
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input d_mode,
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input delay_lclkr,
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input mpw1_b,
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input mpw2_b,
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input scan_in,
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output scan_out,
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// ports
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input r_act,
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input w_act,
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input [0:5] r_addr,
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input [0:5] w_addr,
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input [0:2*`EFF_IFAR_WIDTH+2] data_in,
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output [0:2*`EFF_IFAR_WIDTH+2] data_out,
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input pc_iu_init_reset
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);
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//--------------------------
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// constants
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//--------------------------
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parameter data_in_offset = 0;
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parameter w_act_offset = data_in_offset + 2 * `EFF_IFAR_WIDTH + 3;
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parameter r_act_offset = w_act_offset + 1;
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parameter w_addr_offset = r_act_offset + 1;
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parameter r_addr_offset = w_addr_offset + 6;
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parameter reset_w_addr_offset = r_addr_offset + 6;
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parameter data_out_offset = reset_w_addr_offset + 6;
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parameter scan_right = data_out_offset + 2 * `EFF_IFAR_WIDTH + 3 - 1;
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//--------------------------
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// signals
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//--------------------------
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wire [0:71] w_data_in;
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wire [0:71] r_data_out;
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wire [0:5] zeros;
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wire pc_iu_func_sl_thold_1;
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wire pc_iu_func_sl_thold_0;
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wire pc_iu_func_sl_thold_0_b;
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wire pc_iu_sg_1;
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wire pc_iu_sg_0;
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wire pc_iu_fce_1;
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(* analysis_not_referenced="true" *)
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wire pc_iu_fce_0;
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wire force_t;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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wire tiup;
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wire tidn;
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wire write_thru;
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wire [0:2*`EFF_IFAR_WIDTH+2] data_in_d;
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wire [0:2*`EFF_IFAR_WIDTH+2] data_in_q;
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wire w_act_d;
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wire w_act_q;
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wire r_act_d;
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wire r_act_q;
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wire [0:5] w_addr_d;
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wire [0:5] w_addr_q;
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wire [0:5] r_addr_d;
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wire [0:5] r_addr_q;
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wire [0:2*`EFF_IFAR_WIDTH+2] data_out_d;
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wire [0:2*`EFF_IFAR_WIDTH+2] data_out_q;
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wire lat_wi_act;
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wire lat_ri_act;
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wire lat_ro_act;
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wire reset_act;
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wire [0:5] reset_w_addr_d;
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wire [0:5] reset_w_addr_q;
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wire w_act_in;
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wire [0:5] w_addr_in;
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//unused
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(* analysis_not_referenced="true" *)
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wire abst_scan_out;
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(* analysis_not_referenced="true" *)
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wire time_scan_out;
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(* analysis_not_referenced="true" *)
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wire repr_scan_out;
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(* analysis_not_referenced="true" *)
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wire bo_pc_failout;
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(* analysis_not_referenced="true" *)
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wire bo_pc_diagloop;
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assign tiup = 1'b1;
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assign tidn = 1'b0;
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assign reset_act = pc_iu_init_reset;
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assign reset_w_addr_d[0:5] = reset_w_addr_q[0:5] + 6'b000001;
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//-- data in
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//
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assign zeros[0:5] = {6{1'b0}};
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//
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//-- arrays
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//
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// tri array
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assign w_act_in = reset_act | w_act;
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assign w_addr_in[0:5] = reset_act ? reset_w_addr_q[0:5] : w_addr[0:5];
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assign w_data_in[0:71] = reset_act ? 0 : {data_in[0:2 * `EFF_IFAR_WIDTH + 2], {(71 - (2 * `EFF_IFAR_WIDTH + 2)){1'b0}} };
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tri_64x72_1r1w btb0(
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.vdd(vdd),
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.vcs(vcs),
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.gnd(gnd),
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.nclk(nclk),
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.sg_0(pc_iu_sg_0),
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.abst_sl_thold_0(tidn),
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.ary_nsl_thold_0(tidn),
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.time_sl_thold_0(tiup),
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.repr_sl_thold_0(tiup),
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// Reads
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.rd0_act(r_act),
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.rd0_adr(r_addr),
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.do0(r_data_out),
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// Writes
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.wr_act(w_act_in),
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.wr_adr(w_addr_in),
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.di(w_data_in),
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// Scan
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.abst_scan_in(tidn),
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.abst_scan_out(abst_scan_out),
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.time_scan_in(tidn),
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.time_scan_out(time_scan_out),
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.repr_scan_in(tidn),
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.repr_scan_out(repr_scan_out),
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// Misc Pervasive
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.scan_dis_dc_b(tidn), //an_ac_scan_dis_dc_b,
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.scan_diag_dc(tidn), //an_ac_scan_diag_dc,
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.ccflush_dc(tc_ac_ccflush_dc),
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.clkoff_dc_b(clkoff_b), //g8t_clkoff_dc_b,
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.d_mode_dc(d_mode), //g8t_d_mode_dc,
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.mpw1_dc_b({5{mpw1_b}}), //g8t_mpw1_dc_b,
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.mpw2_dc_b(mpw2_b), //g8t_mpw2_dc_b,
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.delay_lclkr_dc({5{delay_lclkr}}), //g8t_delay_lclkr_dc,
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// BOLT-ON
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.lcb_bolt_sl_thold_0(tidn), //bolt_sl_thold_0,
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.pc_bo_enable_2(tidn), //bo_enable_2, -- general bolt-on enable
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.pc_bo_reset(tidn), //pc_xu_bo_reset, -- reset
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.pc_bo_unload(tidn), //pc_xu_bo_unload, -- unload sticky bits
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.pc_bo_repair(tidn), //pc_xu_bo_repair, -- execute sticky bit decode
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.pc_bo_shdata(tidn), //pc_xu_bo_shdata, -- shift data for timing write and diag loop
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.pc_bo_select(tidn), //pc_xu_bo_select, -- select for mask and hier writes
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.bo_pc_failout(bo_pc_failout),
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.bo_pc_diagloop(bo_pc_diagloop),
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.tri_lcb_mpw1_dc_b(mpw1_b), //mpw1_dc_b,
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.tri_lcb_mpw2_dc_b(mpw2_b), //mpw2_dc_b,
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.tri_lcb_delay_lclkr_dc(delay_lclkr), //delay_lclkr_dc,
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.tri_lcb_clkoff_dc_b(clkoff_b), //clkoff_dc_b,
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.tri_lcb_act_dis_dc(act_dis),
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// ABIST
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.abist_bw_odd(tidn), //abist_g8t_bw_1_q,
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.abist_bw_even(tidn), //abist_g8t_bw_0_q,
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.tc_lbist_ary_wrt_thru_dc(tidn), //an_ac_lbist_ary_wrt_thru_dc,
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.abist_ena_1(tidn), //pc_xu_abist_ena_dc,
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.wr_abst_act(tidn), //abist_g8t_wenb_q,
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.abist_wr_adr(zeros[0:5]), //abist_waddr_0_q,
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.abist_di(zeros[0:3]), //abist_di_0_q,
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.rd0_abst_act(tidn), //abist_g8t1p_renb_0_q,
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.abist_rd0_adr(zeros[0:5]), //abist_raddr_0_q,
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.abist_g8t_rd0_comp_ena(tidn), //abist_wl32_comp_ena_q,
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.abist_raw_dc_b(tidn), //pc_xu_abist_raw_dc_b,
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.obs0_abist_cmp(zeros[0:3]) //abist_g8t_dcomp_q
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);
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// write through support
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assign data_in_d[0:2 * `EFF_IFAR_WIDTH + 2] = data_in[0:2 * `EFF_IFAR_WIDTH + 2];
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assign w_act_d = w_act;
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assign r_act_d = r_act;
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assign w_addr_d[0:5] = w_addr[0:5];
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assign r_addr_d[0:5] = r_addr[0:5];
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assign write_thru = w_act_q & (w_addr_q[0:5] == r_addr_q[0:5]) & r_act_q;
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// data out
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assign data_out_d[0:2 * `EFF_IFAR_WIDTH + 2] = (write_thru == 1'b1) ? data_in_q[0:2 * `EFF_IFAR_WIDTH + 2] :
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r_data_out[0:2 * `EFF_IFAR_WIDTH + 2];
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assign data_out[0:2 * `EFF_IFAR_WIDTH + 2] = data_out_q[0:2 * `EFF_IFAR_WIDTH + 2];
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//latch acts
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assign lat_wi_act = w_act;
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assign lat_ri_act = r_act;
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assign lat_ro_act = r_act_q;
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// latches
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tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_in_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(lat_wi_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[data_in_offset:data_in_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
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.scout(sov[data_in_offset:data_in_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
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.din(data_in_d),
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.dout(data_in_q)
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);
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tri_rlmlatch_p #(.INIT(0)) w_act_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[w_act_offset]),
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.scout(sov[w_act_offset]),
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.din(w_act_d),
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.dout(w_act_q)
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);
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tri_rlmlatch_p #(.INIT(0)) r_act_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[r_act_offset]),
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.scout(sov[r_act_offset]),
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.din(r_act_d),
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.dout(r_act_q)
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);
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tri_rlmreg_p #(.WIDTH(6), .INIT(0)) w_addr_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(lat_wi_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[w_addr_offset:w_addr_offset + 6 - 1]),
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.scout(sov[w_addr_offset:w_addr_offset + 6 - 1]),
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.din(w_addr_d),
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.dout(w_addr_q)
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);
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tri_rlmreg_p #(.WIDTH(6), .INIT(0)) r_addr_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(lat_ri_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[r_addr_offset:r_addr_offset + 6 - 1]),
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.scout(sov[r_addr_offset:r_addr_offset + 6 - 1]),
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.din(r_addr_d),
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.dout(r_addr_q)
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);
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tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_out_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(lat_ro_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[data_out_offset:data_out_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
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.scout(sov[data_out_offset:data_out_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]),
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.din(data_out_d),
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.dout(data_out_q)
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);
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tri_rlmreg_p #(.WIDTH(6), .INIT(0)) reset_w_addr_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(reset_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[reset_w_addr_offset:reset_w_addr_offset + 6 - 1]),
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.scout(sov[reset_w_addr_offset:reset_w_addr_offset + 6 - 1]),
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.din(reset_w_addr_d),
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.dout(reset_w_addr_q)
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);
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//-----------------------------------------------
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// pervasive
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//-----------------------------------------------
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tri_plat #(.WIDTH(3)) perv_2to1_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_fce_2}),
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.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1})
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);
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tri_plat #(.WIDTH(3)) perv_1to0_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}),
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.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_fce_0})
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);
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tri_lcbor perv_lcbor(
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.clkoff_b(clkoff_b),
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.thold(pc_iu_func_sl_thold_0),
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.sg(pc_iu_sg_0),
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.act_dis(act_dis),
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.force_t(force_t),
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.thold_b(pc_iu_func_sl_thold_0_b)
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);
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//-----------------------------------------------
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// scan
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//-----------------------------------------------
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assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]};
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assign scan_out = sov[scan_right];
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endmodule
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