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a2o
/
dev
/
verilog
/
unisims_soc
/
IDELAYCTRL.v
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module
IDELAYCTRL
#
(
)
(
output
RDY
,
input
REFCLK
,
input
RST
)
;
assign
RDY
=
!
RST
;
endmodule
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