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145 lines
5.0 KiB
Python
145 lines
5.0 KiB
Python
# A2O variants
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import os
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from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU
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dir = os.path.dirname(os.path.realpath(__file__))
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# these select the top RTL file for each variant name
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CPU_VARIANTS = {
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'WB_32BE' : 'a2owb',
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'WB_64LE' : 'a2owb',
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'standard' : 'a2owb'
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}
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#wtf doesnt do anything, but you can somehow do it by using -Xassembler in gcc flags
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GAS_FLAGS = {
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'WB_32BE' : '-defsym BIOS_32=1',
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'WB_64LE' : '-defsym BIOS_LE=1'
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}
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GCC_FLAGS = {
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'WB_32BE' : '-mcpu=a2 -m32 -mbig-endian -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_32=1',
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'WB_64LE' : '-mcpu=a2 -m64 -mlittle-endian -mabi=elfv2 -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_LE=1'
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}
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class A2O(CPU, AutoCSR):
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name = 'a2o'
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human_name = 'a2o'
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variants = CPU_VARIANTS
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# default 64LE
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family = 'ppc64'
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data_width = 64
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endianness = 'little'
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gcc_triple = ('powerpc64le-linux', 'powerpc64le-linux-gnu')
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linker_output_format = 'elf64-powerpcle'
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nop = 'nop'
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io_regions = {0xF0000000: 0x10000000} # origin, length
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@property
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def mem_map(self):
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return {}
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# how do you make this be default but not overwrite any defines in soc.py?
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return {
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'rom': 0x00000000, # on-board
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'sram': 0x00004000, # on-board
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'main_ram': 0x00100000, # external 1M+
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'csr': 0xF0000000,
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}
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@property
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags += ' -D__a2o__'
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return flags
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def __init__(self, platform, variant='WB'):
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if variant == 'standard':
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variant = 'WB_64LE'
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if variant == 'WB_32BE':
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#self.family = 'ppc' # kills meson build
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self.family = 'powerpc'
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self.data_width = 32
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self.endianness = 'big'
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self.gcc_triple = 'powerpc-linux-gnu'
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self.linker_output_format = 'elf32-powerpc'
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self.platform = platform
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self.variant = variant
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self.human_name = CPU_VARIANTS.get(variant, 'a2o')
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self.external_variant = None
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self.reset = Signal()
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self.interrupt = Signal(3)
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self.interruptS = Signal()
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self.dbus = dbus = wishbone.Interface()
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self.periph_buses = [dbus]
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self.memory_buses = []
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self.enableDebug = False
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self.enableJTAG = False
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self.reset_address = 0x00000000
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self.cpu_params = dict(
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i_clk = ClockSignal('sys'),
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#i_clk_2x = ClockSignal('sys2x'),
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i_rst = ResetSignal() | self.reset,
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# how do i connect these to csr?
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#i_cfg_wr = csr_0[0], # wr command - will be 3+ bit cmd
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#i_cfg_dat = csr_1, # wr data
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#o_status = status, # should update csr continuously
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i_cfg_wr = 0,
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i_externalInterrupt = self.interrupt[0],
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i_timerInterrupt = self.interrupt[1],
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i_softwareInterrupt = self.interrupt[2],
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i_externalInterruptS = self.interruptS,
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#wtf i guess you get these names from the Inteface() def - but what about other sigs?
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o_wb_cyc = dbus.cyc,
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o_wb_stb = dbus.stb,
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#wtf litex is declaring wire [29:0] a2o_dbus_adr and connecting directly here but a2owb;wb_adr is [0:31]
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# o_wb_adr = Cat(dbus.adr,Signal(2)),
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o_wb_adr = Cat(Signal(2),dbus.adr), # wb adr [31:2] = a2o adr[0:29]
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o_wb_we = dbus.we,
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o_wb_sel = dbus.sel,
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o_wb_datw = dbus.dat_w,
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i_wb_ack = dbus.ack,
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i_wb_datr = dbus.dat_r
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)
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def set_reset_address(self, reset_address):
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if reset_address != self.reset_address:
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print(f'Reset address = {self.reset_address} and cannot be changed here!')
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assert False
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@staticmethod
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def add_sources(platform, variant='WB_64LE'):
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dir = os.path.dirname(os.path.realpath(__file__))
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# unfortunately, vivado doesn't do the right thing and skip modules already analyzed, so overrides dirs don't work; rearrange override after
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platform.add_source(os.path.join(dir, 'verilog/a2o_litex/')) # node, wrapper
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platform.add_source(os.path.join(dir, 'verilog/trilib/')) # array, ff
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platform.add_source(os.path.join(dir, 'verilog/trilib_clk1x/')) # 2r4w override
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#platform.add_source(os.path.join(dir, 'verilog/unisims/')) # xil array
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platform.add_source(os.path.join(dir, 'verilog/work/')) # core
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def use_external_variant(self, variant_filename):
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self.external_variant = True
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self.platform.add_source(variant_filename)
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def do_finalize(self):
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if not self.external_variant:
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self.add_sources(self.platform, self.variant)
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self.specials += Instance('a2owb', **self.cpu_params)
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