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493 lines
22 KiB
Plaintext
493 lines
22 KiB
Plaintext
1 # asmtst.tpl
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2
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3 .include "defines.s"
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1 # © IBM Corp. 2020
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2 # Licensed under and subject to the terms of the CC-BY 4.0
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3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
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4 # Additional rights, including the right to physically implement a softcore
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5 # that is compliant with the required sections of the Power ISA
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6 # Specification, will be available at no cost via the OpenPOWER Foundation.
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7 # This README will be updated with additional information when OpenPOWER's
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8 # license is available.
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9
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10 #-----------------------------------------
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11 # Defines
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12 #-----------------------------------------
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13
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14 # Regs
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15
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16 .set r0, 0
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17 .set r1, 1
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18 .set r2, 2
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19 .set r3, 3
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20 .set r4, 4
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21 .set r5, 5
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22 .set r6, 6
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23 .set r7, 7
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24 .set r8, 8
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25 .set r9, 9
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26 .set r10,10
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27 .set r11,11
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28 .set r12,12
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29 .set r13,13
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30 .set r14,14
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31 .set r15,15
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32 .set r16,16
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33 .set r17,17
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34 .set r18,18
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35 .set r19,19
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36 .set r20,20
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37 .set r21,21
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38 .set r22,22
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39 .set r23,23
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40 .set r24,24
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41 .set r25,25
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42 .set r26,26
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43 .set r27,27
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44 .set r28,28
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45 .set r29,29
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46 .set r30,30
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47 .set r31,31
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48
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49 .set f0, 0
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50 .set f1, 1
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51 .set f2, 2
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52 .set f3, 3
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53 .set f4, 4
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54 .set f5, 5
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55 .set f6, 6
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56 .set f7, 7
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57 .set f8, 8
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58 .set f9, 9
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59 .set f10,10
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60 .set f11,11
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61 .set f12,12
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62 .set f13,13
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63 .set f14,14
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64 .set f15,15
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65 .set f16,16
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66 .set f17,17
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67 .set f18,18
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68 .set f19,19
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69 .set f20,20
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70 .set f21,21
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71 .set f22,22
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72 .set f23,23
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73 .set f24,24
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74 .set f25,25
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75 .set f26,26
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76 .set f27,27
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77 .set f28,28
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78 .set f29,29
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79 .set f30,30
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80 .set f31,31
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81
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82 .set cr0, 0
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83 .set cr1, 1
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84 .set cr2, 2
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85 .set cr3, 3
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86 .set cr4, 4
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87 .set cr5, 5
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88 .set cr6, 6
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89 .set cr7, 7
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90
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91 # SPR numbers
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92
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93 .set srr0, 26
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94 .set srr1, 27
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95 .set dar, 19
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96 .set dsisr, 18
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97 .set epcr, 307
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98 .set tar, 815
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99
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100 .set dbsr, 304
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101 .set dbcr0, 308
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102 .set dbcr1, 309
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103 .set dbcr2, 310
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104 .set dbcr3, 848
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105
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106 .set ivpr, 63
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107
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108 .set iucr0, 1011
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109 .set iucr1, 883
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110 .set iucr2, 884
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111
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112 .set iudbg0, 888
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113 .set iudbg1, 889
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114 .set iudbg2, 890
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115 .set iulfsr, 891
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116 .set iullcr, 892
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117
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118 .set mmucr0, 1020
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119 .set mmucr1, 1021
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120 .set mmucr2, 1022
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121 .set mmucr3, 1023
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122
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123 .set tb, 268
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124 .set tbl, 284
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125 .set tbh, 285
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126
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127 .set dec, 22
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128 .set udec, 550
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129 .set tsr, 336
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130 .set tcr, 340
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131
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132 .set xucr0, 1014
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133 .set xucr1, 851
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134 .set xucr2, 1016
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135 .set xucr3, 852
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136 .set xucr4, 853
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137
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138 .set tens, 438
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139 .set tenc, 439
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140 .set tensr, 437
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141
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142 .set pid, 48
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143 .set pir, 286
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144 .set pvr, 287
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145 .set tir, 446
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146
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147 #.set sprg0,
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148 #.set sprg1,
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149 #.set sprg2,
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150 .set sprg3, 259
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4
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5 # -------------------------------------------------------------------------------------------------
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6 # c-accessible
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7
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8 .global init_tst
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9 .global tst_start
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10 .global tst_end
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11 .global tst_inits
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12 .global tst_results
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13 .global tst_expects
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14
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15 # -------------------------------------------------------------------------------------------------
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16 tst_misc:
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17
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18 0000 696E666F tst_info: .asciz "info text"
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18 20746578
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18 7400
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19 000a 68656164 tst_header: .asciz "header text"
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19 65722074
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19 65787400
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20
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21 .set SAVESPR,tar
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22 .set MAGIC,0x8675309
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23
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24 # -------------------------------------------------------------------------------------------------
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25 0016 00000000 .align 5
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25 00000000
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25 0000
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26 tst_inits:
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27
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28 0020 00000000 init_r0: .int 0x00000000
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29 0024 5822C905 init_r1: .int 0x5822C905
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30 0028 FFFFFFFF init_r2: .int 0xFFFFFFFF
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31 002c 91B6D1A3 init_r3: .int 0x91B6D1A3
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32 0030 FFFFFFFF init_r4: .int 0xFFFFFFFF
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33 0034 FFFFFFFF init_r5: .int 0xFFFFFFFF
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34 0038 FFFFFFFF init_r6: .int 0xFFFFFFFF
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35 003c FFFFFFFF init_r7: .int 0xFFFFFFFF
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36 0040 FFFFFFFF init_r8: .int 0xFFFFFFFF
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37 0044 7E11EE88 init_r9: .int 0x7E11EE88
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38 0048 FFFFFFFF init_r10: .int 0xFFFFFFFF
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39 004c 7FFFFFFF init_r11: .int 0x7FFFFFFF
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40 0050 FFFFFFFF init_r12: .int 0xFFFFFFFF
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41 0054 FFFFFFFF init_r13: .int 0xFFFFFFFF
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42 0058 8C20BDE6 init_r14: .int 0x8C20BDE6
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43 005c FFFFFFFF init_r15: .int 0xFFFFFFFF
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44 0060 76D0DADF init_r16: .int 0x76D0DADF
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45 0064 15111F42 init_r17: .int 0x15111F42
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46 0068 FFFFFFFF init_r18: .int 0xFFFFFFFF
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47 006c 36108E50 init_r19: .int 0x36108E50
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48 0070 FFFFFFFF init_r20: .int 0xFFFFFFFF
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49 0074 FFFFFFFF init_r21: .int 0xFFFFFFFF
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50 0078 328A0CED init_r22: .int 0x328A0CED
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51 007c FFFFFFFF init_r23: .int 0xFFFFFFFF
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52 0080 FFFFFFFF init_r24: .int 0xFFFFFFFF
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53 0084 AF224C19 init_r25: .int 0xAF224C19
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54 0088 FFFFFFFF init_r26: .int 0xFFFFFFFF
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55 008c FFFFFFFF init_r27: .int 0xFFFFFFFF
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56 0090 D624B27A init_r28: .int 0xD624B27A
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57 0094 FFFFFFFF init_r29: .int 0xFFFFFFFF
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58 0098 FFFFFFFF init_r30: .int 0xFFFFFFFF
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59 009c FFFFFFFF init_r31: .int 0xFFFFFFFF
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60
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61 00a0 DBFD3628 init_cr: .int 0xDBFD3628
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62 00a4 89F0006E init_xer: .int 0x89F0006E
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63 00a8 FFFFFFFF init_ctr: .int 0xFFFFFFFF
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64 00ac FFFFFFFF init_lr: .int 0xFFFFFFFF
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65 00b0 FFFFFFFF init_tar: .int 0xFFFFFFFF
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66 00b4 00001104 init_msr: .int 0x00001104
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67
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68 00b8 00010000 init_iar: .int 0x00010000
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69
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70 00bc 00000000 save_r1: .int 0
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71
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72 00c0 0000000D codelen: .int 13
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73 00c4 7C61CC14 ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x
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73 7D230595
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73 7AC37392
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73 7E094C11
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73 7E1CB115
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74 00f8 00010000 iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x
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74 00010004
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74 00010008
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74 0001000C
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74 00010010
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75
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76 # -------------------------------------------------------------------------------------------------
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77 # r3=@tst_inits
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78 012c 48000014 .align 5
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78 60000000
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78 60000000
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78 60000000
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78 60000000
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79 init_tst:
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80
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81 # save c stuff
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82 0140 9023009C stw r1,(save_r1-tst_inits)(r3)
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83
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84 # copy ops
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85 opcopy:
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86 0144 802300A0 lwz r1,(codelen-tst_inits)(r3)
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87 0148 7C2903A6 mtctr r1
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88 014c 382300A4 la r1,(ops-tst_inits)(r3) # @ ops list
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89 0150 384300D8 la r2,(iars-tst_inits)(r3) # @ iars list
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90 opcopy_loop:
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91 0154 80810000 lwz r4,0(r1) # next op
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92 0158 80A20000 lwz r5,0(r2) # next iar
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93 015c 90850000 stw r4,0(r5) # store it
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94 0160 38210004 addi r1,r1,4 # inc to next
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95 0164 38420004 addi r2,r2,4
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96 0168 4200FFEC bdnz opcopy_loop
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97
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98 # add end of test op - could be done here or by builder
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99 # ways to end:
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100 # ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
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101 # trap,sc,scv - branch to tst_end in handler
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102 # attn, priv op, etc. - "
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103 # overwrite the last epilogue op to avoid any crossing
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104 opcopy_eot:
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105 016c 3C804800 lis r4,0x4800
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106 0170 60840006 ori r4,r4,0x0006 # ba 0x0004
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107 0174 90850000 stw r4,0(r5)
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108
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109 # get tst start
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110 0178 80200000 lwz r1,init_msr(r0)
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111 017c 7C3B03A6 mtsrr1 r1
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112 0180 80200000 lwz r1,iars(r0)
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113 0184 7C3A03A6 mtsrr0 r1
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114
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115 # init test regs
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116 init_regs:
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117 0188 80230080 lwz r1,(init_cr-tst_inits)(r3)
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118 018c 7C2FF120 mtcr r1
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119 0190 80230084 lwz r1,(init_xer-tst_inits)(r3)
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120 0194 7C2103A6 mtxer r1
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121 0198 80230088 lwz r1,(init_ctr-tst_inits)(r3)
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122 019c 7C2903A6 mtctr r1
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123 01a0 8023008C lwz r1,(init_lr-tst_inits)(r3)
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124 01a4 7C2803A6 mtlr r1
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125 01a8 80230090 lwz r1,(init_tar-tst_inits)(r3)
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126 01ac 7C2FCBA6 mtspr tar,r1
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127
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128 01b0 80030000 lwz r0,(init_r0-tst_inits)(r3)
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129 01b4 80230004 lwz r1,(init_r1-tst_inits)(r3)
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130 01b8 80430008 lwz r2,(init_r2-tst_inits)(r3)
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131 01bc 80830010 lwz r4,(init_r4-tst_inits)(r3)
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132 01c0 80A30014 lwz r5,(init_r5-tst_inits)(r3)
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133 01c4 80C30018 lwz r6,(init_r6-tst_inits)(r3)
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134 01c8 80E3001C lwz r7,(init_r7-tst_inits)(r3)
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135 01cc 81030020 lwz r8,(init_r8-tst_inits)(r3)
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136 01d0 81230024 lwz r9,(init_r9-tst_inits)(r3)
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137 01d4 81430028 lwz r10,(init_r10-tst_inits)(r3)
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138 01d8 8163002C lwz r11,(init_r11-tst_inits)(r3)
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139 01dc 81830030 lwz r12,(init_r12-tst_inits)(r3)
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140 01e0 81A30034 lwz r13,(init_r13-tst_inits)(r3)
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141 01e4 81C30038 lwz r14,(init_r14-tst_inits)(r3)
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142 01e8 81E3003C lwz r15,(init_r15-tst_inits)(r3)
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143 01ec 82030040 lwz r16,(init_r16-tst_inits)(r3)
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144 01f0 82230044 lwz r17,(init_r17-tst_inits)(r3)
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145 01f4 82430048 lwz r18,(init_r18-tst_inits)(r3)
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146 01f8 8263004C lwz r19,(init_r19-tst_inits)(r3)
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147 01fc 82830050 lwz r20,(init_r20-tst_inits)(r3)
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148 0200 82A30054 lwz r21,(init_r21-tst_inits)(r3)
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149 0204 82C30058 lwz r22,(init_r22-tst_inits)(r3)
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150 0208 82E3005C lwz r23,(init_r23-tst_inits)(r3)
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151 020c 83030060 lwz r24,(init_r24-tst_inits)(r3)
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152 0210 83230064 lwz r25,(init_r25-tst_inits)(r3)
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153 0214 83430068 lwz r26,(init_r26-tst_inits)(r3)
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154 0218 8363006C lwz r27,(init_r27-tst_inits)(r3)
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155 021c 83830070 lwz r28,(init_r28-tst_inits)(r3)
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156 0220 83A30074 lwz r29,(init_r29-tst_inits)(r3)
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157 0224 83C30078 lwz r30,(init_r30-tst_inits)(r3)
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158 0228 83E3007C lwz r31,(init_r31-tst_inits)(r3)
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159 022c 8063000C lwz r3,(init_r3-tst_inits)(r3)
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160
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161 jmp2tst:
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162 0230 4C000064 rfi
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163 #rfid
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164 #ba 0x10000
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165
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166 tst_end:
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167 0234 4800000C b save_results
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168
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169 # -------------------------------------------------------------------------------------------------
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170 0238 60000000 .align 5
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170 60000000
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171 save_results:
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172 # use a designated spr to save (sprgx, ...)
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173 0240 7C2FCBA6 mtspr SAVESPR,r1
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174 0244 3C200000 lis r1,tst_results@h
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175 0248 60210000 ori r1,r1,tst_results@l
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176 024c 90010000 stw r0,(rslt_r0-tst_results)(r1)
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177 0250 90410008 stw r2,(rslt_r2-tst_results)(r1)
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178 0254 9061000C stw r3,(rslt_r3-tst_results)(r1)
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179 0258 90810010 stw r4,(rslt_r4-tst_results)(r1)
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180 025c 90A10014 stw r5,(rslt_r5-tst_results)(r1)
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181 0260 90C10018 stw r6,(rslt_r6-tst_results)(r1)
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182 0264 90E1001C stw r7,(rslt_r7-tst_results)(r1)
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183 0268 91010020 stw r8,(rslt_r8-tst_results)(r1)
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184 026c 91210024 stw r9,(rslt_r9-tst_results)(r1)
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185 0270 91410028 stw r10,(rslt_r10-tst_results)(r1)
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186 0274 9161002C stw r11,(rslt_r11-tst_results)(r1)
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187 0278 91810030 stw r12,(rslt_r12-tst_results)(r1)
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188 027c 91A10034 stw r13,(rslt_r13-tst_results)(r1)
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189 0280 91C10038 stw r14,(rslt_r14-tst_results)(r1)
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190 0284 91E1003C stw r15,(rslt_r15-tst_results)(r1)
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191 0288 92010040 stw r16,(rslt_r16-tst_results)(r1)
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192 028c 92210044 stw r17,(rslt_r17-tst_results)(r1)
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193 0290 92410048 stw r18,(rslt_r18-tst_results)(r1)
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194 0294 9261004C stw r19,(rslt_r19-tst_results)(r1)
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195 0298 92810050 stw r20,(rslt_r20-tst_results)(r1)
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196 029c 92A10054 stw r21,(rslt_r21-tst_results)(r1)
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197 02a0 92C10058 stw r22,(rslt_r22-tst_results)(r1)
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198 02a4 92E1005C stw r23,(rslt_r23-tst_results)(r1)
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199 02a8 93010060 stw r24,(rslt_r24-tst_results)(r1)
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200 02ac 93210064 stw r25,(rslt_r25-tst_results)(r1)
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201 02b0 93410068 stw r26,(rslt_r26-tst_results)(r1)
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202 02b4 9361006C stw r27,(rslt_r27-tst_results)(r1)
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203 02b8 93810070 stw r28,(rslt_r28-tst_results)(r1)
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204 02bc 93A10074 stw r29,(rslt_r29-tst_results)(r1)
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205 02c0 93C10078 stw r30,(rslt_r30-tst_results)(r1)
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206 02c4 93E1007C stw r31,(rslt_r31-tst_results)(r1)
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207 02c8 7C4FCAA6 mfspr r2,SAVESPR
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208 02cc 90410004 stw r2,(rslt_r1-tst_results)(r1)
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209 02d0 7C400026 mfcr r2
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210 02d4 90410080 stw r2,(rslt_cr-tst_results)(r1)
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211 02d8 7C4102A6 mfxer r2
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212 02dc 90410084 stw r2,(rslt_xer-tst_results)(r1)
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213 02e0 7C4902A6 mfctr r2
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214 02e4 90410088 stw r2,(rslt_ctr-tst_results)(r1)
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215 02e8 7C4802A6 mflr r2
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216 02ec 9041008C stw r2,(rslt_lr-tst_results)(r1)
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217 02f0 7C4FCAA6 mfspr r2,tar
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218 02f4 90410090 stw r2,(rslt_tar-tst_results)(r1)
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219
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220 tst_cleanup:
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221 # restore c stuff
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222 02f8 3C600000 lis r3,tst_inits@h
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223 02fc 60630000 ori r3,r3,tst_inits@l
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224 0300 8023009C lwz r1,(save_r1-tst_inits)(r3)
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225 0304 3C600867 lis r3,MAGIC@h
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226 0308 60635309 ori r3,r3,MAGIC@l
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227
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228 030c 48000003 bla tst_done
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229
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230 # -------------------------------------------------------------------------------------------------
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231 0310 60000000 .align 5
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231 60000000
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231 60000000
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231 60000000
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232 tst_results:
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233
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234 0320 FFFFFFFF rslt_r0: .int 0xFFFFFFFF
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235 0324 FFFFFFFF rslt_r1: .int 0xFFFFFFFF
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236 0328 FFFFFFFF rslt_r2: .int 0xFFFFFFFF
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237 032c FFFFFFFF rslt_r3: .int 0xFFFFFFFF
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238 0330 FFFFFFFF rslt_r4: .int 0xFFFFFFFF
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239 0334 FFFFFFFF rslt_r5: .int 0xFFFFFFFF
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240 0338 FFFFFFFF rslt_r6: .int 0xFFFFFFFF
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241 033c FFFFFFFF rslt_r7: .int 0xFFFFFFFF
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242 0340 FFFFFFFF rslt_r8: .int 0xFFFFFFFF
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243 0344 FFFFFFFF rslt_r9: .int 0xFFFFFFFF
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244 0348 FFFFFFFF rslt_r10: .int 0xFFFFFFFF
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245 034c FFFFFFFF rslt_r11: .int 0xFFFFFFFF
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246 0350 FFFFFFFF rslt_r12: .int 0xFFFFFFFF
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247 0354 FFFFFFFF rslt_r13: .int 0xFFFFFFFF
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248 0358 FFFFFFFF rslt_r14: .int 0xFFFFFFFF
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249 035c FFFFFFFF rslt_r15: .int 0xFFFFFFFF
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250 0360 FFFFFFFF rslt_r16: .int 0xFFFFFFFF
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251 0364 FFFFFFFF rslt_r17: .int 0xFFFFFFFF
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252 0368 FFFFFFFF rslt_r18: .int 0xFFFFFFFF
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253 036c FFFFFFFF rslt_r19: .int 0xFFFFFFFF
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254 0370 FFFFFFFF rslt_r20: .int 0xFFFFFFFF
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255 0374 FFFFFFFF rslt_r21: .int 0xFFFFFFFF
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256 0378 FFFFFFFF rslt_r22: .int 0xFFFFFFFF
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257 037c FFFFFFFF rslt_r23: .int 0xFFFFFFFF
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258 0380 FFFFFFFF rslt_r24: .int 0xFFFFFFFF
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259 0384 FFFFFFFF rslt_r25: .int 0xFFFFFFFF
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260 0388 FFFFFFFF rslt_r26: .int 0xFFFFFFFF
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261 038c FFFFFFFF rslt_r27: .int 0xFFFFFFFF
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262 0390 FFFFFFFF rslt_r28: .int 0xFFFFFFFF
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263 0394 FFFFFFFF rslt_r29: .int 0xFFFFFFFF
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264 0398 FFFFFFFF rslt_r30: .int 0xFFFFFFFF
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265 039c FFFFFFFF rslt_r31: .int 0xFFFFFFFF
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266
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267 03a0 FFFFFFFF rslt_cr: .int 0xFFFFFFFF
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268 03a4 FFFFFFFF rslt_xer: .int 0xFFFFFFFF
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269 03a8 FFFFFFFF rslt_ctr: .int 0xFFFFFFFF
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270 03ac FFFFFFFF rslt_lr: .int 0xFFFFFFFF
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271 03b0 FFFFFFFF rslt_tar: .int 0xFFFFFFFF
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272
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273 # -------------------------------------------------------------------------------------------------
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274 03b4 60000000 .align 5
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274 60000000
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274 60000000
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275 tst_expects:
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276
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277 03c0 00000000 expt_r0: .int 0x00000000
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278 03c4 CD75F313 expt_r1: .int 0xCD75F313
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279 03c8 FFFFFFFF expt_r2: .int 0xFFFFFFFF
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280 03cc 00000000 expt_r3: .int 0x00000000
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281 03d0 FFFFFFFF expt_r4: .int 0xFFFFFFFF
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282 03d4 FFFFFFFF expt_r5: .int 0xFFFFFFFF
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283 03d8 FFFFFFFF expt_r6: .int 0xFFFFFFFF
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284 03dc FFFFFFFF expt_r7: .int 0xFFFFFFFF
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285 03e0 FFFFFFFF expt_r8: .int 0xFFFFFFFF
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286 03e4 008A0C68 expt_r9: .int 0x008A0C68
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287 03e8 FFFFFFFF expt_r10: .int 0xFFFFFFFF
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288 03ec 7FFFFFFF expt_r11: .int 0x7FFFFFFF
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289 03f0 FFFFFFFF expt_r12: .int 0xFFFFFFFF
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290 03f4 FFFFFFFF expt_r13: .int 0xFFFFFFFF
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291 03f8 8C20BDE6 expt_r14: .int 0x8C20BDE6
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292 03fc FFFFFFFF expt_r15: .int 0xFFFFFFFF
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293 0400 08AEBF68 expt_r16: .int 0x08AEBF68
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294 0404 80000001 expt_r17: .int 0x80000001
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295 0408 FFFFFFFF expt_r18: .int 0xFFFFFFFF
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296 040c 00000000 expt_r19: .int 0x00000000
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297 0410 FFFFFFFF expt_r20: .int 0xFFFFFFFF
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298 0414 FFFFFFFF expt_r21: .int 0xFFFFFFFF
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299 0418 328A0CED expt_r22: .int 0x328A0CED
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300 041c FFFFFFFF expt_r23: .int 0xFFFFFFFF
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301 0420 FFFFFFFF expt_r24: .int 0xFFFFFFFF
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302 0424 AF224C19 expt_r25: .int 0xAF224C19
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303 0428 FFFFFFFF expt_r26: .int 0xFFFFFFFF
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304 042c FFFFFFFF expt_r27: .int 0xFFFFFFFF
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305 0430 D624B27A expt_r28: .int 0xD624B27A
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306 0434 FFFFFFFF expt_r29: .int 0xFFFFFFFF
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307 0438 FFFFFFFF expt_r30: .int 0xFFFFFFFF
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308 043c FFFFFFFF expt_r31: .int 0xFFFFFFFF
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309
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310 0440 9BFD3628 expt_cr: .int 0x9BFD3628
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311 0444 98F0006E expt_xer: .int 0x98F0006E
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312 0448 FFFFFFFF expt_ctr: .int 0xFFFFFFFF
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313 044c FFFFFFFF expt_lr: .int 0xFFFFFFFF
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314 0450 FFFFFFFF expt_tar: .int 0xFFFFFFFF
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315 0454 00001104 expt_msr: .int 0x00001104
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316
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317 0458 00010038 expt_iar: .int 0x00010038
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318
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