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231 lines
10 KiB
Verilog
231 lines
10 KiB
Verilog
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`include "tri_a2o.vh"
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`timescale 1ns/1ps
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// might add some sim-only lines to enable clks, etc.
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module cocotb_icarus_node (
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input[0:`NCLK_WIDTH-1] nclk,
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input scan_in,
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output scan_out,
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// Pervasive clock control
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input an_ac_rtim_sl_thold_8,
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input an_ac_func_sl_thold_8,
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input an_ac_func_nsl_thold_8,
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input an_ac_ary_nsl_thold_8,
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input an_ac_sg_8,
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input an_ac_fce_8,
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input [0:7] an_ac_abst_scan_in,
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//SCOM Satellite
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input [0:3] an_ac_scom_sat_id,
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input an_ac_scom_dch,
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input an_ac_scom_cch,
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output ac_an_scom_dch,
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output ac_an_scom_cch,
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// FIR and Error Signals
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output [0:`THREADS-1] ac_an_special_attn,
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output [0:2] ac_an_checkstop,
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output [0:2] ac_an_local_checkstop,
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output [0:2] ac_an_recov_err,
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output ac_an_trace_error,
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output ac_an_livelock_active,
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input [0:`THREADS-1] an_ac_external_mchk,
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output an_ac_checkstop,
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// Perfmon Event Bus
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output [0:4*`THREADS-1] ac_an_event_bus0,
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output [0:4*`THREADS-1] ac_an_event_bus1,
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// Reset related
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input an_ac_reset_1_complete,
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input an_ac_reset_2_complete,
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input an_ac_reset_3_complete,
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input an_ac_reset_wd_complete,
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// Power Management
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output [0:`THREADS-1] ac_an_pm_thread_running,
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input [0:`THREADS-1] an_ac_pm_thread_stop,
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input [0:`THREADS-1] an_ac_pm_fetch_halt,
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output ac_an_power_managed,
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output ac_an_rvwinkle_mode,
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input an_ac_flh2l2_gate,
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// Clock, Test, and LCB Controls
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input an_ac_gsd_test_enable_dc,
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input an_ac_gsd_test_acmode_dc,
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input an_ac_ccflush_dc,
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input an_ac_ccenable_dc,
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input an_ac_lbist_en_dc,
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input an_ac_lbist_ip_dc,
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input an_ac_lbist_ac_mode_dc,
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input an_ac_scan_diag_dc,
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input an_ac_scan_dis_dc_b,
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//Thold input to clock control macro
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input [0:8] an_ac_scan_type_dc,
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// Pervasive
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output ac_an_reset_1_request,
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output ac_an_reset_2_request,
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output ac_an_reset_3_request,
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output ac_an_reset_wd_request,
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input an_ac_lbist_ary_wrt_thru_dc,
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input [0:`THREADS-1] an_ac_sleep_en,
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input [0:`THREADS-1] an_ac_ext_interrupt,
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input [0:`THREADS-1] an_ac_crit_interrupt,
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input [0:`THREADS-1] an_ac_perf_interrupt,
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input [0:`THREADS-1] an_ac_hang_pulse,
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input an_ac_tb_update_enable,
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input an_ac_tb_update_pulse,
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input [0:3] an_ac_chipid_dc,
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input [0:7] an_ac_coreid,
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output [0:`THREADS-1] ac_an_machine_check,
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input an_ac_debug_stop,
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output [0:`THREADS-1] ac_an_debug_trigger,
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input [0:`THREADS-1] an_ac_uncond_dbg_event,
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output [0:31] ac_an_debug_bus,
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output ac_an_coretrace_first_valid,
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output ac_an_coretrace_valid,
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output [0:1] ac_an_coretrace_type,
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output [0:31] mem_adr,
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input [0:127] mem_dat,
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output mem_wr_val,
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output [0:15] mem_wr_be,
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output [0:127] mem_wr_dat,
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output wb_stb,
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output wb_cyc,
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output [31:0] wb_adr,
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output wb_we,
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output [3:0] wb_sel,
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output [31:0] wb_datw,
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input wb_ack,
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input [31:0] wb_datr
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);
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a2owb c0 (
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.nclk(nclk),
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.scan_in(scan_in),
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.scan_out(scan_out),
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// Pervasive clock control
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.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
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.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
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.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
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.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
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.an_ac_sg_8(an_ac_sg_8),
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.an_ac_fce_8(an_ac_fce_8),
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.an_ac_abst_scan_in(an_ac_abst_scan_in),
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//SCOM Satellite
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.an_ac_scom_sat_id(an_ac_scom_sat_id),
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.an_ac_scom_dch(an_ac_scom_dch),
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.an_ac_scom_cch(an_ac_scom_cch),
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.ac_an_scom_dch(ac_an_scom_dch),
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.ac_an_scom_cch(ac_an_scom_cch),
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// FIR and Error Signals
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.ac_an_special_attn(ac_an_special_attn),
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.ac_an_checkstop(ac_an_checkstop),
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.ac_an_local_checkstop(ac_an_local_checkstop),
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.ac_an_recov_err(ac_an_recov_err),
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.ac_an_trace_error(ac_an_trace_error),
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.ac_an_livelock_active(ac_an_livelock_active),
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.an_ac_checkstop(an_ac_checkstop),
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.an_ac_external_mchk(an_ac_external_mchk),
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// Perfmon Event Bus
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.ac_an_event_bus0(ac_an_event_bus0),
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.ac_an_event_bus1(ac_an_event_bus1),
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// Reset related
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.an_ac_reset_1_complete(an_ac_reset_1_complete),
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.an_ac_reset_2_complete(an_ac_reset_2_complete),
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.an_ac_reset_3_complete(an_ac_reset_3_complete),
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.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
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// Power Management
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.ac_an_pm_thread_running(ac_an_pm_thread_running),
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.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
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.ac_an_power_managed(ac_an_power_managed),
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.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
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.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
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// Clock, Test, and LCB Controls
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.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
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.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
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.an_ac_ccflush_dc(an_ac_ccflush_dc),
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.an_ac_ccenable_dc(an_ac_ccenable_dc),
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.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
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.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
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.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
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.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
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.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
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//Thold input to clock control macro
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.an_ac_scan_type_dc(an_ac_scan_type_dc),
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// Pervasive
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.ac_an_reset_1_request(ac_an_reset_1_request),
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.ac_an_reset_2_request(ac_an_reset_2_request),
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.ac_an_reset_3_request(ac_an_reset_3_request),
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.ac_an_reset_wd_request(ac_an_reset_wd_request),
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.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
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.an_ac_sleep_en(an_ac_sleep_en),
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.an_ac_ext_interrupt(an_ac_ext_interrupt),
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.an_ac_crit_interrupt(an_ac_crit_interrupt),
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.an_ac_perf_interrupt(an_ac_perf_interrupt),
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.an_ac_hang_pulse(an_ac_hang_pulse),
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.an_ac_tb_update_enable(an_ac_tb_update_enable),
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.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
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.an_ac_chipid_dc(an_ac_chipid_dc),
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.an_ac_coreid(an_ac_coreid),
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.ac_an_machine_check(ac_an_machine_check),
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.an_ac_debug_stop(an_ac_debug_stop),
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.ac_an_debug_trigger(ac_an_debug_trigger),
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.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
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// direct-attach mem
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.mem_adr(mem_adr),
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.mem_dat(mem_dat),
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.mem_wr_val(mem_wr_val),
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.mem_wr_be(mem_wr_be),
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.mem_wr_dat(mem_wr_dat),
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// wishbone
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.wb_stb(wb_stb),
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.wb_cyc(wb_cyc),
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.wb_adr(wb_adr),
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.wb_we(wb_we),
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.wb_ack(wb_ack),
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.wb_sel(wb_sel),
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.wb_datr(wb_datr),
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.wb_datw(wb_datw)
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);
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initial begin
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$dumpfile ("a2onode.vcd");
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// you can do it by levels and also by module so could prune down
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$dumpvars;
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// need to explicitly specify arrays for icarus
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// guess not: $dumpvars cannot dump a vpiMemory
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//$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q);
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#1;
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end
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// see if coco lets me risingedge() these
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wire clk_1x, clk_2x, clk_4x, rst;
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assign clk_1x = nclk[0];
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assign clk_2x = nclk[2];
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assign clk_4x = nclk[3];
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assign rst = nclk[1];
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endmodule |