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433 lines
13 KiB
C++
433 lines
13 KiB
C++
// simple verilator top
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// uses a2owb with sim mem interface
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#define TRACING
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// old public access method
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//#define OLD_PUBLIC
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#include <cstddef>
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#include <unordered_map>
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#include "verilated.h"
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#include "Va2owb.h"
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#ifndef OLD_PUBLIC
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// internal nets
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#include "Va2owb___024root.h"
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#endif
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#include "Va2owb_a2owb.h"
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#include "Va2owb_a2l2wb.h"
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#include "Va2owb_c.h"
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#include "Va2owb_iuq.h"
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#include "Va2owb_iuq_cpl_top.h"
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#include "Va2owb_iuq_cpl.h"
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//#include "Va2owb_iuq_cpl_ctrl.h" // getting rid of public sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q fixed sim probs?#??!?~@?
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#ifdef TRACING
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#include "verilated_vcd_c.h"
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VerilatedVcdC *t;
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#else
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unsigned int t = 0;
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#endif
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/*
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#include "uart/uartsim.h"
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*/
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Va2owb* m;
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#ifdef OLD_PUBLIC
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Va2owb* root;
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#else
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Va2owb___024root* root;
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#endif
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vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override
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double sc_time_stamp() { // $time in verilog
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return main_time;
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}
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const char* tbName = "tb_litex";
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const int resetCycle = 10;
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const int threadRunCycle = resetCycle + 5;
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const int runCycles = 15000;
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const int hbCycles = 500;
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const int quiesceCycles = 50;
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const int threads = 1;
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const std::string testFile = "../mem/test3/rom.init";
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const unsigned int bootAdr = 0x00000000;
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const unsigned int stopOnHang = 200;
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const unsigned int stopOnLoop = 10;
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const unsigned long iarPass = 0x7F0;
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const unsigned long iarFail = 0x7F4;
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const bool debugWB = false;
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// Cythonize this and use it for cocotb too...
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class Memory {
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std::unordered_map<unsigned int, unsigned int> mem;
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public:
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bool le;
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bool logStores;
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int defaultVal;
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Memory();
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void loadFile(std::string filename, unsigned int adr=0, bool le=false, std::string format="ascii");
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int read(unsigned int adr);
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void write(unsigned int adr, unsigned int dat);
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void write(unsigned int adr, unsigned int be, unsigned int dat);
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};
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Memory::Memory() {
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this->defaultVal = 0;
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this->le = false;
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this->logStores = true;
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}
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void Memory::loadFile(std::string filename, unsigned int adr, bool le, std::string format) {
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unsigned int dat;
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std::ifstream f;
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f.open(filename, std::fstream::in);
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// "ascii"
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//while (f.peek()!=EOF) {
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//f >> std::hex >> dat;
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// f >> dat;
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while (f >> std::hex >> dat) {
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this->write(adr, dat);
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adr += 4;
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}
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}
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// adr is word-aligned byte address
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int Memory::read(unsigned int adr) {
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if (this->mem.find(adr) != this->mem.end()) {
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return this->mem[adr];
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} else {
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return this->defaultVal;
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}
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}
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// adr is word-aligned byte address
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void Memory::write(unsigned int adr, unsigned int dat) {
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unsigned int startDat = this->read(adr);
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this->write(adr, 0xF, dat);
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}
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void Memory::write(unsigned int adr, unsigned int be, unsigned int dat) {
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if (be == 0) return;
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int mask = 0, startDat;
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if (be >= 8) {
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be = be - 8;
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mask = 0xFF000000;
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} else {
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mask = 0;
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}
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if (be >= 4) {
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be = be - 4;
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mask |= 0x00FF0000;
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}
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if (be >= 2) {
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be = be - 2;
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mask |= 0x0000FF00;
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}
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if (be = 1) {
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mask |= 0x000000FF;
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}
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startDat = this->read(adr);
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this->mem[adr] = (startDat & ~mask) | (dat & mask);
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if (this->logStores) {
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std::cout << " * Mem Update @" << std::setw(8) << std::setfill('0') << std::uppercase << std::hex << adr <<
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" " <<std::setw(8) << std::setfill('0') << std::uppercase << std::hex << startDat <<
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"->" <<std::setw(8) << std::setfill('0') << std::uppercase << std::hex << this->read(adr) << std::endl;
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}
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}
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Memory mem;
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int main(int argc, char **argv) {
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using namespace std;
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cout << setfill('0');
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Verilated::commandArgs(argc, argv);
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m = new Va2owb;
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#ifdef OLD_PUBLIC
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root = m;
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#else
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root = m->rootp;
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#endif
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#ifdef TRACING
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Verilated::traceEverOn(true);
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t = new VerilatedVcdC;
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m->trace(t, 99);
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t->open("a2olitex.vcd");
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cout << "Tracing enabled." << endl;
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#endif
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bool ok = true;
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bool done = false;
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bool resetDone = false;
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bool booted = false;
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unsigned int quiesceCount = 0;
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unsigned int threadStop = 0x3;
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unsigned int tick = 0;
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unsigned int cycle = 1;
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unsigned int readPending = 0;
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unsigned int readAddr = 0;
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unsigned int readTag = 0;
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unsigned int readTID = 0;
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unsigned int countReads = 0;
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unsigned int lastCompCycle = 0;
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unsigned int lastCompSame = 0;
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bool wbRdPending = false, wbWrPending = false;
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//unsigned int wbSel, wbDatW;
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unsigned int iu0Comp, iu1Comp, iu0CompLast, iu1CompLast;
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unsigned long iu0CompIFAR, iu1CompIFAR, iu0CompIFARLast, iu1CompIFARLast, iuCompFlushIFAR;
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/*
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# GPR pool and arch map
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gprCompMap = []
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lastGprCompMap = []
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#wtf check what 33:36 are!
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for i in range(36):
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gprCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastGprCompMap.append(i)
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gpr = []
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for i in range(144):
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gpr.append(sim.a2o.root.xu0.gpr.gpr0.loc[i].dat)
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# CR fields pool and arch map
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crCompMap = []
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lastCrCompMap = []
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for i in range(8):
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crCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.cr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastCrCompMap.append(i)
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cr = []
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for i in range(24):
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cr.append(sim.a2o.root.xu0.cr.entry[i].reg_latch.dout)
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# XER pool and arch map
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xerCompMap = []
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lastXerCompMap = []
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for i in range(1):
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xerCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastXerCompMap.append(i)
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xer = []
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for i in range(12):
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xer.append(sim.a2o.root.xu0.xer.entry[i].reg_latch.dout)
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# CTR pool and arch map
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ctrCompMap = []
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lastCtrCompMap = []
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for i in range(1):
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ctrCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastCtrCompMap.append(i)
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ctr = []
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for i in range(8):
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ctr.append(sim.a2o.root.xu0.ctr.entry[i].reg_latch.dout)
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# LR pool and arch map
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lrCompMap = []
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lastLrCompMap = []
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for i in range(1):
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lrCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.lr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastLrCompMap.append(i)
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lr = []
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for i in range(8):
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lr.append(sim.a2o.root.xu0.lr.entry[i].reg_latch.dout)
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*/
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mem.write(0xFFFFFFFC, 0x48000002);
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mem.loadFile(testFile);
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m->rst = 1;
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cout << dec << setw(8) << cycle << " Resetting..." << endl;
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//m->an_ac_pm_thread_stop = threadStop;
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//cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl;
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//const int clocks[4] = {0x3, 0x2, 0x1, 0x0}; // 1x, 2x
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//const int ticks1x = 4;
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// all clk2x and clk4x fpga arrays overridden
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const int clocks[2] = {0x1, 0x0}; // 1x
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const int ticks1x = 2;
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while (!Verilated::gotFinish() && (ok | quiesceCount > 0) && cycle <= runCycles && !done) {
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if (!resetDone && (cycle > resetCycle)) {
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m->rst = 0;
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cout << dec << setw(8) << cycle << " Releasing reset." << endl;
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resetDone = true;
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}
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if (threadStop && (cycle > threadRunCycle)) {
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//threadStop = 0x0;
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//m->an_ac_pm_thread_stop = threadStop;
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//cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl;
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}
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m->clk = clocks[tick % ticks1x];
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m->eval();
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// 1x clock
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if ((tick % ticks1x) == 0) {
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// core
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iu0Comp = root->a2owb->c0->iuq0->iuq_cpl_top0->iuq_cpl0->cp2_i0_completed;
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iu1Comp = root->a2owb->c0->iuq0->iuq_cpl_top0->iuq_cpl0->cp2_i1_completed;
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iu0CompIFAR = root->a2owb->c0->iuq0->iuq_cpl_top0->iuq_cpl0->cp2_i0_ifar << 2;
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iu1CompIFAR = root->a2owb->c0->iuq0->iuq_cpl_top0->iuq_cpl0->cp2_i1_ifar << 2;
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iuCompFlushIFAR = root->a2owb->c0->cp_t0_flush_ifar << 2;
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if (iu0Comp || iu1Comp) {
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " C0: CP";
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if (iu0Comp)
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cout << " 0:" << setw(6) << setfill('0') << hex << (iu0CompIFAR);
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if (iu1Comp)
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cout << " 1:" << setw(6) << setfill('0') << hex << (iu1CompIFAR);
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cout << " " << setw(16) << setfill('0') << hex << (iuCompFlushIFAR);
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cout << endl;
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lastCompCycle = cycle;
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if (quiesceCount > 0) {
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// skip remaining checks
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} else if ((iu0Comp && (iu0CompIFAR == iarPass)) || (iu1Comp && (iu1CompIFAR == iarPass))) {
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cout << "*** Passing IAR detected ***" << endl;
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quiesceCount = 5;
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} else if ((iu0Comp && (iu0CompIFAR == iarFail)) || (iu1Comp && (iu1CompIFAR == iarFail))) {
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cout << "*** Failing IAR detected ***" << endl;
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ok = false;
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quiesceCount = 5;
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} else if ((iu0Comp == iu0CompLast) && (!iu0Comp || (iu0CompIFAR == iu0CompIFARLast)) &&
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(iu1Comp == iu1CompLast) && (!iu1Comp || (iu1CompIFAR == iu1CompIFARLast))) {
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lastCompSame++;
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if (stopOnLoop && (lastCompSame == stopOnLoop)) {
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ok = false;
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cout << "*** Loop detected for " << dec << stopOnLoop << " iterations ***" << endl;
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}
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} else {
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iu0CompLast = iu0Comp;
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iu0CompIFARLast = iu0CompIFAR;
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iu1CompLast = iu1Comp;
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iu1CompIFARLast = iu1CompIFAR;
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lastCompSame = 0;
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}
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} else if (!quiesceCount && (stopOnHang != 0) && (cycle - lastCompCycle > stopOnHang)) {
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ok = false;
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cout << "*** No completion detected in " << dec << stopOnHang << " cycles ***" << endl;
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}
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// wb
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m->wb_ack = 0;
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if (wbRdPending) {
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m->wb_datr = mem.read(m->wb_adr & 0xFFFFFFFC);
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m->wb_ack = 1;
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if (debugWB)
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (m->wb_adr & 0xFFFFFFFC) <<
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" DATA=" << setw(8) << hex << setfill('0') << m->wb_datr << endl;
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wbRdPending = false;
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} else if (wbWrPending) {
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mem.write(m->wb_adr, m->wb_sel, m->wb_datw);
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m->wb_ack = 1;
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if (debugWB)
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (m->wb_adr & 0xFFFFFFFC) <<
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" SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)m->wb_sel <<
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" DATA=" << setw(8) << hex << setfill('0') << m->wb_datw << endl;
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wbWrPending = false;
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} else if (m->wb_cyc && m->wb_stb) {
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if (!m->wb_we) {
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//cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD RA=" << setw(8) << hex << setfill('0') << m->wb_adr << endl;
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wbRdPending = true;
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/* only for debug - completions should be checked for loops, hangs, boot re-execute
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if (m->wb_adr == bootAdr) {
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if (booted) {
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cout << "*** Fetch to boot address (" << dec << setw(8) << bootAdr << ") after initial boot ***" << endl;
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ok = false;
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} else {
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booted = true;
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}
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}
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*/
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} else {
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//cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR RA=" << setw(8) << hex << setfill('0') << m->wb_adr <<
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// " SEL=" << m->wb_sel << " DATA=" << setw(8) << hex << setfill('0') << m->wb_datw << endl;
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wbWrPending = true;
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}
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}
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}
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m->eval(); // NEED THIS!!!!
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// finish clock stuff
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if ((tick % ticks1x) == 0) {
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cycle++;
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if ((cycle % hbCycles) == 0) {
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cout << dec << setw(8) << setfill('0') << cycle << " ...tick..." << endl;
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}
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}
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tick++;
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#ifdef TRACING
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t->dump(tick);
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t->flush();
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#endif
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// check for fails
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if (!ok && quiesceCount == 0) {
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quiesceCount = quiesceCycles;
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cout << "Quiescing..." << endl;
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} else if (quiesceCount > 0) {
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quiesceCount--;
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if (ok && quiesceCount == 0) {
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done = true;
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}
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}
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}
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#ifdef TRACING
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t->close();
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#endif
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m->final();
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cout << endl << endl << tbName << endl;
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cout << endl << "Cycles run=" << dec << cycle << endl << endl;
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if (!ok) {
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cout << "You are worthless and weak." << endl;
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exit(EXIT_FAILURE);
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} else {
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cout << "You has opulence." << endl;
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exit(EXIT_SUCCESS);
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}
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} |