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638 lines
23 KiB
Verilog
638 lines
23 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ps / 1 ps
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//*****************************************************************************
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// Description: Tri-Lam Array Wrapper
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module tri_144x78_2r4w(
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// Inputs
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// Power
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inout vdd,
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inout gnd,
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// Clock & Scan
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input [0:`NCLK_WIDTH-1] nclk,
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input func_slp_sl_force,
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input func_slp_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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//-------------------------------------------------------------------
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// Read Port
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//-------------------------------------------------------------------
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input r_late_en_1,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
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output [64-`GPR_WIDTH:77] r_data_out_1,
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input r_late_en_2,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
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output [64-`GPR_WIDTH:77] r_data_out_2,
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//-------------------------------------------------------------------
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// Write Port
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//-------------------------------------------------------------------
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input w_late_en_1,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
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input [64-`GPR_WIDTH:77] w_data_in_1,
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input w_late_en_2,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
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input [64-`GPR_WIDTH:77] w_data_in_2,
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input w_late_en_3,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
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input [64-`GPR_WIDTH:77] w_data_in_3,
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input w_late_en_4,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
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input [64-`GPR_WIDTH:77] w_data_in_4
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);
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// Configuration Statement for NCsim
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//for all:RAM64X1D use entity unisim.RAM64X1D;
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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//-------------------------------------------------------------------
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// Signals
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//-------------------------------------------------------------------
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//reg write_en;
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//reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr;
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//reg [64-`GPR_WIDTH:77] write_data;
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wire write_en;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr;
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wire [64-`GPR_WIDTH:77] write_data;
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wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr;
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wire [0:5] write_addr_arr;
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wire [0:1] wr_mux_ctrl;
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//-------------------------------------------------------------------
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// Latch Signals
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//-------------------------------------------------------------------
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wire w1e_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a_q;
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wire [64-`GPR_WIDTH:77] w1d_q;
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wire w2e_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a_q;
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wire [64-`GPR_WIDTH:77] w2d_q;
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wire w3e_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a_q;
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wire [64-`GPR_WIDTH:77] w3d_q;
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wire w4e_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w4a_q;
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wire [64-`GPR_WIDTH:77] w4d_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
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wire [0:5] read1_addr_arr;
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wire [0:5] read2_addr_arr;
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wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr;
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wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr;
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reg [64-`GPR_WIDTH:77] read1_data;
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reg [64-`GPR_WIDTH:77] read2_data;
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wire [64-`GPR_WIDTH:77] r1d_array[0:(`GPR_POOL*`THREADS-1)/64];
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wire [64-`GPR_WIDTH:77] r2d_array[0:(`GPR_POOL*`THREADS-1)/64];
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wire [64-`GPR_WIDTH:77] r1d_d;
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wire [64-`GPR_WIDTH:77] r2d_d;
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wire [64-`GPR_WIDTH:77] r1d_q;
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wire [64-`GPR_WIDTH:77] r2d_q;
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(* analysis_not_referenced="true" *)
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wire unused;
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wire [64-`GPR_WIDTH:77] unused_port;
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wire [64-`GPR_WIDTH:77] unused_port2;
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//-------------------------------------------------------------------
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// Scanchain
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//-------------------------------------------------------------------
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parameter w1e_offset = 0;
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parameter w1a_offset = w1e_offset + 1;
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parameter w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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parameter w2e_offset = w1d_offset + (`GPR_WIDTH+14);
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parameter w2a_offset = w2e_offset + 1;
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parameter w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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parameter w3e_offset = w2d_offset + (`GPR_WIDTH+14);
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parameter w3a_offset = w3e_offset + 1;
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parameter w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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parameter w4e_offset = w3d_offset + (`GPR_WIDTH+14);
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parameter w4a_offset = w4e_offset + 1;
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parameter w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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parameter r1a_offset = w4d_offset + (`GPR_WIDTH+14);
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parameter r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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parameter r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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parameter r2d_offset = r1d_offset + (`GPR_WIDTH+14);
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parameter scan_right = r2d_offset + (`GPR_WIDTH+14);
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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generate
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begin
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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// Read Control
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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// BYPASS
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assign r1d_d = read1_data;
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assign r2d_d = read2_data;
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assign r_data_out_1 = r1d_q;
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assign r_data_out_2 = r2d_q;
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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// Write Control
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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assign wr_mux_ctrl = {nclk[0], nclk[2]};
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//wtf moved these here to try to get them to work in icarus - they seem to now
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assign write_en = ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
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(wr_mux_ctrl == 2'b01) ? w_late_en_2 :
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(wr_mux_ctrl == 2'b10) ? w_late_en_3 :
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w_late_en_4);
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assign write_addr = ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
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(wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
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(wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
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w_addr_in_4);
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assign write_data = ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
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(wr_mux_ctrl == 2'b01) ? w_data_in_2 :
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(wr_mux_ctrl == 2'b10) ? w_data_in_3 :
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w_data_in_4);
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//always @ ( * )
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//begin
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//write_addr = #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
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// (wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
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// (wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
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// w_addr_in_4);
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//write_en = #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
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// (wr_mux_ctrl == 2'b01) ? w_late_en_2 :
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// (wr_mux_ctrl == 2'b10) ? w_late_en_3 :
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// w_late_en_4);
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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// Depth Control
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// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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//write_data = #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
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// (wr_mux_ctrl == 2'b01) ? w_data_in_2 :
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// (wr_mux_ctrl == 2'b10) ? w_data_in_3 :
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// w_data_in_4);
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//end
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if (((`GPR_POOL*`THREADS - 1)/64) == 0)
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begin : depth1
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if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6)
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begin
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assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
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assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
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assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
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end
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assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr;
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assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q;
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assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q;
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assign write_en_arr[0] = write_en;
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assign read1_en_arr[0] = 1'b1;
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assign read2_en_arr[0] = 1'b1;
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end
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if (((`GPR_POOL*`THREADS - 1)/64) != 0)
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begin : depthMulti
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assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
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assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
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assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
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genvar wen;
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for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1)
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begin : wrenGen
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wire wen_match = wen;
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assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match);
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assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
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assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
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end
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end
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always @( * )
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begin: rdDataMux
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reg [64-`GPR_WIDTH:77] rd1_data;
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reg [64-`GPR_WIDTH:77] rd2_data;
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//(* analysis_not_referenced="true" *)
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integer rdArr;
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rd1_data = {`GPR_WIDTH+14{1'b0}};
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rd2_data = {`GPR_WIDTH+14{1'b0}};
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for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1)
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begin
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rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data;
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rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data;
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end
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read1_data = rd1_data;
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read2_data = rd2_data;
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end
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genvar depth;
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for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1)
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begin : depth_loop
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genvar i;
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for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
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begin : r1
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RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1(
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.SPO(unused_port[i]),
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.DPO(r1d_array[depth][i]), // Port A 1-bit data output
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.A0(write_addr_arr[5]), // Port A - Write Address (A0-A5)
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.A1(write_addr_arr[4]),
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.A2(write_addr_arr[3]),
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.A3(write_addr_arr[2]),
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.A4(write_addr_arr[1]),
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.A5(write_addr_arr[0]),
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//.A(write_addr_arr),
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.D(write_data[i]), // Port A 1-bit data input
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.DPRA0(read1_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5)
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.DPRA1(read1_addr_arr[4]),
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.DPRA2(read1_addr_arr[3]),
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.DPRA3(read1_addr_arr[2]),
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.DPRA4(read1_addr_arr[1]),
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.DPRA5(read1_addr_arr[0]),
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//.DPRA(read1_addr_arr),
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.WCLK(nclk[3]), // Port A write clock input : clk4x
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.WE(write_en_arr[depth]) // Port A write enable input
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);
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end
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//genvar i;
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for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
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begin : r2
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RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2(
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.SPO(unused_port2[i]),
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.DPO(r2d_array[depth][i]), // Port A 1-bit data output
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.A0(write_addr_arr[5]), // Port A - Write Address (A0-A5)
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.A1(write_addr_arr[4]),
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.A2(write_addr_arr[3]),
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.A3(write_addr_arr[2]),
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.A4(write_addr_arr[1]),
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.A5(write_addr_arr[0]),
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//.A(write_addr_arr),
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.D(write_data[i]), // Port A 1-bit data input
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.DPRA0(read2_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5)
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.DPRA1(read2_addr_arr[4]),
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.DPRA2(read2_addr_arr[3]),
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.DPRA3(read2_addr_arr[2]),
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.DPRA4(read2_addr_arr[1]),
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.DPRA5(read2_addr_arr[0]),
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//.DPRA(read2_addr_arr),
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.WCLK(nclk[3]), // Port A write clock input : clk4x
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.WE(write_en_arr[depth]) // Port A write enable input
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);
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end
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end
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end
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endgenerate
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//----------------------------------------------------------------------------------------------------------------------------------------
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// Latches
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//----------------------------------------------------------------------------------------------------------------------------------------
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(tiup),
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.force_t(func_sl_force),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.d_mode(1'b0),
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.sg(sg_0),
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.scin(siv[w1e_offset]),
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.scout(sov[w1e_offset]),
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.din(w_late_en_1),
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.dout(w1e_q)
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);
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tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(tiup),
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.force_t(func_sl_force),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.d_mode(1'b0),
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.sg(sg_0),
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.scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
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.scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
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.din(w_addr_in_1),
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.dout(w1a_q)
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);
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tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(tiup),
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.force_t(func_sl_force),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
|
|
.scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
|
|
.din(w_data_in_1[64 - `GPR_WIDTH:77]),
|
|
.dout(w1d_q)
|
|
);
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w2e_offset]),
|
|
.scout(sov[w2e_offset]),
|
|
.din(w_late_en_2),
|
|
.dout(w2e_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.din(w_addr_in_2),
|
|
.dout(w2a_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
|
|
.scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
|
|
.din(w_data_in_2[64 - `GPR_WIDTH:77]),
|
|
.dout(w2d_q)
|
|
);
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w3e_offset]),
|
|
.scout(sov[w3e_offset]),
|
|
.din(w_late_en_3),
|
|
.dout(w3e_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.din(w_addr_in_3),
|
|
.dout(w3a_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
|
|
.scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
|
|
.din(w_data_in_3[64 - `GPR_WIDTH:77]),
|
|
.dout(w3d_q)
|
|
);
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w4e_offset]),
|
|
.scout(sov[w4e_offset]),
|
|
.din(w_late_en_4),
|
|
.dout(w4e_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.din(w_addr_in_4),
|
|
.dout(w4a_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
|
|
.scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
|
|
.din(w_data_in_4[64 - `GPR_WIDTH:77]),
|
|
.dout(w4d_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.din(r_addr_in_1),
|
|
.dout(r1a_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
|
|
.din(r_addr_in_2),
|
|
.dout(r2a_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
|
|
.scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
|
|
.din(r1d_d),
|
|
.dout(r1d_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(tiup),
|
|
.force_t(func_sl_force),
|
|
.delay_lclkr(delay_lclkr_dc),
|
|
.mpw1_b(mpw1_dc_b),
|
|
.mpw2_b(mpw2_dc_b),
|
|
.thold_b(func_sl_thold_0_b),
|
|
.d_mode(1'b0),
|
|
.sg(sg_0),
|
|
.scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
|
|
.scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
|
|
.din(r2d_d),
|
|
.dout(r2d_q)
|
|
);
|
|
|
|
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
|
|
assign scan_out = sov[0];
|
|
|
|
assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b};
|
|
endmodule
|