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121 lines
3.6 KiB
Verilog
121 lines
3.6 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: Prioritizer
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//
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//*****************************************************************************
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module rv_pri(
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cond,
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pri
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);
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parameter size = 32;
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input [0:size-1] cond;
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output [0:size-1] pri;
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parameter s = size - 1;
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wire [0:s] or_l1;
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wire [0:s] or_l2;
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wire [0:s] or_l3;
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wire [0:s] or_l4;
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wire [0:s] or_l5;
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(* analysis_not_referenced="true" *)
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wire or_cond;
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// Odd Numbered Levels are inverted
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assign or_l1[0] = (~cond[0]);
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assign or_l1[1:s] = ~(cond[0:s - 1] | cond[1:s]);
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generate
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if (s >= 2)
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begin : or_l2_gen0
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assign or_l2[0:1] = (~or_l1[0:1]);
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assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s - 2]);
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end
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endgenerate
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generate
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if (s < 2)
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begin : or_l2_gen1
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assign or_l2 = (~or_l1);
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end
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endgenerate
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generate
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if (s >= 4)
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begin : or_l3_gen0
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assign or_l3[0:3] = (~or_l2[0:3]);
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assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s - 4]);
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end
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endgenerate
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generate
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if (s < 4)
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begin : or_l3_gen1
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assign or_l3 = (~or_l2);
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end
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endgenerate
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generate
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if (s >= 8)
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begin : or_l4_gen0
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assign or_l4[0:7] = (~or_l3[0:7]);
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assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s - 8]);
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end
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endgenerate
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generate
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if (s < 8)
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begin : or_l4_gen1
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assign or_l4 = (~or_l3);
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end
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endgenerate
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generate
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if (s >= 16)
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begin : or_l5_gen0
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assign or_l5[0:15] = (~or_l4[0:15]);
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assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s - 16]);
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end
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endgenerate
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generate
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if (s < 16)
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begin : or_l5_gen1
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assign or_l5 = (~or_l4);
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end
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endgenerate
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//assert size > 32 report "Maximum Size of 32 Exceeded!" severity error;
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assign pri[0] = cond[0];
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assign pri[1:s] = cond[1:s] & or_l5[0:s - 1];
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assign or_cond = (~or_l5[s]);
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endmodule // rv_pri
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