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991 lines
56 KiB
Verilog
991 lines
56 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//********************************************************************
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//*
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//* TITLE: Performance event mux
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//*
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//* NAME: mmq_perf.v
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//*
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//*********************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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`include "mmu_a2o.vh"
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module mmq_perf(
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inout vdd,
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inout gnd,
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(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
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input [0:`NCLK_WIDTH-1] nclk,
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input pc_func_sl_thold_2,
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input pc_func_slp_nsl_thold_2,
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input pc_sg_2,
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input pc_fce_2,
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input tc_ac_ccflush_dc,
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input lcb_clkoff_dc_b,
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input lcb_act_dis_dc,
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input lcb_d_mode_dc,
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input lcb_delay_lclkr_dc,
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input lcb_mpw1_dc_b,
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input lcb_mpw2_dc_b,
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(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
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input scan_in,
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(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
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output scan_out,
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input [0:`MM_THREADS-1] cp_flush_p1,
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input [0:`THDID_WIDTH-1] xu_mm_msr_gs,
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input [0:`THDID_WIDTH-1] xu_mm_msr_pr,
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input xu_mm_ccr2_notlb_b,
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// count event inputs
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input [0:`THDID_WIDTH-1] lq_mm_perf_dtlb,
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input [0:`THDID_WIDTH-1] iu_mm_perf_itlb,
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input lq_mm_derat_req_nonspec,
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input iu_mm_ierat_req_nonspec,
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input [0:9] tlb_cmp_perf_event_t0,
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input [0:9] tlb_cmp_perf_event_t1,
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input [0:1] tlb_cmp_perf_state, // gs & pr
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input tlb_cmp_perf_miss_direct,
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input tlb_cmp_perf_hit_direct,
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input tlb_cmp_perf_hit_indirect,
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input tlb_cmp_perf_hit_first_page,
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input tlb_cmp_perf_ptereload,
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input tlb_cmp_perf_ptereload_noexcep,
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input tlb_cmp_perf_lrat_request,
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input tlb_cmp_perf_lrat_miss,
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input tlb_cmp_perf_pt_fault,
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input tlb_cmp_perf_pt_inelig,
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input tlb_ctl_perf_tlbwec_resv,
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input tlb_ctl_perf_tlbwec_noresv,
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input [0:`THDID_WIDTH-1] derat_req0_thdid,
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input derat_req0_valid,
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input derat_req0_nonspec,
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input [0:`THDID_WIDTH-1] derat_req1_thdid,
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input derat_req1_valid,
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input derat_req1_nonspec,
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input [0:`THDID_WIDTH-1] derat_req2_thdid,
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input derat_req2_valid,
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input derat_req2_nonspec,
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input [0:`THDID_WIDTH-1] derat_req3_thdid,
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input derat_req3_valid,
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input derat_req3_nonspec,
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input [0:`THDID_WIDTH-1] ierat_req0_thdid,
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input ierat_req0_valid,
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input ierat_req0_nonspec,
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input [0:`THDID_WIDTH-1] ierat_req1_thdid,
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input ierat_req1_valid,
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input ierat_req1_nonspec,
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input [0:`THDID_WIDTH-1] ierat_req2_thdid,
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input ierat_req2_valid,
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input ierat_req2_nonspec,
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input [0:`THDID_WIDTH-1] ierat_req3_thdid,
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input ierat_req3_valid,
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input ierat_req3_nonspec,
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input ierat_req_taken,
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input derat_req_taken,
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input [0:`THDID_WIDTH-1] tlb_tag0_thdid,
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input [0:1] tlb_tag0_type, // derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
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input tlb_tag0_nonspec,
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input tlb_tag4_nonspec,
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input tlb_seq_idle,
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input inval_perf_tlbilx,
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input inval_perf_tlbivax,
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input inval_perf_tlbivax_snoop,
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input inval_perf_tlb_flush,
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input htw_req0_valid,
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input [0:`THDID_WIDTH-1] htw_req0_thdid,
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input [0:1] htw_req0_type,
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input htw_req1_valid,
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input [0:`THDID_WIDTH-1] htw_req1_thdid,
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input [0:1] htw_req1_type,
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input htw_req2_valid,
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input [0:`THDID_WIDTH-1] htw_req2_thdid,
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input [0:1] htw_req2_type,
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input htw_req3_valid,
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input [0:`THDID_WIDTH-1] htw_req3_thdid,
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input [0:1] htw_req3_type,
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`ifdef WAIT_UPDATES
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input [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q,
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// 0:1 - thdid/val
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// 2 - I=0/D=1
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// 3 - TLB miss
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// 4 - Storage int (TLBI/PTfault)
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// 5 - LRAT miss
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// 6 - Mcheck
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`endif
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// control inputs
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input [0:`MESR1_WIDTH*`THREADS-1] mmq_spr_event_mux_ctrls,
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input [0:2] pc_mm_event_count_mode, // 0=count events in problem state,1=sup,2=hypv
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input rp_mm_event_bus_enable_q, // act for perf related latches from repower
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input [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_in,
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output [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_out
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);
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parameter rp_mm_event_bus_enable_offset = 0;
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parameter mmq_spr_event_mux_ctrls_offset = rp_mm_event_bus_enable_offset + 1;
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parameter pc_mm_event_count_mode_offset = mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS;
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parameter xu_mm_msr_gs_offset = pc_mm_event_count_mode_offset + 3;
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parameter xu_mm_msr_pr_offset = xu_mm_msr_gs_offset + `THDID_WIDTH;
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parameter event_bus_out_offset = xu_mm_msr_pr_offset + `THDID_WIDTH;
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parameter scan_right = event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1;
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wire [0:`PERF_EVENT_WIDTH*`THREADS-1] event_bus_out_d, event_bus_out_q;
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wire rp_mm_event_bus_enable_int_q;
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wire [0:`MESR1_WIDTH*`THREADS-1] mmq_spr_event_mux_ctrls_q;
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wire [0:2] pc_mm_event_count_mode_q; // 0=count events in problem state,1=sup,2=hypv
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wire [0:23] mm_perf_event_t0_d, mm_perf_event_t0_q; // t0 threadwise events
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wire [0:23] mm_perf_event_t1_d, mm_perf_event_t1_q; // t1 threadwise events
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wire [0:31] mm_perf_event_core_level_d, mm_perf_event_core_level_q; // thread independent events
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wire [0:`THDID_WIDTH-1] xu_mm_msr_gs_q;
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wire [0:`THDID_WIDTH-1] xu_mm_msr_pr_q;
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wire [0:`THDID_WIDTH] event_en;
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wire [0:`PERF_MUX_WIDTH-1] unit_t0_events_in;
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`ifndef THREADS1
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wire [0:`PERF_MUX_WIDTH-1] unit_t1_events_in;
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`endif
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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wire tidn;
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wire tiup;
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wire pc_func_sl_thold_1;
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wire pc_func_sl_thold_0;
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wire pc_func_sl_thold_0_b;
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wire pc_func_slp_nsl_thold_1;
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wire pc_func_slp_nsl_thold_0;
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wire pc_func_slp_nsl_thold_0_b;
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wire pc_func_slp_nsl_force;
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wire pc_sg_1;
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wire pc_sg_0;
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wire pc_fce_1;
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wire pc_fce_0;
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wire force_t;
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wire [0:79] tri_regk_unused_scan;
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//---------------------------------------------------------------------
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// Logic
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//---------------------------------------------------------------------
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assign tidn = 1'b0;
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assign tiup = 1'b1;
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assign event_en[0:3] = (xu_mm_msr_pr_q[0:3] & {4{pc_mm_event_count_mode_q[0]}}) |
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// User problem state
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((~xu_mm_msr_pr_q[0:3]) & xu_mm_msr_gs_q[0:3] & {4{pc_mm_event_count_mode_q[1]}}) |
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// Guest Supervisor
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((~xu_mm_msr_pr_q[0:3]) & (~xu_mm_msr_gs_q[0:3]) & {4{pc_mm_event_count_mode_q[2]}});
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// Hypervisor
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//tlb_cmp_perf_state: 0 =gs, 1=pr
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assign event_en[4] = (tlb_cmp_perf_state[1] & pc_mm_event_count_mode_q[0]) |
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// User problem state
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(tlb_cmp_perf_state[0] & (~tlb_cmp_perf_state[1]) & pc_mm_event_count_mode_q[1]) |
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// Guest Supervisor
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((~tlb_cmp_perf_state[0]) & (~tlb_cmp_perf_state[1]) & pc_mm_event_count_mode_q[2]);
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// Hypervisor
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//--------------------------------------------------
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// t* threadwise event list
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//--------------------------------------------------
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// 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch)
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// 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch)
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// 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception)
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// 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch)
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// 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi)
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// 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op)
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// 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op)
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// 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception)
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// 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op)
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// 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi)
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// 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency)
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// 11 DERAT miss (or latency), edge (or level) (total derat misses or latency)
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// 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch)
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// 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch)
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// 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op)
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// 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op)
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// 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency)
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// 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency)
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// 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch)
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// 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch)
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// 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op)
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// 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op)
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// 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency)
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// 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency)
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//--------------------------------------------------
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// core single event list
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//--------------------------------------------------
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// 0 IERAT miss total (part of direct entry search total)
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// 1 DERAT miss total (part of direct entry search total)
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// 2 TLB miss direct entry total (total TLB ind=0 misses)
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// 3 TLB hit direct entry first page size
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//--------------------------------------------------
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// 4 TLB indirect entry hits total (=page table searches)
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// 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss)
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// 6 LRAT translation request total (for GS=1 tlbwe and ptereload)
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// 7 LRAT misses total (for GS=1 tlbwe and ptereload)
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//--------------------------------------------------
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// 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi)
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// 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi)
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// 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match)
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// 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match)
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//--------------------------------------------------
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// 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total)
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// 13 tlbivax invalidations sourced total (sourced tlbivax on this core total)
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// 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care)
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// 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards)
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//--------------------------------------------------
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// 16 IERAT NONSPECULATIVE miss total (part of direct entry search total)
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// 17 DERAT NONSPECULATIVE miss total (part of direct entry search total)
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// 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses)
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// 19 TLB NONSPECULATIVE hit direct entry first page size
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//--------------------------------------------------
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// 20 IERAT SPECULATIVE miss total (part of direct entry search total)
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// 21 DERAT SPECULATIVE miss total (part of direct entry search total)
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// 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses)
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// 23 TLB SPECULATIVE hit direct entry first page size
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//--------------------------------------------------
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// 24 ERAT miss total (TLB direct entry search total for both I and D sides)
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// 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides)
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// 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides)
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// 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides)
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// 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides)
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// 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides)
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// 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1)
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// 31 Raw Total ERAT misses, either mode
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//--------------------------------------------------
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// t* threadwise event list
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//--------------------------------------------------
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// 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch)
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// 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch)
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// 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception)
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// 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch)
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// 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi)
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// 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op)
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// 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op)
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// 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception)
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// 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op)
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// 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi)
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assign mm_perf_event_t0_d[0:9] = tlb_cmp_perf_event_t0[0:9] & {10{event_en[0]}};
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// 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency)
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// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
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assign mm_perf_event_t0_d[10] = (((ierat_req0_valid & ierat_req0_thdid[0]) |
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(ierat_req1_valid & ierat_req1_thdid[0]) |
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(ierat_req2_valid & ierat_req2_thdid[0]) |
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(ierat_req3_valid & ierat_req3_thdid[0]) |
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// ierat nonspec miss request
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((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0]) |
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// searching tlb for direct entry, or ptereload of instr
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(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[0]) |
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(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[0]) |
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(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[0]) |
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(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
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// htw servicing miss of instr
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(iu_mm_perf_itlb[0] & (~xu_mm_ccr2_notlb_b));
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// 11 DERAT miss (or latency), edge (or level) (total derat misses or latency)
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// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
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assign mm_perf_event_t0_d[11] = (((derat_req0_valid & derat_req0_thdid[0]) |
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(derat_req1_valid & derat_req1_thdid[0]) |
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(derat_req2_valid & derat_req2_thdid[0]) |
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(derat_req3_valid & derat_req3_thdid[0]) |
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// derat nonspec miss request
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((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0]) |
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// searching tlb for direct entry, or ptereload of data
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(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[0]) |
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(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[0]) |
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(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[0]) |
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(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
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// htw servicing miss of data
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(lq_mm_perf_dtlb[0] & (~xu_mm_ccr2_notlb_b));
|
|
|
|
// 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch)
|
|
assign mm_perf_event_t0_d[12] = tlb_cmp_perf_event_t0[0] & event_en[0] & tlb_tag4_nonspec;
|
|
|
|
// 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch)
|
|
assign mm_perf_event_t0_d[13] = tlb_cmp_perf_event_t0[1] & event_en[0] & tlb_tag4_nonspec;
|
|
|
|
// 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t0_d[14] = tlb_cmp_perf_event_t0[5] & event_en[0] & tlb_tag4_nonspec;
|
|
|
|
// 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t0_d[15] = tlb_cmp_perf_event_t0[6] & event_en[0] & tlb_tag4_nonspec;
|
|
|
|
// 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
assign mm_perf_event_t0_d[16] = (((ierat_req0_valid & ierat_req0_nonspec & ierat_req0_thdid[0]) |
|
|
(ierat_req1_valid & ierat_req1_nonspec & ierat_req1_thdid[0]) |
|
|
(ierat_req2_valid & ierat_req2_nonspec & ierat_req2_thdid[0]) |
|
|
(ierat_req3_valid & ierat_req3_nonspec & ierat_req3_thdid[0]) |
|
|
// ierat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0] & tlb_tag0_nonspec) |
|
|
// searching tlb for direct entry, or ptereload of instr
|
|
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[0]) |
|
|
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[0]) |
|
|
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[0]) |
|
|
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
|
|
// htw servicing miss of instr
|
|
(iu_mm_perf_itlb[0] & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b));
|
|
|
|
// 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
assign mm_perf_event_t0_d[17] = (((derat_req0_valid & derat_req0_nonspec & derat_req0_thdid[0]) |
|
|
(derat_req1_valid & derat_req1_nonspec & derat_req1_thdid[0]) |
|
|
(derat_req2_valid & derat_req2_nonspec & derat_req2_thdid[0]) |
|
|
(derat_req3_valid & derat_req3_nonspec & derat_req3_thdid[0]) |
|
|
// derat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0] & tlb_tag0_nonspec) |
|
|
// searching tlb for direct entry, or ptereload of data
|
|
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[0]) |
|
|
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[0]) |
|
|
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[0]) |
|
|
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) |
|
|
// htw servicing miss of data
|
|
(lq_mm_perf_dtlb[0] & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b));
|
|
|
|
|
|
// 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch)
|
|
assign mm_perf_event_t0_d[18] = tlb_cmp_perf_event_t0[0] & event_en[0] & ~tlb_tag4_nonspec;
|
|
|
|
// 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch)
|
|
assign mm_perf_event_t0_d[19] = tlb_cmp_perf_event_t0[1] & event_en[0] & ~tlb_tag4_nonspec;
|
|
|
|
// 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t0_d[20] = tlb_cmp_perf_event_t0[5] & event_en[0] & ~tlb_tag4_nonspec;
|
|
|
|
// 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t0_d[21] = tlb_cmp_perf_event_t0[6] & event_en[0] & ~tlb_tag4_nonspec;
|
|
|
|
// 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
// NOTE - speculative requests do not envoke h/w tablewalker actions..
|
|
// ..tablewalker handles only non-speculative requests
|
|
assign mm_perf_event_t0_d[22] = (((ierat_req0_valid & ~ierat_req0_nonspec & ierat_req0_thdid[0]) |
|
|
(ierat_req1_valid & ~ierat_req1_nonspec & ierat_req1_thdid[0]) |
|
|
(ierat_req2_valid & ~ierat_req2_nonspec & ierat_req2_thdid[0]) |
|
|
(ierat_req3_valid & ~ierat_req3_nonspec & ierat_req3_thdid[0]) |
|
|
// ierat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
|
|
// searching tlb for direct entry, or ptereload of instr
|
|
(iu_mm_perf_itlb[0] & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
|
|
|
|
// 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
// NOTE - speculative requests do not envoke h/w tablewalker actions..
|
|
// ..tablewalker handles only non-speculative requests
|
|
assign mm_perf_event_t0_d[23] = (((derat_req0_valid & ~derat_req0_nonspec & derat_req0_thdid[0]) |
|
|
(derat_req1_valid & ~derat_req1_nonspec & derat_req1_thdid[0]) |
|
|
(derat_req2_valid & ~derat_req2_nonspec & derat_req2_thdid[0]) |
|
|
(derat_req3_valid & ~derat_req3_nonspec & derat_req3_thdid[0]) |
|
|
// derat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
|
|
// searching tlb for direct entry, or ptereload of data
|
|
(lq_mm_perf_dtlb[0] & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
|
|
|
|
|
|
//--------------------------------------------------
|
|
// t* threadwise event list
|
|
//--------------------------------------------------
|
|
// 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch)
|
|
// 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch)
|
|
// 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception)
|
|
// 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch)
|
|
// 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi)
|
|
// 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op)
|
|
// 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op)
|
|
// 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception)
|
|
// 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op)
|
|
// 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi)
|
|
assign mm_perf_event_t1_d[0:9] = tlb_cmp_perf_event_t1[0:9] & {10{event_en[1]}};
|
|
|
|
// 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
assign mm_perf_event_t1_d[10] = (((ierat_req0_valid & ierat_req0_thdid[1]) |
|
|
(ierat_req1_valid & ierat_req1_thdid[1]) |
|
|
(ierat_req2_valid & ierat_req2_thdid[1]) |
|
|
(ierat_req3_valid & ierat_req3_thdid[1]) |
|
|
// ierat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1]) |
|
|
// searching tlb for direct entry, or ptereload of instr
|
|
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[1]) |
|
|
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[1]) |
|
|
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[1]) |
|
|
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
|
|
// htw servicing miss of instr
|
|
(iu_mm_perf_itlb[1] & (~xu_mm_ccr2_notlb_b));
|
|
|
|
// 11 DERAT miss (or latency), edge (or level) (total derat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
assign mm_perf_event_t1_d[11] = (((derat_req0_valid & derat_req0_thdid[1]) |
|
|
(derat_req1_valid & derat_req1_thdid[1]) |
|
|
(derat_req2_valid & derat_req2_thdid[1]) |
|
|
(derat_req3_valid & derat_req3_thdid[1]) |
|
|
// derat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1]) |
|
|
// searching tlb for direct entry, or ptereload of data
|
|
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[1]) |
|
|
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[1]) |
|
|
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[1]) |
|
|
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
|
|
// htw servicing miss of data
|
|
(lq_mm_perf_dtlb[1] & (~xu_mm_ccr2_notlb_b));
|
|
|
|
|
|
// 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch)
|
|
assign mm_perf_event_t1_d[12] = tlb_cmp_perf_event_t1[0] & event_en[1] & tlb_tag4_nonspec;
|
|
|
|
// 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch)
|
|
assign mm_perf_event_t1_d[13] = tlb_cmp_perf_event_t1[1] & event_en[1] & tlb_tag4_nonspec;
|
|
|
|
// 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t1_d[14] = tlb_cmp_perf_event_t1[5] & event_en[1] & tlb_tag4_nonspec;
|
|
|
|
// 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t1_d[15] = tlb_cmp_perf_event_t1[6] & event_en[1] & tlb_tag4_nonspec;
|
|
|
|
// 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency)
|
|
assign mm_perf_event_t1_d[16] = (((ierat_req0_valid & ierat_req0_nonspec & ierat_req0_thdid[1]) |
|
|
(ierat_req1_valid & ierat_req1_nonspec & ierat_req1_thdid[1]) |
|
|
(ierat_req2_valid & ierat_req2_nonspec & ierat_req2_thdid[1]) |
|
|
(ierat_req3_valid & ierat_req3_nonspec & ierat_req3_thdid[1]) |
|
|
// ierat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1] & tlb_tag0_nonspec) |
|
|
// searching tlb for direct entry, or ptereload of instr
|
|
(htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[1]) |
|
|
(htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[1]) |
|
|
(htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[1]) |
|
|
(htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
|
|
// htw servicing miss of instr
|
|
(iu_mm_perf_itlb[1] & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b));
|
|
|
|
// 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency)
|
|
assign mm_perf_event_t1_d[17] = (((derat_req0_valid & derat_req0_nonspec & derat_req0_thdid[1]) |
|
|
(derat_req1_valid & derat_req1_nonspec & derat_req1_thdid[1]) |
|
|
(derat_req2_valid & derat_req2_nonspec & derat_req2_thdid[1]) |
|
|
(derat_req3_valid & derat_req3_nonspec & derat_req3_thdid[1]) |
|
|
// derat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1] & tlb_tag0_nonspec) |
|
|
// searching tlb for direct entry, or ptereload of data
|
|
(htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[1]) |
|
|
(htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[1]) |
|
|
(htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[1]) |
|
|
(htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) |
|
|
// htw servicing miss of data
|
|
(lq_mm_perf_dtlb[1] & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b));
|
|
|
|
|
|
// 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch)
|
|
assign mm_perf_event_t1_d[18] = tlb_cmp_perf_event_t1[0] & event_en[1] & ~tlb_tag4_nonspec;
|
|
|
|
// 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch)
|
|
assign mm_perf_event_t1_d[19] = tlb_cmp_perf_event_t1[1] & event_en[1] & ~tlb_tag4_nonspec;
|
|
|
|
// 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t1_d[20] = tlb_cmp_perf_event_t1[5] & event_en[1] & ~tlb_tag4_nonspec;
|
|
|
|
// 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op)
|
|
assign mm_perf_event_t1_d[21] = tlb_cmp_perf_event_t1[6] & event_en[1] & ~tlb_tag4_nonspec;
|
|
|
|
// 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
// NOTE - speculative requests do not envoke h/w tablewalker actions..
|
|
// ..tablewalker handles only non-speculative requests
|
|
assign mm_perf_event_t1_d[22] = (((ierat_req0_valid & ~ierat_req0_nonspec & ierat_req0_thdid[1]) |
|
|
(ierat_req1_valid & ~ierat_req1_nonspec & ierat_req1_thdid[1]) |
|
|
(ierat_req2_valid & ~ierat_req2_nonspec & ierat_req2_thdid[1]) |
|
|
(ierat_req3_valid & ~ierat_req3_nonspec & ierat_req3_thdid[1]) |
|
|
// ierat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
|
|
// searching tlb for direct entry, or ptereload of instr
|
|
(iu_mm_perf_itlb[1] & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
|
|
|
|
// 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency)
|
|
// type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload
|
|
// NOTE - speculative requests do not envoke h/w tablewalker actions..
|
|
// ..tablewalker handles only non-speculative requests
|
|
assign mm_perf_event_t1_d[23] = (((derat_req0_valid & ~derat_req0_nonspec & derat_req0_thdid[1]) |
|
|
(derat_req1_valid & ~derat_req1_nonspec & derat_req1_thdid[1]) |
|
|
(derat_req2_valid & ~derat_req2_nonspec & derat_req2_thdid[1]) |
|
|
(derat_req3_valid & ~derat_req3_nonspec & derat_req3_thdid[1]) |
|
|
// derat nonspec miss request
|
|
((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) |
|
|
// searching tlb for direct entry, or ptereload of data
|
|
(lq_mm_perf_dtlb[1] & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b));
|
|
|
|
|
|
|
|
//--------------------------------------------------
|
|
// core single event list
|
|
//--------------------------------------------------
|
|
// 0 IERAT miss total (part of direct entry search total)
|
|
// 1 DERAT miss total (part of direct entry search total)
|
|
// 2 TLB miss direct entry total (total TLB ind=0 misses)
|
|
// 3 TLB hit direct entry first page size
|
|
//--------------------------------------------------
|
|
// 4 TLB indirect entry hits total (=page table searches)
|
|
// 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss)
|
|
// 6 LRAT translation request total (for GS=1 tlbwe and ptereload)
|
|
// 7 LRAT misses total (for GS=1 tlbwe and ptereload)
|
|
//--------------------------------------------------
|
|
// 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi)
|
|
// 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi)
|
|
// 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match)
|
|
// 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match)
|
|
//--------------------------------------------------
|
|
// 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total)
|
|
// 13 tlbivax invalidations sourced total (sourced tlbivax on this core total)
|
|
// 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care)
|
|
// 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards)
|
|
//--------------------------------------------------
|
|
// 16 IERAT NONSPECULATIVE miss total (part of direct entry search total)
|
|
// 17 DERAT NONSPECULATIVE miss total (part of direct entry search total)
|
|
// 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses)
|
|
// 19 TLB NONSPECULATIVE hit direct entry first page size
|
|
//--------------------------------------------------
|
|
// 20 IERAT SPECULATIVE miss total (part of direct entry search total)
|
|
// 21 DERAT SPECULATIVE miss total (part of direct entry search total)
|
|
// 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses)
|
|
// 23 TLB SPECULATIVE hit direct entry first page size
|
|
//--------------------------------------------------
|
|
// 24 ERAT miss total (TLB direct entry search total for both I and D sides)
|
|
// 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides)
|
|
// 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides)
|
|
// 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides)
|
|
// 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides)
|
|
// 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides)
|
|
// 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1)
|
|
// 31 Raw Total ERAT misses, either mode
|
|
|
|
// 0 IERAT miss total (part of direct entry search total)
|
|
assign mm_perf_event_core_level_d[0] = (ierat_req_taken & xu_mm_ccr2_notlb_b) |
|
|
( |(iu_mm_perf_itlb) & (~xu_mm_ccr2_notlb_b) );
|
|
|
|
// 1 DERAT miss total (part of direct entry search total)
|
|
assign mm_perf_event_core_level_d[1] = (derat_req_taken & xu_mm_ccr2_notlb_b) |
|
|
( |(lq_mm_perf_dtlb) & (~xu_mm_ccr2_notlb_b) );
|
|
|
|
// 2 TLB miss direct entry total (total TLB ind=0 misses)
|
|
assign mm_perf_event_core_level_d[2] = tlb_cmp_perf_miss_direct & event_en[4];
|
|
|
|
// 3 TLB hit direct entry first page size
|
|
assign mm_perf_event_core_level_d[3] = tlb_cmp_perf_hit_first_page & event_en[4];
|
|
|
|
// 4 TLB indirect entry hits total (=page table searches)
|
|
assign mm_perf_event_core_level_d[4] = tlb_cmp_perf_hit_indirect & event_en[4];
|
|
|
|
// 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss)
|
|
assign mm_perf_event_core_level_d[5] = tlb_cmp_perf_ptereload_noexcep & event_en[4];
|
|
|
|
// 6 LRAT translation request total (for GS=1 tlbwe and ptereload)
|
|
assign mm_perf_event_core_level_d[6] = tlb_cmp_perf_lrat_request & event_en[4];
|
|
|
|
// 7 LRAT misses total (for GS=1 tlbwe and ptereload)
|
|
assign mm_perf_event_core_level_d[7] = tlb_cmp_perf_lrat_miss & event_en[4];
|
|
|
|
// 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi)
|
|
assign mm_perf_event_core_level_d[8] = tlb_cmp_perf_pt_fault & event_en[4];
|
|
|
|
// 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi)
|
|
assign mm_perf_event_core_level_d[9] = tlb_cmp_perf_pt_inelig & event_en[4];
|
|
|
|
// 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match)
|
|
assign mm_perf_event_core_level_d[10] = tlb_ctl_perf_tlbwec_noresv & event_en[4];
|
|
|
|
// 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match)
|
|
assign mm_perf_event_core_level_d[11] = tlb_ctl_perf_tlbwec_resv & event_en[4];
|
|
|
|
// 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total)
|
|
assign mm_perf_event_core_level_d[12] = inval_perf_tlbilx;
|
|
|
|
// 13 tlbivax invalidations sourced total (sourced tlbivax on this core total)
|
|
assign mm_perf_event_core_level_d[13] = inval_perf_tlbivax;
|
|
|
|
// 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care)
|
|
assign mm_perf_event_core_level_d[14] = inval_perf_tlbivax_snoop;
|
|
|
|
// 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards)
|
|
assign mm_perf_event_core_level_d[15] = inval_perf_tlb_flush;
|
|
|
|
//--------------------------------------------------
|
|
// 16 IERAT NONSPECULATIVE miss total (part of direct entry search total)
|
|
assign mm_perf_event_core_level_d[16] = (mm_perf_event_core_level_q[0] & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // ierat_req_taken, nonspec
|
|
( |(iu_mm_perf_itlb) & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b) );
|
|
|
|
// 17 DERAT NONSPECULATIVE miss total (part of direct entry search total)
|
|
assign mm_perf_event_core_level_d[17] = (mm_perf_event_core_level_q[1] & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // derat_req_taken, nonspec
|
|
( |(lq_mm_perf_dtlb) & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b) );
|
|
|
|
// 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses)
|
|
assign mm_perf_event_core_level_d[18] = tlb_cmp_perf_miss_direct & event_en[4] & tlb_tag4_nonspec;
|
|
|
|
// 19 TLB NONSPECULATIVE hit direct entry first page size
|
|
assign mm_perf_event_core_level_d[19] = tlb_cmp_perf_hit_first_page & event_en[4] & tlb_tag4_nonspec;
|
|
|
|
//--------------------------------------------------
|
|
// 20 IERAT SPECULATIVE miss total (part of direct entry search total)
|
|
assign mm_perf_event_core_level_d[20] = (mm_perf_event_core_level_q[0] & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // ierat_req_taken, spec
|
|
( |(iu_mm_perf_itlb) & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b) );
|
|
|
|
// 21 DERAT SPECULATIVE miss total (part of direct entry search total)
|
|
assign mm_perf_event_core_level_d[21] = (mm_perf_event_core_level_q[1] & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // derat_req_taken, spec
|
|
( |(lq_mm_perf_dtlb) & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b) );
|
|
|
|
// 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses)
|
|
assign mm_perf_event_core_level_d[22] = tlb_cmp_perf_miss_direct & event_en[4] & ~tlb_tag4_nonspec;
|
|
|
|
// 23 TLB SPECULATIVE hit direct entry first page size
|
|
assign mm_perf_event_core_level_d[23] = tlb_cmp_perf_hit_first_page & event_en[4] & ~tlb_tag4_nonspec;
|
|
|
|
//--------------------------------------------------
|
|
// 24 ERAT miss total (TLB direct entry search total for both I and D sides)
|
|
assign mm_perf_event_core_level_d[24] = (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]); // i/derat_req_taken (tlb mode),
|
|
// or raw i/derat misses (erat-only mode)
|
|
|
|
// 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides)
|
|
assign mm_perf_event_core_level_d[25] = ( (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]) & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b ) | // nonspec i/derat_req_taken (tlb mode)
|
|
( (mm_perf_event_core_level_q[16] | mm_perf_event_core_level_q[17]) & (~xu_mm_ccr2_notlb_b) ); // raw nonspec i/derat misses (erat-only mode)
|
|
|
|
// 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides)
|
|
assign mm_perf_event_core_level_d[26] = ( (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]) & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b ) | // spec i/derat_req_taken (tlb mode)
|
|
( (mm_perf_event_core_level_q[20] | mm_perf_event_core_level_q[21]) & (~xu_mm_ccr2_notlb_b) ); // raw spec i/derat misses (erat-only mode)
|
|
|
|
// 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides)
|
|
assign mm_perf_event_core_level_d[27] = tlb_cmp_perf_hit_direct & event_en[4];
|
|
|
|
// 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides)
|
|
assign mm_perf_event_core_level_d[28] = tlb_cmp_perf_hit_direct & event_en[4] & tlb_tag4_nonspec;
|
|
|
|
// 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides)
|
|
assign mm_perf_event_core_level_d[29] = tlb_cmp_perf_hit_direct & event_en[4] & ~tlb_tag4_nonspec;
|
|
|
|
// 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1)
|
|
assign mm_perf_event_core_level_d[30] = tlb_cmp_perf_ptereload & event_en[4];
|
|
|
|
// 31 Raw Total ERAT misses, either mode
|
|
assign mm_perf_event_core_level_d[31] = ( |(iu_mm_perf_itlb) | |(lq_mm_perf_dtlb) );
|
|
|
|
//--------------------------------------------------
|
|
// end of core single event list
|
|
//--------------------------------------------------
|
|
|
|
assign unit_t0_events_in = {1'b0, mm_perf_event_t0_q[0:23],
|
|
7'b0,
|
|
mm_perf_event_core_level_q[0:31]};
|
|
|
|
tri_event_mux1t #(.EVENTS_IN(`PERF_MUX_WIDTH), .EVENTS_OUT(4)) event_mux0(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.select_bits(mmq_spr_event_mux_ctrls_q[0:`MESR1_WIDTH - 1]),
|
|
.unit_events_in(unit_t0_events_in[1:63]),
|
|
.event_bus_in(mm_event_bus_in[0:3]),
|
|
.event_bus_out(event_bus_out_d[0:3])
|
|
);
|
|
|
|
`ifndef THREADS1
|
|
assign unit_t1_events_in = {1'b0, mm_perf_event_t1_q[0:23],
|
|
7'b0,
|
|
mm_perf_event_core_level_q[0:31]};
|
|
|
|
|
|
tri_event_mux1t #(.EVENTS_IN(`PERF_MUX_WIDTH), .EVENTS_OUT(4)) event_mux1(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.select_bits(mmq_spr_event_mux_ctrls_q[`MESR1_WIDTH:`MESR1_WIDTH+`MESR2_WIDTH - 1]),
|
|
.unit_events_in(unit_t1_events_in),
|
|
.event_bus_in(mm_event_bus_in[4:7]),
|
|
.event_bus_out(event_bus_out_d[4:7])
|
|
);
|
|
`endif
|
|
|
|
assign mm_event_bus_out = event_bus_out_q;
|
|
|
|
|
|
//---------------------------------------------------------------------
|
|
// Latches
|
|
//---------------------------------------------------------------------
|
|
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rp_mm_event_bus_enable_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.thold_b(pc_func_sl_thold_0_b),
|
|
.sg(pc_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.scin(siv[rp_mm_event_bus_enable_offset]),
|
|
.scout(sov[rp_mm_event_bus_enable_offset]),
|
|
.din(rp_mm_event_bus_enable_q), // yes, this in the input name
|
|
.dout(rp_mm_event_bus_enable_int_q) // this is local internal version
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH*`THREADS), .INIT(0)) mmq_spr_event_mux_ctrls_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.thold_b(pc_func_sl_thold_0_b),
|
|
.sg(pc_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.scin(siv[mmq_spr_event_mux_ctrls_offset:mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS - 1]),
|
|
.scout(sov[mmq_spr_event_mux_ctrls_offset:mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS - 1]),
|
|
.din(mmq_spr_event_mux_ctrls),
|
|
.dout(mmq_spr_event_mux_ctrls_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_mm_event_count_mode_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.thold_b(pc_func_sl_thold_0_b),
|
|
.sg(pc_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.scin(siv[pc_mm_event_count_mode_offset:pc_mm_event_count_mode_offset + 3 - 1]),
|
|
.scout(sov[pc_mm_event_count_mode_offset:pc_mm_event_count_mode_offset + 3 - 1]),
|
|
.din(pc_mm_event_count_mode),
|
|
.dout(pc_mm_event_count_mode_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_gs_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rp_mm_event_bus_enable_int_q),
|
|
.thold_b(pc_func_sl_thold_0_b),
|
|
.sg(pc_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.scin(siv[xu_mm_msr_gs_offset:xu_mm_msr_gs_offset + `THDID_WIDTH - 1]),
|
|
.scout(sov[xu_mm_msr_gs_offset:xu_mm_msr_gs_offset + `THDID_WIDTH - 1]),
|
|
.din(xu_mm_msr_gs),
|
|
.dout(xu_mm_msr_gs_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_pr_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rp_mm_event_bus_enable_int_q),
|
|
.thold_b(pc_func_sl_thold_0_b),
|
|
.sg(pc_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.scin(siv[xu_mm_msr_pr_offset:xu_mm_msr_pr_offset + `THDID_WIDTH - 1]),
|
|
.scout(sov[xu_mm_msr_pr_offset:xu_mm_msr_pr_offset + `THDID_WIDTH - 1]),
|
|
.din(xu_mm_msr_pr),
|
|
.dout(xu_mm_msr_pr_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(`PERF_EVENT_WIDTH*`THREADS), .INIT(0)) event_bus_out_latch(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(rp_mm_event_bus_enable_int_q),
|
|
.thold_b(pc_func_sl_thold_0_b),
|
|
.sg(pc_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.scin(siv[event_bus_out_offset:event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1]),
|
|
.scout(sov[event_bus_out_offset:event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1]),
|
|
.din(event_bus_out_d),
|
|
.dout(event_bus_out_q)
|
|
);
|
|
|
|
|
|
tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t0_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(rp_mm_event_bus_enable_int_q),
|
|
.sg(pc_sg_0),
|
|
.force_t(pc_func_slp_nsl_force),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.thold_b(pc_func_slp_nsl_thold_0_b),
|
|
.scin(tri_regk_unused_scan[0:23]),
|
|
.scout(tri_regk_unused_scan[0:23]),
|
|
.din(mm_perf_event_t0_d),
|
|
.dout(mm_perf_event_t0_q)
|
|
);
|
|
|
|
|
|
tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t1_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(rp_mm_event_bus_enable_int_q),
|
|
.sg(pc_sg_0),
|
|
.force_t(pc_func_slp_nsl_force),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.thold_b(pc_func_slp_nsl_thold_0_b),
|
|
.scin(tri_regk_unused_scan[24:47]),
|
|
.scout(tri_regk_unused_scan[24:47]),
|
|
.din(mm_perf_event_t1_d),
|
|
.dout(mm_perf_event_t1_q)
|
|
);
|
|
|
|
|
|
tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_core_level_latch(
|
|
.nclk(nclk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.act(rp_mm_event_bus_enable_int_q),
|
|
.sg(pc_sg_0),
|
|
.force_t(pc_func_slp_nsl_force),
|
|
.d_mode(lcb_d_mode_dc),
|
|
.delay_lclkr(lcb_delay_lclkr_dc),
|
|
.mpw1_b(lcb_mpw1_dc_b),
|
|
.mpw2_b(lcb_mpw2_dc_b),
|
|
.thold_b(pc_func_slp_nsl_thold_0_b),
|
|
.scin(tri_regk_unused_scan[48:79]),
|
|
.scout(tri_regk_unused_scan[48:79]),
|
|
.din(mm_perf_event_core_level_d),
|
|
.dout(mm_perf_event_core_level_q)
|
|
);
|
|
|
|
|
|
|
|
//-----------------------------------------------
|
|
// pervasive
|
|
//-----------------------------------------------
|
|
|
|
|
|
tri_plat #(.WIDTH(4)) perv_2to1_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(tc_ac_ccflush_dc),
|
|
.din( {pc_func_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ),
|
|
.q( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} )
|
|
);
|
|
|
|
|
|
tri_plat #(.WIDTH(4)) perv_1to0_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(tc_ac_ccflush_dc),
|
|
.din( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ),
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|
.q( {pc_func_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} )
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|
);
|
|
|
|
|
|
tri_lcbor perv_lcbor(
|
|
.clkoff_b(lcb_clkoff_dc_b),
|
|
.thold(pc_func_sl_thold_0),
|
|
.sg(pc_sg_0),
|
|
.act_dis(lcb_act_dis_dc),
|
|
.force_t(force_t),
|
|
.thold_b(pc_func_sl_thold_0_b)
|
|
);
|
|
|
|
|
|
tri_lcbor perv_nsl_lcbor(
|
|
.clkoff_b(lcb_clkoff_dc_b),
|
|
.thold(pc_func_slp_nsl_thold_0),
|
|
.sg(pc_fce_0),
|
|
.act_dis(tidn),
|
|
.force_t(pc_func_slp_nsl_force),
|
|
.thold_b(pc_func_slp_nsl_thold_0_b)
|
|
);
|
|
|
|
//---------------------------------------------------------------------
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|
// Scan
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|
//---------------------------------------------------------------------
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|
assign siv[0:scan_right] = {sov[1:scan_right], scan_in};
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|
assign scan_out = sov[0];
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|
|
|
|
|
endmodule
|