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316 lines
9.8 KiB
Verilog
316 lines
9.8 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *********************************************************************
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//
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// This is the ENTITY for iuq_ram
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//
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// *********************************************************************
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module iuq_ram(
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pc_iu_ram_instr,
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pc_iu_ram_instr_ext,
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pc_iu_ram_issue,
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pc_iu_ram_active,
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iu_pc_ram_done,
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cp_flush,
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ib_rm_rdy,
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rm_ib_iu3_val,
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rm_ib_iu3_instr,
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vdd,
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gnd,
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nclk,
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pc_iu_sg_2,
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pc_iu_func_sl_thold_2,
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clkoff_b,
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act_dis,
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tc_ac_ccflush_dc,
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d_mode,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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scan_in,
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scan_out
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);
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`include "tri_a2o.vh"
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// parameter `EXPAND_TYPE = 2;
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// parameter `THREADS = 2; // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
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input [0:31] pc_iu_ram_instr;
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input [0:3] pc_iu_ram_instr_ext;
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input pc_iu_ram_issue;
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input [0:`THREADS-1] pc_iu_ram_active;
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input iu_pc_ram_done;
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input [0:`THREADS-1] cp_flush;
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input [0:`THREADS-1] ib_rm_rdy;
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output [0:`THREADS-1] rm_ib_iu3_val;
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output [0:35] rm_ib_iu3_instr;
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//pervasive
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inout vdd;
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inout gnd;
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(* pin_data="PIN_FUNCTION=/G_CLK/" *)
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input [0:`NCLK_WIDTH-1] nclk;
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input pc_iu_sg_2;
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input pc_iu_func_sl_thold_2;
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input clkoff_b;
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input act_dis;
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input tc_ac_ccflush_dc;
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input d_mode;
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input delay_lclkr;
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input mpw1_b;
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input mpw2_b;
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input scan_in;
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output scan_out;
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//--------------------------
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// components
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//--------------------------
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//--------------------------
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// constants
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//--------------------------
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//scan chain
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parameter cp_flush_offset = 0;
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parameter ram_val_offset = cp_flush_offset + `THREADS;
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parameter ram_act_offset = ram_val_offset + `THREADS;
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parameter ram_instr_offset = ram_act_offset + `THREADS;
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parameter ram_done_offset = ram_instr_offset + 36;
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parameter scan_right = ram_done_offset + 1 - 1;
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//--------------------------
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// signals
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//--------------------------
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wire tiup;
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wire ram_valid;
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wire [0:`THREADS-1] ram_val_d;
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wire [0:`THREADS-1] ram_val_q;
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wire [0:`THREADS-1] ram_act_d;
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wire [0:`THREADS-1] ram_act_q;
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wire [0:35] ram_instr_d;
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wire [0:35] ram_instr_q;
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wire ram_done_d;
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wire ram_done_q;
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wire [0:`THREADS-1] cp_flush_d;
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wire [0:`THREADS-1] cp_flush_q;
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wire pc_iu_func_sl_thold_1;
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wire pc_iu_func_sl_thold_0;
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wire pc_iu_func_sl_thold_0_b;
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wire pc_iu_sg_1;
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wire pc_iu_sg_0;
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wire force_t;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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assign tiup = 1'b1;
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//assign tidn = 1'b0;
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//-----------------------------------------------
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// logic
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//-----------------------------------------------
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assign cp_flush_d = cp_flush;
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assign ram_done_d = iu_pc_ram_done;
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generate
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begin : xhdl1
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genvar i;
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for (i = 0; i <= `THREADS - 1; i = i + 1)
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begin : issue_gating
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assign ram_val_d[i] = (pc_iu_ram_active[i] & pc_iu_ram_issue) | (ram_val_q[i] & (~ib_rm_rdy[i])) | (cp_flush_q[i] & ram_act_d[i]);
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assign ram_act_d[i] = (ram_done_q == 1'b1) ? 1'b0 :
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(ram_val_q[i] == 1'b1) ? 1'b1 :
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ram_act_q[i];
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end
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end
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endgenerate
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assign ram_valid = pc_iu_ram_issue;
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assign ram_instr_d = {pc_iu_ram_instr, pc_iu_ram_instr_ext};
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//-----------------------------------------------
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// outputs
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//-----------------------------------------------
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assign rm_ib_iu3_val = ram_val_q;
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assign rm_ib_iu3_instr = ram_instr_q;
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//-----------------------------------------------
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// latches
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//-----------------------------------------------
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tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]),
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.scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]),
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.din(cp_flush_d),
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.dout(cp_flush_q)
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);
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tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_val_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[ram_val_offset:ram_val_offset + `THREADS - 1]),
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.scout(sov[ram_val_offset:ram_val_offset + `THREADS - 1]),
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.din(ram_val_d),
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.dout(ram_val_q)
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);
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tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_act_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[ram_act_offset:ram_act_offset + `THREADS - 1]),
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.scout(sov[ram_act_offset:ram_act_offset + `THREADS - 1]),
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.din(ram_act_d),
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.dout(ram_act_q)
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);
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tri_rlmreg_p #(.WIDTH(36), .INIT(0)) ram_instr_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(ram_valid),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[ram_instr_offset:ram_instr_offset + 35]),
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.scout(sov[ram_instr_offset:ram_instr_offset + 35]),
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.din(ram_instr_d[0:35]),
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.dout(ram_instr_q[0:35])
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);
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tri_rlmlatch_p #(.INIT(0)) ram_done_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[ram_done_offset]),
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.scout(sov[ram_done_offset]),
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.din(ram_done_d),
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.dout(ram_done_q)
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);
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//-----------------------------------------------
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// pervasive
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//-----------------------------------------------
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tri_plat #(.WIDTH(2)) perv_2to1_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
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.q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
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);
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tri_plat #(.WIDTH(2)) perv_1to0_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
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.q({pc_iu_func_sl_thold_0,pc_iu_sg_0})
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);
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tri_lcbor perv_lcbor(
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.clkoff_b(clkoff_b),
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.thold(pc_iu_func_sl_thold_0),
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.sg(pc_iu_sg_0),
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.act_dis(act_dis),
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.force_t(force_t),
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.thold_b(pc_iu_func_sl_thold_0_b)
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);
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//-----------------------------------------------
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// scan
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//-----------------------------------------------
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assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]};
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assign scan_out = sov[scan_right];
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endmodule
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