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265 lines
9.3 KiB
Verilog
265 lines
9.3 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//********************************************************************
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//*
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//* TITLE: Instruction Unit Debug
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//*
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//* NAME: iuq_dbg.v
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//*
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//*********************************************************************
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`include "tri_a2o.vh"
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module iuq_dbg(
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inout vdd,
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inout gnd,
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(* pin_data ="PIN_FUNCTION=/G_CLK/" *)
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input [0:`NCLK_WIDTH-1] nclk,
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input thold_2, // Connect to slp if unit uses slp
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input pc_iu_sg_2,
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input clkoff_b,
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input act_dis,
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input tc_ac_ccflush_dc,
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input d_mode,
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input delay_lclkr,
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input mpw1_b,
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input mpw2_b,
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(* pin_data ="PIN_FUNCTION=/SCAN_IN/" *)
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input func_scan_in,
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(* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *)
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output func_scan_out,
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input [0:31] unit_dbg_data0,
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input [0:31] unit_dbg_data1,
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input [0:31] unit_dbg_data2,
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input [0:31] unit_dbg_data3,
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input [0:31] unit_dbg_data4,
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input [0:31] unit_dbg_data5,
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input [0:31] unit_dbg_data6,
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input [0:31] unit_dbg_data7,
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input [0:31] unit_dbg_data8,
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input [0:31] unit_dbg_data9,
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input [0:31] unit_dbg_data10,
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input [0:31] unit_dbg_data11,
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input [0:31] unit_dbg_data12,
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input [0:31] unit_dbg_data13,
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input [0:31] unit_dbg_data14,
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input [0:31] unit_dbg_data15,
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input pc_iu_trace_bus_enable,
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input [0:10] pc_iu_debug_mux_ctrls,
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input [0:31] debug_bus_in,
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output [0:31] debug_bus_out,
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input [0:3] coretrace_ctrls_in,
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output [0:3] coretrace_ctrls_out
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);
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localparam trace_bus_enable_offset = 0;
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localparam debug_mux_ctrls_offset = trace_bus_enable_offset + 1;
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localparam trace_data_out_offset = debug_mux_ctrls_offset + 11;
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localparam coretrace_ctrls_out_offset = trace_data_out_offset + 32;
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localparam scan_right = coretrace_ctrls_out_offset + 4 - 1;
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wire trace_bus_enable_d;
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wire trace_bus_enable_q;
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wire [0:10] debug_mux_ctrls_d;
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wire [0:10] debug_mux_ctrls_q;
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wire [0:31] trace_data_out_d;
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wire [0:31] trace_data_out_q;
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wire [0:3] coretrace_ctrls_out_d;
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wire [0:3] coretrace_ctrls_out_q;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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wire thold_1;
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wire thold_0;
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wire thold_0_b;
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wire pc_iu_sg_1;
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wire pc_iu_sg_0;
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wire force_t;
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wire tiup;
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//BEGIN
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assign tiup = 1'b1;
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tri_debug_mux16 dbg_mux0(
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//.vd(vdd),
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//.gd(gnd),
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.select_bits(debug_mux_ctrls_q),
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.trace_data_in(debug_bus_in),
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.dbg_group0(unit_dbg_data0),
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.dbg_group1(unit_dbg_data1),
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.dbg_group2(unit_dbg_data2),
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.dbg_group3(unit_dbg_data3),
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.dbg_group4(unit_dbg_data4),
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.dbg_group5(unit_dbg_data5),
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.dbg_group6(unit_dbg_data6),
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.dbg_group7(unit_dbg_data7),
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.dbg_group8(unit_dbg_data8),
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.dbg_group9(unit_dbg_data9),
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.dbg_group10(unit_dbg_data10),
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.dbg_group11(unit_dbg_data11),
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.dbg_group12(unit_dbg_data12),
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.dbg_group13(unit_dbg_data13),
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.dbg_group14(unit_dbg_data14),
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.dbg_group15(unit_dbg_data15),
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.trace_data_out(trace_data_out_d),
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.coretrace_ctrls_in(coretrace_ctrls_in),
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.coretrace_ctrls_out(coretrace_ctrls_out_d)
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);
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assign debug_bus_out = trace_data_out_q;
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assign coretrace_ctrls_out = coretrace_ctrls_out_q;
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//---------------------------------------------------------------------
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// Latches
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//---------------------------------------------------------------------
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assign trace_bus_enable_d = pc_iu_trace_bus_enable;
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assign debug_mux_ctrls_d = pc_iu_debug_mux_ctrls;
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tri_rlmlatch_p #(.INIT(0)) trace_bus_enable_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[trace_bus_enable_offset]),
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.scout(sov[trace_bus_enable_offset]),
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.din(trace_bus_enable_d),
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.dout(trace_bus_enable_q)
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);
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tri_rlmreg_p #(.WIDTH(11), .INIT(0)) debug_mux_ctrls_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(trace_bus_enable_q),
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.thold_b(thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[debug_mux_ctrls_offset:debug_mux_ctrls_offset + 10]),
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.scout(sov[debug_mux_ctrls_offset:debug_mux_ctrls_offset + 10]),
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.din(debug_mux_ctrls_d),
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.dout(debug_mux_ctrls_q)
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);
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tri_rlmreg_p #(.WIDTH(32), .INIT(0)) trace_data_out_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(trace_bus_enable_q),
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.thold_b(thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[trace_data_out_offset:trace_data_out_offset + 31]),
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.scout(sov[trace_data_out_offset:trace_data_out_offset + 31]),
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.din(trace_data_out_d),
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.dout(trace_data_out_q)
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);
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tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(trace_bus_enable_q),
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.thold_b(thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 3]),
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.scout(sov[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 3]),
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.din(coretrace_ctrls_out_d),
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.dout(coretrace_ctrls_out_q)
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);
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//---------------------------------------------------------------------
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// pervasive thold/sg latches
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//---------------------------------------------------------------------
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tri_plat #(.WIDTH(2)) perv_2to1_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({thold_2, pc_iu_sg_2}),
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.q( {thold_1, pc_iu_sg_1})
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);
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tri_plat #(.WIDTH(2)) perv_1to0_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({thold_1, pc_iu_sg_1}),
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.q( {thold_0, pc_iu_sg_0})
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);
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tri_lcbor perv_lcbor(
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.clkoff_b(clkoff_b),
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.thold(thold_0),
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.sg(pc_iu_sg_0),
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.act_dis(act_dis),
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.force_t(force_t),
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.thold_b(thold_0_b)
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);
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//---------------------------------------------------------------------
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// Scan
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//---------------------------------------------------------------------
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assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
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assign func_scan_out = sov[0];
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endmodule
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