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427 lines
18 KiB
Verilog
427 lines
18 KiB
Verilog
// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// A2L2 bridge
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// single req (shared L/S credit)
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// interface to a sim mem[]
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`include "tri_a2o.vh"
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`timescale 1ns/1ps
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module a2l2wb #(
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parameter MEM_MODE = 0, // 0:ext 1:int 2:wb
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parameter MEM_QW = 16384
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)
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(
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input clk,
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input rst,
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input ac_an_req_pwr_token,
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input ac_an_req,
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input [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra,
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input [0:5] ac_an_req_ttype,
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input [0:2] ac_an_req_thread,
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input [0:4] ac_an_req_ld_core_tag,
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input [0:2] ac_an_req_ld_xfr_len,
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input ac_an_req_wimg_w,
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input ac_an_req_wimg_i,
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input ac_an_req_wimg_m,
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input ac_an_req_wimg_g,
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input ac_an_req_endian,
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input [0:3] ac_an_req_user_defined,
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input [0:3] ac_an_req_spare_ctrl_a0,
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input ac_an_st_data_pwr_token,
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input [0:31] ac_an_st_byte_enbl,
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input [0:255] ac_an_st_data,
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output an_ac_reld_data_vld,
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output [0:4] an_ac_reld_core_tag,
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output [0:127] an_ac_reld_data,
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output [58:59] an_ac_reld_qw,
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output an_ac_reld_ecc_err,
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output an_ac_reld_ecc_err_ue,
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output an_ac_reld_data_coming,
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output an_ac_reld_ditc,
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output an_ac_reld_crit_qw,
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output an_ac_reld_l1_dump,
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output [0:3] an_ac_req_spare_ctrl_a1,
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output [0:`THREADS-1] an_ac_sync_ack,
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output an_ac_req_ld_pop,
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output an_ac_req_st_pop,
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output an_ac_req_st_gather,
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output [0:`THREADS-1] an_ac_stcx_complete,
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output [0:`THREADS-1] an_ac_stcx_pass,
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output [0:`THREADS-1] an_ac_reservation_vld,
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output an_ac_icbi_ack,
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output [0:1] an_ac_icbi_ack_thread,
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output an_ac_back_inv,
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output [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr,
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output [0:4] an_ac_back_inv_target,
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output an_ac_back_inv_local,
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output an_ac_back_inv_lbit,
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output an_ac_back_inv_gs,
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output an_ac_back_inv_ind,
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output [0:7] an_ac_back_inv_lpar_id,
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input ac_an_back_inv_reject,
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input [0:7] ac_an_lpar_id,
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output an_ac_checkstop,
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// direct-attach mem
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output [0:31] mem_adr,
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input [0:127] mem_dat,
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output mem_wr_val,
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output [0:15] mem_wr_be,
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output [0:127] mem_wr_dat,
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// wishbone
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output wb_stb,
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output wb_cyc,
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output [31:0] wb_adr,
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output wb_we,
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output [3:0] wb_sel,
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output [31:0] wb_datw,
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input wb_ack,
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input [31:0] wb_datr
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);
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// unsupported right now
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assign an_ac_sync_ack = 0;
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assign an_ac_stcx_complete = 0;
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assign an_ac_stcx_pass = 0;
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assign an_ac_reservation_vld = 0;
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assign an_ac_icbi_ack = 0;
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assign an_ac_icbi_ack_thread = 0;
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assign an_ac_back_inv = 0;
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assign an_ac_back_inv_addr = 0;
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assign an_ac_back_inv_target = 0;
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assign an_ac_back_inv_local = 0;
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assign an_ac_back_inv_lbit = 0;
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assign an_ac_back_inv_gs = 0;
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assign an_ac_back_inv_ind = 0;
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assign an_ac_back_inv_lpar_id = 0;
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assign an_ac_req_st_gather = 0;
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assign an_ac_req_spare_ctrl_a1 = 0;
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assign an_ac_reld_l1_dump = 0;
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wire [0:4] cmdseq_d;
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reg [0:4] cmdseq_q;
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wire [0:30+`REAL_IFAR_WIDTH] req_d;
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reg [0:30+`REAL_IFAR_WIDTH] req_q;
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wire [0:31+256] std_d;
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reg [0:31+256] std_q;
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reg req_tkn_q;
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reg std_tkn_q;
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wire [0:255] rld_d;
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reg [0:255] rld_q;
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wire [0:1] qw_d;
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reg [0:1] qw_q;
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wire [0:1] mem_qw_d;
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reg [0:1] mem_qw_q;
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wire [0:7] err_d;
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reg [0:7] err_q;
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wire new_req;
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wire ld_req_val;
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wire st_req_val;
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wire req_ieq1;
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wire req_le;
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wire [64-`REAL_IFAR_WIDTH:63] req_adr;
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wire [0:4] req_tag;
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wire [0:2] req_len;
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wire rld_coming;
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wire rld_valid;
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wire rld_done;
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wire [0:1] rld_qw;
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wire idle;
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wire ld_ready;
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wire st_ready;
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generate if (MEM_MODE == 1)
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reg [0:127] mem[MEM_QW];
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endgenerate
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// FF
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always @(posedge clk) begin
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if (rst) begin
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cmdseq_q = 'b11111;
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req_q = 0;
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std_q = 0;
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req_tkn_q = 0;
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std_tkn_q = 0;
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qw_q = 0;
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mem_qw_q = 0;
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err_q = 0;
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end else begin
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cmdseq_q = cmdseq_d;
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req_q = req_d;
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std_q = std_d;
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req_tkn_q = ac_an_req_pwr_token;
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std_tkn_q = ac_an_st_data_pwr_token;
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qw_q = qw_d;
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mem_qw_q = mem_qw_d;
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err_q = err_d;
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end
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end
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// adr needs to be created for cacheable!
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// ext/int mem
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// mem_adr --- (qw-aligned byte address)
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// mem_dat ---
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// external memory
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generate if (MEM_MODE == 0)
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assign mem_adr = req_st_val ? {req_adr[64-`REAL_IFAR_WIDTH:59], 4'b0000} :
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req_ieq1 ? req_adr :
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{req_adr[64-`REAL_IFAR_WIDTH:57], mem_qw_q, 4'b0000};
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endgenerate
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// internal memory
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generate if (MEM_MODE == 1) begin
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always @(posedge clk) begin
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if (mem_wr_val) begin
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mem[req_adr] = mem_wr_data;
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end
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end
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assign mem_dat = mem[req_adr];
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end
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endgenerate
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// clkgate
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// oflow if req_q[0]==1!
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assign new_req = req_tkn_q & ac_an_req;
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assign req_d = new_req ?
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{1'b1, // 0
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ac_an_req_thread, // 1:3
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ac_an_req_ttype, // 4:9
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ac_an_req_ld_core_tag, // 10:14
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ac_an_req_ra, // 15:56
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ac_an_req_ld_xfr_len, // 57:59
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ac_an_req_wimg_w, // 60
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ac_an_req_wimg_i, // 61
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ac_an_req_wimg_m, // 62
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ac_an_req_wimg_g, // 63
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ac_an_req_endian, // 64
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ac_an_req_user_defined, // 65:68
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ac_an_req_spare_ctrl_a0 // 69:72
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} :
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(rld_done | do_store) ? 0 : req_q;
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assign std_d = std_tkn_q ? {ac_an_st_byte_enbl, // 0:31
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ac_an_st_data // 32:287
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} : do_store ? 0 : std_q;
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// request
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assign req_ld_val = req_q[0] & (
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(req_q[4:9] == 6'b000000) | // if
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(req_q[4:9] == 6'b001000) | // ld
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(req_q[4:9] == 6'b100010) | // ditc
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(req_q[4:9] == 6'b001001) | // larx
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(req_q[4:9] == 6'b001011) // larx hint
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);
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assign req_ieq1 = req_q[61];
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assign req_le = req_q[64];
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assign req_st_val = req_q[0] & (
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(req_q[4:9] == 6'b100000) | // st
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(req_q[4:9] == 6'b101001) // stcx
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);
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assign req_tag = req_q[10:14];
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assign req_adr = req_q[15:15+`REAL_IFAR_WIDTH-1];
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assign req_len = req_q[57:59];
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// random delay, or future functional stuff
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assign ld_ready = 1;
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assign st_ready = 1;
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// b2b
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// coming --- ---
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// valid --- --- --- --- (and qualifiers)
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// data --- --- --- --- (only 1 beat for ieq1)
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// vtable -V -b 0 a2l2wb.v
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//tbl cmdseq
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//n cmdseq_q cmdseq_d
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//n | | rld_coming
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//n | req_ld_val | |rld_valid
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//n | |req_st_val | ||do_store
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//n | ||ld_ready | |||rld_done
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//n | |||st_ready | ||||inc_qw
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//n | ||||req_ieq1 | ||||| idle
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//n | ||||| | ||||| |
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//n | ||||| | ||||| |
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//b 01234 ||||| 01234 ||||| |
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//t iiiii iiiii ooooo ooooo o
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//*----------------------------------------------------------------------
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//* Idle ****************************************************************
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//s 11111 ----- ----- 00000 1
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//s 11111 00--- 11111 00000 - * ...zzz...
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//s 11111 1---- 00001 00000 -
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//s 11111 -1--- 10000 00000 -
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//* Load ****************************************************************
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//s 00001 --0-- 00001 00000 0
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//s 00001 --1-- 00010 10000 0
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//* Reload V0 *********************************************************** * val 0
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//s 00010 ----- 00011 01001 0
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//* Reload Nop *********************************************************** * val 1 (not ieq1)
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//s 00011 ----1 00100 00000 0
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//s 00011 ----0 01000 11001 0
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//* Reload D0 (I=1) ****************************************************** * dat 0 (ieq1)
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//s 00100 ----- 11111 00010 0
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//* Reload D0 ************************************************************ * val 2, dat 0
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//s 01000 ----- 01001 01001 0
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//* Reload D1 ************************************************************ * val 3, dat 1
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//s 01001 ----- 01010 01001 0
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//* Reload D2 ************************************************************ * dat 2
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//s 01010 ----- 01011 00000 0
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//* Reload D3 ************************************************************ * dat 3
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//s 01011 ----- 11111 00010 0
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//* Store ***************************************************************
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//s 10000 ---0- 10000 00000 0
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//s 10000 ---1- 11111 00100 0
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//*----------------------------------------------------------------------
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//tbl cmdseq
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// crit first uses qw pattern instead of +1
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// valid (d-2)
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assign qw_d = new_req ? 0 :
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inc_qw ? qw_q + 1 :
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qw_q;
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assign rld_qw = req_ieq1 ? 2'b00 : qw_q;
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// mem address (d-1)
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assign mem_qw_d = rld_qw;
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// response
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assign an_ac_reld_ecc_err = 0;
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assign an_ac_reld_ecc_err_ue = 0;
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assign an_ac_reld_ditc = 0;
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// loads
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assign an_ac_reld_data_coming = rld_coming;
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assign an_ac_reld_data_vld = rld_valid;
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assign an_ac_reld_core_tag = req_tag;
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assign an_ac_reld_qw = rld_qw;
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assign an_ac_reld_crit_qw = req_ieq1 | (req_adr[58:59] == rld_qw);
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assign an_ac_reld_data = mem_dat;
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assign an_ac_req_ld_pop = rld_done;
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// stores
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assign an_ac_req_st_pop = do_store;
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// BE, 16B max store
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assign mem_wr_val = do_store;
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assign mem_wr_be = std_q[0:15];
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assign mem_wr_dat = std_q[32:32+127];
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// misc
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assign err_d = {(new_req & ~idle), 7'b0};
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assign an_ac_checkstop = err_q != 0;
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//vtable cmdseq
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assign cmdseq_d[0] =
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) +
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_st_val) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) +
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & ~st_ready) +
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
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assign cmdseq_d[1] =
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) +
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
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assign cmdseq_d[2] =
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_ieq1) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) +
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
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assign cmdseq_d[3] =
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ld_ready) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) +
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
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assign cmdseq_d[4] =
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) +
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_ld_val) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ~ld_ready) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) +
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
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assign rld_coming =
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ld_ready) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1);
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assign rld_valid =
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]);
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assign do_store =
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(cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
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assign rld_done =
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(~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]);
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assign inc_qw =
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) +
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(~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]);
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assign idle =
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(cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]);
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//vtable cmdseq
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endmodule
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