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333 lines
11 KiB
Python
333 lines
11 KiB
Python
# A2O Core
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import cocotb
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from cocotb.triggers import Timer, RisingEdge
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from cocotb.binary import BinaryValue
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from cocotb.handle import Force
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from cocotb.handle import Release
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from cocotb.result import TestSuccess
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from dotmap import DotMap
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import itertools
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from OPEnv import *
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# ------------------------------------------------------------------------------------------------
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# Tasks
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async def A2OConfig(dut, sim):
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"""Configure A2O. """
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# A2L2 load/store credits
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creditsLd = sim.a2o.root.lq0.lsq.arb.load_cred_cnt_d # 8 max
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creditsLdMax = sim.a2o.root.lq0.lsq.arb.ld_cred_max # hdw check
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creditsSt = sim.a2o.root.lq0.lsq.arb.store_cred_cnt_d # 32 max
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creditsStMax = sim.a2o.root.lq0.lsq.arb.st_cred_max # hdw check
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creditsLdStSingle = sim.a2o.root.lq0.lsq.arb.spr_xucr0_cred_d # 1 total credit
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#wtf this affects A2L2 - default=1
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# sim.a2o.root.lq0.lsq.arb.spr_lsucr0_b2b_q # 0=crit first, every other 1=crit first, b2b **the a2l2 spec does not say crit must be first**
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lsucr0_d = sim.a2o.root.lq0.ctl.spr.lq_spr_cspr.lsucr0_d
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lsucr0_q = sim.a2o.root.lq0.ctl.spr.lq_spr_cspr.lsucr0_q
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cpcr2_d = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr2_d
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cpcr2_q = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr2_l2
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cpcr2_act = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr2_wren
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cpcr4_d = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_d
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cpcr4_q = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_l2
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cpcr4_act = sim.a2o.root.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_wren
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await RisingEdge(dut.clk_1x)
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if sim.a2o.config.creditsLd is not None:
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creditsLd.value = Force(sim.a2o.config.creditsLd)
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creditsLdMax.value = Force(sim.a2o.config.creditsLd)
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sim.msg(f'A2O: load credits changed from {creditsLd.value.integer} to {sim.a2o.config.creditsLd}.')
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await RisingEdge(dut.clk_1x)
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creditsLd.value = Release()
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if sim.a2o.config.creditsSt is not None:
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creditsSt.value = Force(sim.a2o.config.creditsSt)
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creditsStMax.value = Force(sim.a2o.config.creditsSt)
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sim.msg(f'A2O: store credits changed from {creditsSt.value.integer} to {sim.a2o.config.creditsSt}.')
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await RisingEdge(dut.clk_1x)
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creditsSt.value = Release()
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if sim.a2o.config.creditsLdStSingle is not None:
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v = 1 if sim.a2o.config.creditsLdStSingle else 0
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creditsLdStSingle.value = Force(v)
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sim.msg(f'A2O: only one load OR store allowed when credits=1/1.')
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await RisingEdge(dut.clk_1x)
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#creditsLdStSingle.value = Release() # to release have to set _q with xucr0_d[51] and xucr0_act
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#wtf make a function - needs mask,thread
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if sim.a2o.config.lsDataForward is not None:
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v = 1 if sim.a2o.config.lsDataForward else 0
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sim.msg(f'A2O: LSUCR0 = {hex(lsucr0_q.value), 8}')
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sim.msg(f'A2O: Setting LSUCR0[DFWD] = {v}.')
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v = v << 2
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v = (lsucr0_q.value.integer & ~0x4) | v
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lsucr0_d.value = Force(v)
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await RisingEdge(dut.clk_1x)
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lsucr0_d.value = Release()
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sim.msg(f'A2O: LSUCR0 = {hex(lsucr0_q.value), 8}')
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if sim.a2o.config.cpcr4_sq_cnt is not None:
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v = sim.a2o.config.cpcr4_sq_cnt
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sim.msg(f'A2O: CPCR4 = {hex(cpcr4_q[0], 8)}')
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sim.msg(f'A2O: Setting CPCR4[SQ_CNT] = {v}.')
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v = v << 0
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v = (cpcr4_q[0].value.integer & ~0x1F) | v
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await RisingEdge(dut.clk_1x) # need cuz of act?
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cpcr4_d[0].value = Force(v)
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cpcr4_act.value = Force(1)
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await RisingEdge(dut.clk_1x)
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await RisingEdge(dut.clk_1x) # need cuz of act?
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cpcr4_d[0].value = Release()
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cpcr4_act.value = Release()
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sim.msg(f'A2O: CPCR4 = {hex(cpcr4_q[0], 8)}')
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await RisingEdge(dut.clk_1x)
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async def A2ODriver(dut, sim):
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"""A2O Core Driver"""
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transTypes = {
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'00': 'IFETCH',
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'08': 'LOAD',
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'20': 'STORE'
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}
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ok = True
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readPending = []
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countReads = 0
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mem = {}
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sim.msg('A2O Driver: nothing to do.')
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#while ok and not sim.done:
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# await RisingEdge(dut.clk_1x)
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# A2O Checker
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# check protocol, etc.
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async def A2OChecker(dut, sim):
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"""A2O Core Checker """
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me = 'A2O Checker'
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ok = True
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sim.msg(f'{me}: started.')
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# errors
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creditsLdErr = sim.a2o.root.lq0.lsq.arb.ld_cred_err_q
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creditsStErr = sim.a2o.root.lq0.lsq.arb.st_cred_err_q
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errors = [
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{'name': 'Load Credits', 'sig': creditsLdErr},
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{'name': 'Store Credits', 'sig': creditsStErr},
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]
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while ok:
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await RisingEdge(dut.clk_1x)
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if not sim.resetDone:
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continue
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for i in range(len(errors)):
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assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}'
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# A2O Monitor
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# count transactions, etc.
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# fail on bad addresses
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async def A2OMonitor(dut, sim):
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"""A2O Core Monitor"""
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me = 'A2O Monitor'
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ok = True
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sim.msg(f'{me}: started.')
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# completions
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iu0Comp = sim.a2o.root.iu_lq_i0_completed
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iu0CompIFAR = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar
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iu1Comp = sim.a2o.root.iu_lq_i1_completed
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iu1CompIFAR = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar
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iuCompFlushIFAR = sim.a2o.root.cp_t0_flush_ifar
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cp3NIA = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q # nia after last cycle's completions
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# GPR ppol and arch map
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gprCompMap = []
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lastGprCompMap = []
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#wtf check what 33:36 are!
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for i in range(36):
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gprCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastGprCompMap.append(i)
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gpr = []
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for i in range(144):
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gpr.append(sim.a2o.root.xu0.gpr.gpr0.loc[i].dat)
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# CR fields pool and arch map
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crCompMap = []
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lastCrCompMap = []
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for i in range(8):
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crCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.cr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastCrCompMap.append(i)
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cr = []
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for i in range(24):
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cr.append(sim.a2o.root.xu0.cr.entry[i].reg_latch.dout)
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# XER pool and arch map
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xerCompMap = []
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lastXerCompMap = []
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for i in range(1):
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xerCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastXerCompMap.append(i)
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xer = []
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for i in range(12):
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xer.append(sim.a2o.root.xu0.xer.entry[i].reg_latch.dout)
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# CTR pool and arch map
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ctrCompMap = []
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lastCtrCompMap = []
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for i in range(1):
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ctrCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastCtrCompMap.append(i)
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ctr = []
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for i in range(8):
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ctr.append(sim.a2o.root.xu0.ctr.entry[i].reg_latch.dout)
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# LR pool and arch map
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lrCompMap = []
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lastLrCompMap = []
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for i in range(1):
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lrCompMap.append(sim.a2o.root.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.lr_rn_map.xhdl3.comp_map0[i].comp_map_latch.dout)
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lastLrCompMap.append(i)
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lr = []
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for i in range(8):
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lr.append(sim.a2o.root.xu0.lr.entry[i].reg_latch.dout)
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lastComp = ''
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lastCompCount = 0
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lastStack = ''
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lastPrintf = ''
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while ok:
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await RisingEdge(dut.clk_1x)
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if not sim.resetDone:
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continue
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# allow registered callbacks to be called here
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stack = sim.mem.dump(0x1FD00, 0x1FFFF, cols=8, trimLeadingZeros=True, trimTrailingZeros=True)
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if stack != lastStack:
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sim.msg('Stack:\n' + stack)
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lastStack = stack
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printf = sim.mem.dump(0x1C000, 0x1C1FF, cols=8, trimLeadingZeros=True, trimTrailingZeros=True)
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if printf != lastPrintf:
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sim.msg('Print buffer:\n' + printf)
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lastPrintf = printf
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comp = ''
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#wtf seeing something weird here
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# there are cases where x's are in some bits of comp ifar's; maybe ok (predict array?) but why is completed indicated?
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if iu0Comp.value == 1:
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comp = f'0:{sim.safeint(iu0CompIFAR.value.binstr + "00", 2):06X} '
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if iu1Comp.value == 1:
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comp = f'{comp}1:{sim.safeint(iu1CompIFAR.value.binstr + "00", 2):06X} '
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if comp != '':
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comp = f'{comp}{sim.safeint(iuCompFlushIFAR.value.binstr + "00", 2):016X}'
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sim.msg(f'C0: CP {comp}')
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if sim.a2o.iarPass is not None:
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if sim.safeint(iu0CompIFAR.value.binstr + "00", 2) == sim.a2o.iarPass:
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sim.msg(f'Passing IAR detected: {sim.a2o.iarPass:08X}')
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raise TestSuccess('Test passed.')
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if sim.a2o.iarPass is not None:
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if sim.safeint(iu0CompIFAR.value.binstr + "00", 2) == sim.a2o.iarPass:
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sim.ok = False
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sim.fail = 'Failing IAR detected'
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assert False, sim.fail
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break
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if sim.a2o.stopOnLoop is not None and sim.a2o.stopOnLoop > 0:
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if comp == lastComp:
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lastCompCount += 1
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if lastCompCount == sim.a2o.stopOnLoop:
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sim.ok = False
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sim.fail = 'Code hang detected'
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assert False, sim.fail
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break
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else:
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lastCompCount = 0
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lastComp = comp
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if sim.a2o.traceFacUpdates:
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# renamables
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for i in range(36):
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good, arch = sim.safeint(gprCompMap[i].value.binstr, 2, rc=True)
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if good and arch != lastGprCompMap[i]:
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sim.msg(f'GPR Update: R{i:02d}={hex(gpr[arch], 16)}')
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lastGprCompMap[i] = arch
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for i in range(8):
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good, arch = sim.safeint(crCompMap[i].value.binstr, 2, rc=True)
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if good and arch != lastCrCompMap[i]:
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sim.msg(f'CR Update: F{i:01d}={hex(cr[arch], 1)}')
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lastCrCompMap[i] = arch
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for i in range(1):
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good, arch = sim.safeint(xerCompMap[i].value.binstr, 2, rc=True)
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if good and arch != lastXerCompMap[i]:
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v = xer[arch].value.binstr
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sim.msg(f'XER Update: SO/OV/CA={v[0:3]} LEN={int(v[3:],2):02X}')
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lastXerCompMap[i] = arch
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for i in range(1):
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good, arch = sim.safeint(ctrCompMap[i].value.binstr, 2, rc=True)
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if good and arch != lastCtrCompMap[i]:
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sim.msg(f'CTR Update:{hex(ctr[arch], 16)}')
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lastCtrCompMap[i] = arch
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for i in range(1):
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good, arch = sim.safeint(lrCompMap[i].value.binstr, 2, rc=True)
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if good and arch != lastLrCompMap[i]:
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sim.msg(f'LR Update:{hex(lr[arch], 16)}')
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lastLrCompMap[i] = arch
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sim.msg(f'{me}: ended.')
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# ------------------------------------------------------------------------------------------------
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# Classes
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class A2O:
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config = A2OConfig
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driver = A2ODriver
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checker = A2OChecker
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monitor = A2OMonitor
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def __init__(self, sim):
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pass
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class A2OCore(DotMap):
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def __init__(self, sim, root=None):
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super().__init__()
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self.sim = sim
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if root is None:
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self.root = sim.dut.c0
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else:
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self.root = root
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self.traceFacUpdates = False
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self.stopOnLoop = 0
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self.iarPass = None
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self.iarFail = None
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self.config = DotMap({
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'creditsLd': None,
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'creditsSt': None,
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'creditsLdStSingle': None,
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'lsDataForward' : None,
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'cpcr4_sq_cnt' : None
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})
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