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321 lines
16 KiB
Verilog
321 lines
16 KiB
Verilog
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`include "tri_a2o.vh"
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`timescale 1ns/1ps
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// might add some sim-only lines to enable clks, etc.
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module cocotb_icarus (
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input[0:`NCLK_WIDTH-1] nclk,
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input scan_in,
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output scan_out,
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// Pervasive clock control
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input an_ac_rtim_sl_thold_8,
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input an_ac_func_sl_thold_8,
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input an_ac_func_nsl_thold_8,
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input an_ac_ary_nsl_thold_8,
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input an_ac_sg_8,
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input an_ac_fce_8,
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input [0:7] an_ac_abst_scan_in,
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// L2 LARX/STCX
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input [0:`THREADS-1] an_ac_reservation_vld,
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input [0:`THREADS-1] an_ac_stcx_complete,
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input [0:`THREADS-1] an_ac_stcx_pass,
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// ICBI ACK Interface
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input an_ac_icbi_ack,
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input [0:1] an_ac_icbi_ack_thread,
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// Back invalidate interface
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input an_ac_back_inv,
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input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr,
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input [0:4] an_ac_back_inv_target, // connect to bit(0)
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input an_ac_back_inv_local,
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input an_ac_back_inv_lbit,
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input an_ac_back_inv_gs,
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input an_ac_back_inv_ind,
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input [0:7] an_ac_back_inv_lpar_id,
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output ac_an_back_inv_reject,
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output [0:7] ac_an_lpar_id,
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// L2 Reload Inputs
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input an_ac_reld_data_vld, // reload data is coming next cycle
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input [0:4] an_ac_reld_core_tag, // reload data destinatoin tag (which load queue)
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input [0:127] an_ac_reld_data, // Reload Data
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input [58:59] an_ac_reld_qw, // quadword address of reload data beat
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input an_ac_reld_ecc_err, // Reload Data contains a Correctable ECC error
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input an_ac_reld_ecc_err_ue, // Reload Data contains an Uncorrectable ECC error
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input an_ac_reld_data_coming,
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input an_ac_reld_ditc,
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input an_ac_reld_crit_qw,
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input an_ac_reld_l1_dump,
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input [0:3] an_ac_req_spare_ctrl_a1, // spare control bits from L2
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// load/store credit control
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input an_ac_flh2l2_gate, // Gate L1 Hit forwarding SPR config bit
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input an_ac_req_ld_pop, // credit for a load (L2 can take a load command)
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input an_ac_req_st_pop, // credit for a store (L2 can take a store command)
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input an_ac_req_st_gather, // credit for a store due to L2 gathering of store commands
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input [0:`THREADS-1] an_ac_sync_ack,
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//SCOM Satellite
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input [0:3] an_ac_scom_sat_id,
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input an_ac_scom_dch,
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input an_ac_scom_cch,
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output ac_an_scom_dch,
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output ac_an_scom_cch,
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// FIR and Error Signals
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output [0:`THREADS-1] ac_an_special_attn,
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output [0:2] ac_an_checkstop,
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output [0:2] ac_an_local_checkstop,
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output [0:2] ac_an_recov_err,
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output ac_an_trace_error,
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output ac_an_livelock_active,
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input an_ac_checkstop,
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input [0:`THREADS-1] an_ac_external_mchk,
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// Perfmon Event Bus
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output [0:4*`THREADS-1] ac_an_event_bus0,
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output [0:4*`THREADS-1] ac_an_event_bus1,
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// Reset related
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input an_ac_reset_1_complete,
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input an_ac_reset_2_complete,
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input an_ac_reset_3_complete,
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input an_ac_reset_wd_complete,
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// Power Management
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output [0:`THREADS-1] ac_an_pm_thread_running,
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input [0:`THREADS-1] an_ac_pm_thread_stop,
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input [0:`THREADS-1] an_ac_pm_fetch_halt,
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output ac_an_power_managed,
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output ac_an_rvwinkle_mode,
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// Clock, Test, and LCB Controls
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input an_ac_gsd_test_enable_dc,
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input an_ac_gsd_test_acmode_dc,
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input an_ac_ccflush_dc,
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input an_ac_ccenable_dc,
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input an_ac_lbist_en_dc,
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input an_ac_lbist_ip_dc,
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input an_ac_lbist_ac_mode_dc,
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input an_ac_scan_diag_dc,
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input an_ac_scan_dis_dc_b,
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//Thold input to clock control macro
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input [0:8] an_ac_scan_type_dc,
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// Pervasive
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output ac_an_reset_1_request,
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output ac_an_reset_2_request,
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output ac_an_reset_3_request,
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output ac_an_reset_wd_request,
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input an_ac_lbist_ary_wrt_thru_dc,
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input [0:`THREADS-1] an_ac_sleep_en,
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input [0:`THREADS-1] an_ac_ext_interrupt,
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input [0:`THREADS-1] an_ac_crit_interrupt,
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input [0:`THREADS-1] an_ac_perf_interrupt,
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input [0:`THREADS-1] an_ac_hang_pulse,
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input an_ac_tb_update_enable,
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input an_ac_tb_update_pulse,
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input [0:3] an_ac_chipid_dc,
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input [0:7] an_ac_coreid,
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output [0:`THREADS-1] ac_an_machine_check,
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input an_ac_debug_stop,
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output [0:`THREADS-1] ac_an_debug_trigger,
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input [0:`THREADS-1] an_ac_uncond_dbg_event,
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output [0:31] ac_an_debug_bus,
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output ac_an_coretrace_first_valid, // coretrace_ctrls[0]
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output ac_an_coretrace_valid, // coretrace_ctrls[1]
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output [0:1] ac_an_coretrace_type, // coretrace_ctrls[2:3]
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// L2 Outputs
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output ac_an_req_pwr_token, // power token for command coming next cycle
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output ac_an_req, // command request valid
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output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra, // real address for request
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output [0:5] ac_an_req_ttype, // command (transaction) type
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output [0:2] ac_an_req_thread, // encoded thread ID
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output ac_an_req_wimg_w, // write-through
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output ac_an_req_wimg_i, // cache-inhibited
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output ac_an_req_wimg_m, // memory coherence required
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output ac_an_req_wimg_g, // guarded memory
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output [0:3] ac_an_req_user_defined, // User Defined Bits
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output [0:3] ac_an_req_spare_ctrl_a0, // Spare bits
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output [0:4] ac_an_req_ld_core_tag, // load command tag (which load Q)
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output [0:2] ac_an_req_ld_xfr_len, // transfer length for non-cacheable load
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output [0:31] ac_an_st_byte_enbl, // byte enables for store data
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output [0:255] ac_an_st_data, // store data
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output ac_an_req_endian, // endian mode (0=big endian, 1=little endian)
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output ac_an_st_data_pwr_token // store data power token
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);
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c c0(
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// generic map (
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// EXPAND_TYPE => EXPAND_TYPE
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// );
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.nclk(nclk),
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.scan_in(scan_in),
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.scan_out(scan_out),
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// Pervasive clock control
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.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
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.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
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.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
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.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
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.an_ac_sg_8(an_ac_sg_8),
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.an_ac_fce_8(an_ac_fce_8),
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.an_ac_abst_scan_in(an_ac_abst_scan_in),
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// L2 STCX complete
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.an_ac_stcx_complete(an_ac_stcx_complete),
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.an_ac_stcx_pass(an_ac_stcx_pass),
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// ICBI ACK Interface
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.an_ac_icbi_ack(an_ac_icbi_ack),
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.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
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// Back invalidate interface
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.an_ac_back_inv(an_ac_back_inv),
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.an_ac_back_inv_addr(an_ac_back_inv_addr),
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.an_ac_back_inv_target(an_ac_back_inv_target),
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.an_ac_back_inv_local(an_ac_back_inv_local),
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.an_ac_back_inv_lbit(an_ac_back_inv_lbit),
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.an_ac_back_inv_gs(an_ac_back_inv_gs),
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.an_ac_back_inv_ind(an_ac_back_inv_ind),
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.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
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.ac_an_back_inv_reject(ac_an_back_inv_reject),
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.ac_an_lpar_id(ac_an_lpar_id),
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// L2 Reload Inputs
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.an_ac_reld_data_vld(an_ac_reld_data_vld),
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.an_ac_reld_core_tag(an_ac_reld_core_tag),
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.an_ac_reld_data(an_ac_reld_data),
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.an_ac_reld_qw(an_ac_reld_qw),
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.an_ac_reld_ecc_err(an_ac_reld_ecc_err),
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.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
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.an_ac_reld_data_coming(an_ac_reld_data_coming),
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.an_ac_reld_ditc(an_ac_reld_ditc),
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.an_ac_reld_crit_qw(an_ac_reld_crit_qw),
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.an_ac_reld_l1_dump(an_ac_reld_l1_dump),
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.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
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// load/store credit control
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.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
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.an_ac_req_ld_pop(an_ac_req_ld_pop),
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.an_ac_req_st_pop(an_ac_req_st_pop),
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.an_ac_req_st_gather(an_ac_req_st_gather),
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.an_ac_sync_ack(an_ac_sync_ack),
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.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
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//SCOM Satellite
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.an_ac_scom_sat_id(an_ac_scom_sat_id),
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.an_ac_scom_dch(an_ac_scom_dch),
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.an_ac_scom_cch(an_ac_scom_cch),
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.ac_an_scom_dch(ac_an_scom_dch),
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.ac_an_scom_cch(ac_an_scom_cch),
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// FIR and Error Signals
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.ac_an_special_attn(ac_an_special_attn),
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.ac_an_checkstop(ac_an_checkstop),
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.ac_an_local_checkstop(ac_an_local_checkstop),
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.ac_an_recov_err(ac_an_recov_err),
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.ac_an_trace_error(ac_an_trace_error),
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.ac_an_livelock_active(ac_an_livelock_active),
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.an_ac_checkstop(an_ac_checkstop),
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.an_ac_external_mchk(an_ac_external_mchk),
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// Perfmon Event Bus
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.ac_an_event_bus0(ac_an_event_bus0),
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.ac_an_event_bus1(ac_an_event_bus1),
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// Reset related
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.an_ac_reset_1_complete(an_ac_reset_1_complete),
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.an_ac_reset_2_complete(an_ac_reset_2_complete),
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.an_ac_reset_3_complete(an_ac_reset_3_complete),
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.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
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// Power Management
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.ac_an_pm_thread_running(ac_an_pm_thread_running),
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.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
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.ac_an_power_managed(ac_an_power_managed),
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.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
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// Clock, Test, and LCB Controls
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.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
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.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
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.an_ac_ccflush_dc(an_ac_ccflush_dc),
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.an_ac_ccenable_dc(an_ac_ccenable_dc),
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.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
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.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
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.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
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.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
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.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
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//Thold input to clock control macro
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.an_ac_scan_type_dc(an_ac_scan_type_dc),
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// Pervasive
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.ac_an_reset_1_request(ac_an_reset_1_request),
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.ac_an_reset_2_request(ac_an_reset_2_request),
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.ac_an_reset_3_request(ac_an_reset_3_request),
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.ac_an_reset_wd_request(ac_an_reset_wd_request),
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.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
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.an_ac_reservation_vld(an_ac_reservation_vld),
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.an_ac_sleep_en(an_ac_sleep_en),
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.an_ac_ext_interrupt(an_ac_ext_interrupt),
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.an_ac_crit_interrupt(an_ac_crit_interrupt),
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.an_ac_perf_interrupt(an_ac_perf_interrupt),
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.an_ac_hang_pulse(an_ac_hang_pulse),
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.an_ac_tb_update_enable(an_ac_tb_update_enable),
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.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
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.an_ac_chipid_dc(an_ac_chipid_dc),
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.an_ac_coreid(an_ac_coreid),
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.ac_an_machine_check(ac_an_machine_check),
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.an_ac_debug_stop(an_ac_debug_stop),
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.ac_an_debug_trigger(ac_an_debug_trigger),
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.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
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// L2 Outputs
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.ac_an_req_pwr_token(ac_an_req_pwr_token),
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.ac_an_req(ac_an_req),
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.ac_an_req_ra(ac_an_req_ra),
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.ac_an_req_ttype(ac_an_req_ttype),
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.ac_an_req_thread(ac_an_req_thread),
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.ac_an_req_wimg_w(ac_an_req_wimg_w),
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.ac_an_req_wimg_i(ac_an_req_wimg_i),
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.ac_an_req_wimg_m(ac_an_req_wimg_m),
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.ac_an_req_wimg_g(ac_an_req_wimg_g),
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.ac_an_req_user_defined(ac_an_req_user_defined),
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.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
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.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
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.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
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.ac_an_st_byte_enbl(ac_an_st_byte_enbl),
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.ac_an_st_data(ac_an_st_data),
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.ac_an_req_endian(ac_an_req_endian),
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.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
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);
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initial begin
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$dumpfile ("wtf-coco.vcd");
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// you can do it by levels and also by module so could prune down
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$dumpvars;
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// need to explicitly specify arrays for icarus
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// guess not: $dumpvars cannot dump a vpiMemory
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//$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q);
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#1;
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end
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// see if coco lets me risingedge() these
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wire clk_1x, clk_2x, clk_4x, rst;
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assign clk_1x = nclk[0];
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assign clk_2x = nclk[2];
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assign clk_4x = nclk[3];
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assign rst = nclk[1];
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endmodule |