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139 lines
5.3 KiB
Verilog
139 lines
5.3 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_err_rpt.v
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// *! DESCRIPTION : Error Reporting Component
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// *!****************************************************************
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`include "tri.vh"
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module tri_err_rpt(
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vd,
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gd,
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err_d1clk,
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err_d2clk,
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clk,
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rst,
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err_scan_in,
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err_scan_out,
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mode_dclk,
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mode_lclk,
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mode_scan_in,
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mode_scan_out,
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err_in,
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err_out,
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hold_out,
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mask_out
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);
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parameter WIDTH = 1; // number of errors of the same type
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parameter MASK_RESET_VALUE = 1'b0; // use to set default/flush value for mask bits
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parameter INLINE = 1'b0; // make hold latch be inline; err_out is sticky -- default to shadow
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parameter SHARE_MASK = 1'b0; // PERMISSION NEEDED for true
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// used for WIDTH >1 to reduce area of mask (common error disable)
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parameter USE_NLATS = 1'b0; // only necessary in standby area to be able to reset to init value
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parameter NEEDS_SRESET = 1; // for inferred latches
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inout vd;
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inout gd;
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input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported
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input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches
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//input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
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// caution2: and all bits in the "func" chain have to be connected to the mode chain
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input clk;
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input rst;
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// error scan chain (func or mode)
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input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring
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output [0:WIDTH-1] err_scan_out;
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// clock gateable mode clocks
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input mode_dclk;
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//input [0:`NCLK_WIDTH-1] mode_lclk;
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input mode_lclk;
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// mode scan chain
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input [0:WIDTH-1] mode_scan_in;
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output [0:WIDTH-1] mode_scan_out;
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input [0:WIDTH-1] err_in;
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output [0:WIDTH-1] err_out;
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output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage
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output [0:WIDTH-1] mask_out;
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parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE;
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wire [0:WIDTH-1] hold_in;
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wire [0:WIDTH-1] hold_lt;
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wire [0:WIDTH-1] mask_lt;
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(* analysis_not_referenced="true" *)
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wire unused;
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wire [0:WIDTH-1] unused_q_b;
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// hold latches
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assign hold_in = err_in | hold_lt;
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tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(NEEDS_SRESET))
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hold(
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.vd(vd),
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.gd(gd),
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.d1clk(err_d1clk),
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.d2clk(err_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in(err_scan_in[0:WIDTH - 1]),
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.scan_out(err_scan_out[0:WIDTH - 1]),
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.din(hold_in),
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.q(hold_lt),
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.q_b(unused_q_b)
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);
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generate
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begin
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// mask
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if (SHARE_MASK == 1'b0) begin
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assign mask_lt = mask_initv;
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end else begin
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assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
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end
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assign mode_scan_out = {WIDTH{1'b0}};
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// assign outputs
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assign hold_out = hold_lt;
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assign mask_out = mask_lt;
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if (INLINE == 1'b1) begin
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assign err_out = hold_lt & (~mask_lt);
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end else begin
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assign err_out = err_in & (~mask_lt);
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end
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assign unused = | {mode_dclk, mode_lclk, mode_scan_in, unused_q_b};
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end
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endgenerate
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endmodule
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