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138 lines
4.3 KiB
VHDL
138 lines
4.3 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.all;
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use work.a2x_pkg.all;
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entity a2o_dbug is
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port (
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clk : in std_logic;
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reset_n : in std_logic;
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threadstop_in : in std_logic_vector(0 to 3);
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trigger_in : in std_logic;
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trigger_threadstop : in std_logic_vector(0 to 3);
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trigger_ack_enable : in std_logic;
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trigger_out : out std_logic;
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trigger_ack_out : out std_logic;
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threadstop_out : out std_logic_vector(0 to 3);
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req_valid : in std_logic;
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req_id : in std_logic_vector(0 to 3);
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req_addr : in std_logic_vector(0 to 5);
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req_rw : in std_logic;
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req_wr_data : in std_logic_vector(0 to 63);
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rsp_valid : out std_logic;
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rsp_data : out std_logic_vector(0 to 63);
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dch_in : in std_logic;
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cch_in : in std_logic;
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dch_out : out std_logic;
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cch_out : out std_logic;
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err : out std_logic
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);
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end a2o_dbug;
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architecture a2o_dbug of a2o_dbug is
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signal counter_d, counter_q : std_logic_vector(0 to 39);
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signal trigger_ack_d, trigger_ack_q : std_logic;
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begin
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FF: process(clk) begin
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if rising_edge(clk) then
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if reset_n = '0' then
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counter_q <= (others => '0');
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trigger_ack_q <= '0';
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else
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counter_q <= counter_d;
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trigger_ack_q <= trigger_ack_d;
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end if;
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end if;
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end process FF;
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counter_d <= inc(counter_q);
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threadstop_out <= threadstop_in or gate_and(trigger_in, trigger_threadstop);
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trigger_out <= trigger_in;
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trigger_ack_d <= trigger_ack_enable and trigger_in;
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trigger_ack_out <= trigger_ack_q;
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scom: entity work.a2o_scom(a2o_scom)
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port map (
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clk => clk,
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reset_n => reset_n,
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req_valid => req_valid,
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req_id => req_id,
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req_addr => req_addr,
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req_rw => req_rw,
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req_wr_data => req_wr_data,
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rsp_valid => rsp_valid,
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rsp_data => rsp_data,
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dch_in => dch_in,
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cch_in => cch_in,
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dch_out => dch_out,
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cch_out => cch_out,
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err => err
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);
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end a2o_dbug;
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