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74 lines
2.4 KiB
Verilog
74 lines
2.4 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_aoi22.v
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// *! DESCRIPTION : AOI22 gate
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// *!
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_aoi22(
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y,
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a0,
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a1,
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b0,
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b1
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);
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parameter WIDTH = 1;
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parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select
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output [0:WIDTH-1] y;
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input [0:WIDTH-1] a0;
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input [0:WIDTH-1] a1;
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input [0:WIDTH-1] b0;
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input [0:WIDTH-1] b1;
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// tri_aoi22
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genvar i;
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wire [0:WIDTH-1] outA;
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wire [0:WIDTH-1] outB;
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generate
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begin : t
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for (i = 0; i < WIDTH; i = i + 1)
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begin : w
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and I0(outA[i], a0[i], a1[i]);
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and I1(outB[i], b0[i], b1[i]);
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nor I2(y[i], outA[i], outB[i]);
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end // block: w
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end
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endgenerate
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endmodule
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