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92 lines
3.4 KiB
Verilog
92 lines
3.4 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: XU Determine Leftmost Zero Byte
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//
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//*****************************************************************************
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module xu0_dlmzb(
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// Inputs
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input [32:63] byp_dlm_ex2_rs1,
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input [32:63] byp_dlm_ex2_rs2,
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input [0:2] byp_dlm_ex2_xer,
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// Outputs
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output [0:9] dlm_byp_ex2_xer,
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output [0:3] dlm_byp_ex2_cr,
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output [60:63] dlm_byp_ex2_rt
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);
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wire [0:7] a;
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wire [0:7] a0;
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wire [0:7] a1;
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wire [0:7] a2;
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wire [0:3] y;
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// Null == 0
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assign a[0] = |(byp_dlm_ex2_rs1[32:39]);
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assign a[1] = |(byp_dlm_ex2_rs1[40:47]);
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assign a[2] = |(byp_dlm_ex2_rs1[48:55]);
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assign a[3] = |(byp_dlm_ex2_rs1[56:63]);
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assign a[4] = |(byp_dlm_ex2_rs2[32:39]);
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assign a[5] = |(byp_dlm_ex2_rs2[40:47]);
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assign a[6] = |(byp_dlm_ex2_rs2[48:55]);
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assign a[7] = |(byp_dlm_ex2_rs2[56:63]);
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assign a0[1:7] = a[0:6] & a[1:7];
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assign a1[2:7] = a0[0:5] & a0[2:7];
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assign a2[4:7] = a1[0:3] & a1[4:7];
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assign a0[0:0] = a[0:0];
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assign a1[0:1] = a0[0:1];
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assign a2[0:3] = a1[0:3];
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assign y = (a2[0:7] == 8'b00000000) ? 4'b0001 : // Null in last 4B
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(a2[0:7] == 8'b10000000) ? 4'b0010 :
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(a2[0:7] == 8'b11000000) ? 4'b0011 :
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(a2[0:7] == 8'b11100000) ? 4'b0100 :
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(a2[0:7] == 8'b11110000) ? 4'b0101 :
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(a2[0:7] == 8'b11111000) ? 4'b0110 :
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(a2[0:7] == 8'b11111100) ? 4'b0111 :
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4'b1000;
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assign dlm_byp_ex2_cr[0] = (~a2[7]) & a2[3];
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assign dlm_byp_ex2_cr[1] = (~a2[7]) & (~a2[3]); // Null in first 4B
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assign dlm_byp_ex2_cr[2] = a2[7]; // Null not found
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assign dlm_byp_ex2_cr[3] = byp_dlm_ex2_xer[0]; // SO Copy
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assign dlm_byp_ex2_xer = {byp_dlm_ex2_xer[0:2], 3'b000, y[0:3]};
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assign dlm_byp_ex2_rt = y;
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endmodule
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