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// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
`timescale 1 ns / 1 ns
//
// Description: XU LSU Store Data Rotator Wrapper
//
//*****************************************************************************
// ##########################################################################################
// Contents
// 1) Load Queue
// 2) Store Queue
// 3) Load/Store Queue Control
// ##########################################################################################
`include "tri_a2o.vh"
module lq_ldq(
rv_lq_vld,
rv_lq_isLoad,
rv_lq_rvs_empty,
ctl_lsq_rv1_dir_rd_val,
l2_back_inv_val,
l2_back_inv_addr,
ctl_lsq_ex3_ldreq_val,
ctl_lsq_ex3_pfetch_val,
ctl_lsq_ex4_ldreq_val,
ctl_lsq_ex4_streq_val,
ctl_lsq_ex4_othreq_val,
ctl_lsq_ex4_p_addr,
ctl_lsq_ex4_itag,
ctl_lsq_ex4_dReq_val,
ctl_lsq_ex4_gath_load,
ctl_lsq_ex4_wimge,
ctl_lsq_ex4_is_sync,
ctl_lsq_ex4_all_thrd_chk,
ctl_lsq_ex4_byte_swap,
ctl_lsq_ex4_is_resv,
ctl_lsq_ex4_thrd_id,
ctl_lsq_ex5_lock_set,
ctl_lsq_ex5_watch_set,
ctl_lsq_ex5_thrd_id,
ctl_lsq_ex5_load_hit,
ctl_lsq_ex5_opsize,
ctl_lsq_ex5_tgpr,
ctl_lsq_ex5_axu_val,
ctl_lsq_ex5_usr_def,
ctl_lsq_ex5_drop_rel,
ctl_lsq_ex5_flush_req,
ctl_lsq_ex5_flush_pfetch,
ctl_lsq_ex5_cmmt_events,
ctl_lsq_ex5_perf_val0,
ctl_lsq_ex5_perf_sel0,
ctl_lsq_ex5_perf_val1,
ctl_lsq_ex5_perf_sel1,
ctl_lsq_ex5_perf_val2,
ctl_lsq_ex5_perf_sel2,
ctl_lsq_ex5_perf_val3,
ctl_lsq_ex5_perf_sel3,
ctl_lsq_ex5_not_touch,
ctl_lsq_ex5_algebraic,
ctl_lsq_ex5_class_id,
ctl_lsq_ex5_dvc,
ctl_lsq_ex5_ttype,
ctl_lsq_ex5_dacrw,
lsq_ctl_ex6_ldq_events,
lsq_perv_ex7_events,
lsq_perv_ldq_events,
ctl_lsq_ex7_thrd_id,
ctl_lsq_pf_empty,
ctl_lsq_spr_dvc1_dbg,
ctl_lsq_spr_dvc2_dbg,
ctl_lsq_spr_dbcr2_dvc1m,
ctl_lsq_spr_dbcr2_dvc1be,
ctl_lsq_spr_dbcr2_dvc2m,
ctl_lsq_spr_dbcr2_dvc2be,
ctl_lsq_dbg_int_en,
ctl_lsq_ldp_idle,
stq_ldq_ex5_stq_restart,
stq_ldq_ex5_stq_restart_miss,
stq_ldq_ex5_fwd_val,
odq_ldq_resolved,
odq_ldq_report_needed,
odq_ldq_report_itag,
odq_ldq_n_flush,
odq_ldq_np1_flush,
odq_ldq_report_tid,
odq_ldq_report_dacrw,
odq_ldq_report_eccue,
odq_ldq_report_pEvents,
odq_ldq_oldest_ld_tid,
odq_ldq_oldest_ld_itag,
odq_ldq_ex7_pfetch_blk,
stq_ldq_empty,
iu_lq_cp_flush,
iu_lq_cp_next_itag,
arb_ldq_ldq_unit_sel,
l2_lsq_resp_isComing,
l2_lsq_resp_val,
l2_lsq_resp_cTag,
l2_lsq_resp_qw,
l2_lsq_resp_crit_qw,
l2_lsq_resp_l1_dump,
l2_lsq_resp_data,
l2_lsq_resp_ecc_err,
l2_lsq_resp_ecc_err_ue,
xu_lq_spr_xucr0_cls,
ctl_lsq_spr_lsucr0_lge,
ctl_lsq_spr_lsucr0_lca,
pc_lq_inj_relq_parity,
ldq_stq_rel1_blk_store,
ldq_stq_ex5_ldm_hit,
ldq_stq_ex5_ldm_entry,
ldq_stq_ldm_cpl,
ldq_stq_stq4_dir_upd,
ldq_stq_stq4_cclass,
lq_rv_itag2_vld,
lq_rv_itag2,
ldq_rel2_byte_swap,
ldq_rel2_data,
ldq_odq_vld,
ldq_odq_pfetch_vld,
ldq_odq_wimge_i,
ldq_odq_ex6_pEvents,
ldq_odq_upd_val,
ldq_odq_upd_itag,
ldq_odq_upd_nFlush,
ldq_odq_upd_np1Flush,
ldq_odq_upd_tid,
ldq_odq_upd_dacrw,
ldq_odq_upd_eccue,
ldq_odq_upd_pEvents,
lq1_iu_execute_vld,
lq1_iu_itag,
lq1_iu_exception_val,
lq1_iu_exception,
lq1_iu_n_flush,
lq1_iu_np1_flush,
lq1_iu_dacr_type,
lq1_iu_dacrw,
lq1_iu_perf_events,
ldq_hold_all_req,
ldq_rv_set_hold,
ldq_rv_clr_hold,
lsq_ctl_ex5_ldq_restart,
ldq_arb_ld_req_pwrToken,
ldq_arb_ld_req_avail,
ldq_arb_tid,
ldq_arb_usr_def,
ldq_arb_wimge,
ldq_arb_p_addr,
ldq_arb_ttype,
ldq_arb_opsize,
ldq_arb_cTag,
ldq_dat_stq1_stg_act,
lsq_dat_rel1_data_val,
lsq_dat_rel1_qw,
ldq_ctl_stq1_stg_act,
lsq_ctl_rel1_clr_val,
lsq_ctl_rel1_set_val,
lsq_ctl_rel1_data_val,
lsq_ctl_rel1_thrd_id,
lsq_ctl_rel1_back_inv,
lsq_ctl_rel1_tag,
lsq_ctl_rel1_classid,
lsq_ctl_rel1_lock_set,
lsq_ctl_rel1_watch_set,
lsq_ctl_rel2_blk_req,
lsq_ctl_rel2_upd_val,
lsq_ctl_rel3_l1dump_val,
lsq_ctl_rel3_clr_relq,
ldq_arb_rel1_data_sel,
ldq_arb_rel1_axu_val,
ldq_arb_rel1_op_size,
ldq_arb_rel1_addr,
ldq_arb_rel1_ci,
ldq_arb_rel1_byte_swap,
ldq_arb_rel1_thrd_id,
ldq_arb_rel1_data,
ldq_arb_rel2_rdat_sel,
ldq_arb_rel2_rd_data,
arb_ldq_rel2_wrt_data,
lsq_ctl_rel1_gpr_val,
lsq_ctl_rel1_ta_gpr,
lsq_ctl_rel1_upd_gpr,
lq_pc_err_invld_reld,
lq_pc_err_l2intrf_ecc,
lq_pc_err_l2intrf_ue,
lq_pc_err_relq_parity,
lq_mm_lmq_stq_empty,
lq_xu_quiesce,
lq_pc_ldq_quiesce,
lq_pc_stq_quiesce,
lq_pc_pfetch_quiesce,
bo_enable_2,
clkoff_dc_b,
g8t_clkoff_dc_b,
g8t_d_mode_dc,
g8t_delay_lclkr_dc,
g8t_mpw1_dc_b,
g8t_mpw2_dc_b,
pc_lq_ccflush_dc,
an_ac_scan_dis_dc_b,
an_ac_scan_diag_dc,
an_ac_lbist_ary_wrt_thru_dc,
pc_lq_abist_ena_dc,
pc_lq_abist_raw_dc_b,
pc_lq_abist_wl64_comp_ena,
pc_lq_abist_raddr_0,
pc_lq_abist_g8t_wenb,
pc_lq_abist_g8t1p_renb_0,
pc_lq_abist_g8t_dcomp,
pc_lq_abist_g8t_bw_1,
pc_lq_abist_g8t_bw_0,
pc_lq_abist_di_0,
pc_lq_abist_waddr_0,
pc_lq_bo_unload,
pc_lq_bo_repair,
pc_lq_bo_reset,
pc_lq_bo_shdata,
pc_lq_bo_select,
lq_pc_bo_fail,
lq_pc_bo_diagout,
vcs,
vdd,
gnd,
clk,
rst,
sg_0,
func_sl_thold_0_b,
func_sl_force,
func_nsl_thold_0_b,
func_nsl_force,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
bolt_sl_thold_0,
d_mode_dc,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
scan_in,
abst_scan_in,
time_scan_in,
repr_scan_in,
scan_out,
abst_scan_out,
time_scan_out,
repr_scan_out
);
// RV1 RV Issue Valid
input [0:`THREADS-1] rv_lq_vld;
input rv_lq_isLoad;
// RV is empty indicator
input [0:`THREADS-1] rv_lq_rvs_empty;
// SPR Directory Read Valid
input ctl_lsq_rv1_dir_rd_val;
// Back-Invalidate Valid
input l2_back_inv_val;
input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] l2_back_inv_addr;
// Load Request Interface
input ctl_lsq_ex3_ldreq_val;
input ctl_lsq_ex3_pfetch_val;
input ctl_lsq_ex4_ldreq_val;
input ctl_lsq_ex4_streq_val;
input ctl_lsq_ex4_othreq_val;
input [64-`REAL_IFAR_WIDTH:63] ctl_lsq_ex4_p_addr;
input [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex4_itag;
input ctl_lsq_ex4_dReq_val;
input ctl_lsq_ex4_gath_load;
input [0:4] ctl_lsq_ex4_wimge;
input ctl_lsq_ex4_is_sync;
input ctl_lsq_ex4_all_thrd_chk;
input ctl_lsq_ex4_byte_swap;
input ctl_lsq_ex4_is_resv;
input [0:`THREADS-1] ctl_lsq_ex4_thrd_id;
input ctl_lsq_ex5_lock_set;
input ctl_lsq_ex5_watch_set;
input [0:`THREADS-1] ctl_lsq_ex5_thrd_id;
input ctl_lsq_ex5_load_hit;
input [0:2] ctl_lsq_ex5_opsize;
input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr;
input ctl_lsq_ex5_axu_val; // XU,AXU type operation
input [0:3] ctl_lsq_ex5_usr_def;
input ctl_lsq_ex5_drop_rel; // L2 only instructions
input ctl_lsq_ex5_flush_req; // Flush request from LDQ/STQ
input ctl_lsq_ex5_flush_pfetch; // Flush Prefetch in EX5
input [0:10] ctl_lsq_ex5_cmmt_events;
input ctl_lsq_ex5_perf_val0;
input [0:3] ctl_lsq_ex5_perf_sel0;
input ctl_lsq_ex5_perf_val1;
input [0:3] ctl_lsq_ex5_perf_sel1;
input ctl_lsq_ex5_perf_val2;
input [0:3] ctl_lsq_ex5_perf_sel2;
input ctl_lsq_ex5_perf_val3;
input [0:3] ctl_lsq_ex5_perf_sel3;
input ctl_lsq_ex5_not_touch;
input ctl_lsq_ex5_algebraic;
input [0:1] ctl_lsq_ex5_class_id;
input [0:1] ctl_lsq_ex5_dvc;
input [0:5] ctl_lsq_ex5_ttype;
input [0:3] ctl_lsq_ex5_dacrw;
output [0:3] lsq_ctl_ex6_ldq_events; // LDQ Pipeline Performance Events
output [0:`THREADS-1] lsq_perv_ex7_events; // LDQ Pipeline Performance Events
output [0:(2*`THREADS)+3] lsq_perv_ldq_events; // REL Pipeline Performance Events
input [0:`THREADS-1] ctl_lsq_ex7_thrd_id;
input [0:`THREADS-1] ctl_lsq_pf_empty;
// Interface with Local SPR's
input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc1_dbg;
input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc2_dbg;
input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1m;
input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1be;
input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2m;
input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2be;
input [0:`THREADS-1] ctl_lsq_dbg_int_en;
input [0:`THREADS-1] ctl_lsq_ldp_idle;
input stq_ldq_ex5_stq_restart;
input stq_ldq_ex5_stq_restart_miss;
input stq_ldq_ex5_fwd_val;
// OrderQ Inputs
input odq_ldq_resolved;
input odq_ldq_report_needed;
input [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag;
input odq_ldq_n_flush;
input odq_ldq_np1_flush;
input [0:`THREADS-1] odq_ldq_report_tid;
input [0:3] odq_ldq_report_dacrw;
input odq_ldq_report_eccue;
input [0:3] odq_ldq_report_pEvents;
input [0:`THREADS-1] odq_ldq_oldest_ld_tid;
input [0:`ITAG_SIZE_ENC-1] odq_ldq_oldest_ld_itag;
input odq_ldq_ex7_pfetch_blk;
// Store Queue is Empty
input [0:`THREADS-1] stq_ldq_empty;
// Completion Inputs
input [0:`THREADS-1] iu_lq_cp_flush;
input [0:`ITAG_SIZE_ENC*`THREADS-1] iu_lq_cp_next_itag;
// L2 Request Sent
input arb_ldq_ldq_unit_sel;
// L2 Reload
input l2_lsq_resp_isComing;
input l2_lsq_resp_val;
input [0:4] l2_lsq_resp_cTag;
input [57:59] l2_lsq_resp_qw;
input l2_lsq_resp_crit_qw;
input l2_lsq_resp_l1_dump;
input [0:127] l2_lsq_resp_data;
input l2_lsq_resp_ecc_err;
input l2_lsq_resp_ecc_err_ue;
// Data Cache Config
input xu_lq_spr_xucr0_cls; // Data Cache Line Size Mode
// Load Gather Enable Config
input ctl_lsq_spr_lsucr0_lge;
input [0:2] ctl_lsq_spr_lsucr0_lca;
// Inject Reload Data Array Parity Error
input pc_lq_inj_relq_parity;
// Interface to Store Queue
output ldq_stq_rel1_blk_store;
// Store Hit LoadMiss Queue Entries
output [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_hit;
output [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_entry;
output [0:`LMQ_ENTRIES-1] ldq_stq_ldm_cpl;
// Directory Congruence Class Updated
output ldq_stq_stq4_dir_upd;
output [64-(`DC_SIZE-3):57] ldq_stq_stq4_cclass;
// RV Reload Release Dependent ITAGs
output [0:`THREADS-1] lq_rv_itag2_vld;
output [0:`ITAG_SIZE_ENC-1] lq_rv_itag2;
// Physical Register File update data for Reloads
output ldq_rel2_byte_swap;
output [0:127] ldq_rel2_data;
// Load/Store Request was not restarted
output ldq_odq_vld;
output ldq_odq_pfetch_vld;
output ldq_odq_wimge_i;
output [0:3] ldq_odq_ex6_pEvents;
// Update Order Queue Entry when reload is complete and itag is not resolved
output ldq_odq_upd_val;
output [0:`ITAG_SIZE_ENC-1] ldq_odq_upd_itag;
output ldq_odq_upd_nFlush;
output ldq_odq_upd_np1Flush;
output [0:`THREADS-1] ldq_odq_upd_tid;
output [0:3] ldq_odq_upd_dacrw;
output ldq_odq_upd_eccue;
output [0:3] ldq_odq_upd_pEvents;
// Interface to Completion
output [0:`THREADS-1] lq1_iu_execute_vld;
output [0:`ITAG_SIZE_ENC-1] lq1_iu_itag;
output lq1_iu_exception_val;
output [0:5] lq1_iu_exception;
output lq1_iu_n_flush;
output lq1_iu_np1_flush;
output lq1_iu_dacr_type;
output [0:3] lq1_iu_dacrw;
output [0:3] lq1_iu_perf_events;
// Reservation station hold indicator
output ldq_hold_all_req;
// Reservation station set barrier indicator
output ldq_rv_set_hold;
output [0:`THREADS-1] ldq_rv_clr_hold;
// LOADMISS Queue RESTART indicator
output lsq_ctl_ex5_ldq_restart;
// LDQ Request to the L2
output ldq_arb_ld_req_pwrToken;
output ldq_arb_ld_req_avail;
output [0:1] ldq_arb_tid;
output [0:3] ldq_arb_usr_def;
output [0:4] ldq_arb_wimge;
output [64-`REAL_IFAR_WIDTH:63] ldq_arb_p_addr;
output [0:5] ldq_arb_ttype;
output [0:2] ldq_arb_opsize;
output [0:4] ldq_arb_cTag;
// RELOAD Data Control
output ldq_dat_stq1_stg_act; // ACT Pin for DAT
output lsq_dat_rel1_data_val;
output [57:59] lsq_dat_rel1_qw; // RELOAD Data Quadword
// RELOAD Directory Control
output ldq_ctl_stq1_stg_act; // ACT Pin for CTL
output lsq_ctl_rel1_clr_val; // Reload Data is valid, need to Pick a Way to update
output lsq_ctl_rel1_set_val; // Reload Data is valid for last beat, update Directory Contents and set Valid
output lsq_ctl_rel1_data_val; // Reload Data is Valid, need to update Way in Data Cache
output [0:`THREADS-1] lsq_ctl_rel1_thrd_id; // Reload Thread ID for initial requester
output lsq_ctl_rel1_back_inv; // Reload was Back-Invalidated
output [0:3] lsq_ctl_rel1_tag; // Reload Tag
output [0:1] lsq_ctl_rel1_classid; // Used to index into xucr2 RMT table
output lsq_ctl_rel1_lock_set; // Reload is for a dcbt[st]ls instruction
output lsq_ctl_rel1_watch_set; // Reload is for a ldawx. instruction
output lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate
output lsq_ctl_rel2_upd_val; // all 8 data beats have transferred without error, set valid in dir
output lsq_ctl_rel3_l1dump_val; // Reload Complete for an L1_DUMP reload
output lsq_ctl_rel3_clr_relq; // Reload Complete due to an ECC error
// Control Common to Reload and Commit Pipes
output ldq_arb_rel1_data_sel;
output ldq_arb_rel1_axu_val;
output [0:2] ldq_arb_rel1_op_size;
output [64-`REAL_IFAR_WIDTH:63] ldq_arb_rel1_addr;
output ldq_arb_rel1_ci;
output ldq_arb_rel1_byte_swap;
output [0:`THREADS-1] ldq_arb_rel1_thrd_id;
output [0:127] ldq_arb_rel1_data;
output ldq_arb_rel2_rdat_sel;
output [0:143] ldq_arb_rel2_rd_data;
input [0:143] arb_ldq_rel2_wrt_data;
// RELOAD Register Control
output lsq_ctl_rel1_gpr_val; // Critical Quadword requires an update of the Regfile
output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_rel1_ta_gpr; // Reload Target Register
output lsq_ctl_rel1_upd_gpr; // Critical Quadword did not get and ECC error in REL1
// Interface to Pervasive Unit
output lq_pc_err_invld_reld; // Reload detected without Loadmiss waiting for reload or got extra beats for cacheable request
output lq_pc_err_l2intrf_ecc; // Reload detected with an ECC error
output lq_pc_err_l2intrf_ue; // Reload detected with an uncorrectable ECC error
output lq_pc_err_relq_parity; // Reload Data Queue Parity Error Detected
// Thread Quiesced
output [0:`THREADS-1] lq_xu_quiesce; // Thread is Quiesced
output [0:`THREADS-1] lq_pc_ldq_quiesce;
output [0:`THREADS-1] lq_pc_stq_quiesce;
output [0:`THREADS-1] lq_pc_pfetch_quiesce;
// Interface to MMU
output lq_mm_lmq_stq_empty; // Load and Store Queue is empty
// Array Pervasive Controls
input bo_enable_2;
input clkoff_dc_b;
input g8t_clkoff_dc_b;
input g8t_d_mode_dc;
input [0:4] g8t_delay_lclkr_dc;
input [0:4] g8t_mpw1_dc_b;
input g8t_mpw2_dc_b;
input pc_lq_ccflush_dc;
input an_ac_scan_dis_dc_b;
input an_ac_scan_diag_dc;
input an_ac_lbist_ary_wrt_thru_dc;
input pc_lq_abist_ena_dc;
input pc_lq_abist_raw_dc_b;
input pc_lq_abist_wl64_comp_ena;
input [3:8] pc_lq_abist_raddr_0;
input pc_lq_abist_g8t_wenb;
input pc_lq_abist_g8t1p_renb_0;
input [0:3] pc_lq_abist_g8t_dcomp;
input pc_lq_abist_g8t_bw_1;
input pc_lq_abist_g8t_bw_0;
input [0:3] pc_lq_abist_di_0;
input [4:9] pc_lq_abist_waddr_0;
input pc_lq_bo_unload;
input pc_lq_bo_repair;
input pc_lq_bo_reset;
input pc_lq_bo_shdata;
input [8:9] pc_lq_bo_select;
output [8:9] lq_pc_bo_fail;
output [8:9] lq_pc_bo_diagout;
// Pervasive
inout vcs;
inout vdd;
inout gnd;
input clk;
input rst;
input sg_0;
input func_sl_thold_0_b;
input func_sl_force;
input func_nsl_thold_0_b;
input func_nsl_force;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;
input bolt_sl_thold_0;
input d_mode_dc;
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input abst_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input time_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input repr_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output abst_scan_out;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output time_scan_out;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output repr_scan_out;
//--------------------------
// components
//--------------------------
//--------------------------
// signals
//--------------------------
parameter numGrps = ((((`LMQ_ENTRIES-1)/4)+1)*4);
parameter AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREADS_POOL_ENC;
wire [0:`LMQ_ENTRIES-1] ldqe_dRel_d;
wire [0:`LMQ_ENTRIES-1] ldqe_dRel_q;
wire [0:1] ldqe_dGpr_cntrl[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_dGpr_d;
wire [0:`LMQ_ENTRIES-1] ldqe_dGpr_q;
wire [0:`THREADS-1] ldqe_thrd_id_d[0:`LMQ_ENTRIES-1];
wire [0:`THREADS-1] ldqe_thrd_id_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_wimge_i;
wire [0:`LMQ_ENTRIES-1] ldqe_wimge_g;
wire [0:4] ldqe_wimge_d[0:`LMQ_ENTRIES-1];
wire [0:4] ldqe_wimge_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_byte_swap_d;
wire [0:`LMQ_ENTRIES-1] ldqe_byte_swap_q;
wire [0:`LMQ_ENTRIES-1] ldqe_resv_d;
wire [0:`LMQ_ENTRIES-1] ldqe_resv_q;
wire [0:`LMQ_ENTRIES-1] ldqe_pfetch_d;
wire [0:`LMQ_ENTRIES-1] ldqe_pfetch_q;
wire [0:2] ldqe_op_size_d[0:`LMQ_ENTRIES-1];
wire [0:2] ldqe_op_size_q[0:`LMQ_ENTRIES-1];
wire [0:AXU_TARGET_ENC-1] ldqe_tgpr_d[0:`LMQ_ENTRIES-1];
wire [0:AXU_TARGET_ENC-1] ldqe_tgpr_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_axu_d;
wire [0:`LMQ_ENTRIES-1] ldqe_axu_q;
wire [0:3] ldqe_usr_def_d[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_usr_def_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_lock_set_d;
wire [0:`LMQ_ENTRIES-1] ldqe_lock_set_q;
wire [0:`LMQ_ENTRIES-1] ldqe_watch_set_d;
wire [0:`LMQ_ENTRIES-1] ldqe_watch_set_q;
wire [0:`LMQ_ENTRIES-1] ldqe_algebraic_d;
wire [0:`LMQ_ENTRIES-1] ldqe_algebraic_q;
wire [0:1] ldqe_class_id_d[0:`LMQ_ENTRIES-1];
wire [0:1] ldqe_class_id_q[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_perf_events_d[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_perf_events_q[0:`LMQ_ENTRIES-1];
wire [0:1] ldqe_set_gpr_done[0:`LMQ_ENTRIES-1];
wire [0:1] ldqe_dvc_d[0:`LMQ_ENTRIES-1];
wire [0:1] ldqe_dvc_q[0:`LMQ_ENTRIES-1];
wire [0:5] ldqe_ttype_d[0:`LMQ_ENTRIES-1];
wire [0:5] ldqe_ttype_q[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_dacrw_d[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_dacrw_q[0:`LMQ_ENTRIES-1];
wire [0:`ITAG_SIZE_ENC-1] ldqe_itag_d[0:`LMQ_ENTRIES-1];
wire [0:`ITAG_SIZE_ENC-1] ldqe_itag_q[0:`LMQ_ENTRIES-1];
wire [64-`REAL_IFAR_WIDTH:57] ldqe_p_addr_msk[0:`LMQ_ENTRIES-1];
wire [64-`REAL_IFAR_WIDTH:63] ldqe_p_addr_d[0:`LMQ_ENTRIES-1];
wire [64-`REAL_IFAR_WIDTH:63] ldqe_p_addr_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_cp_flush;
wire [0:`LMQ_ENTRIES-1] ldqe_odq_flush;
wire [0:`LMQ_ENTRIES-1] ldqe_pfetch_flush;
wire [0:`LMQ_ENTRIES-1] ldqe_flush;
wire [0:`LMQ_ENTRIES-1] ldqe_kill;
wire [0:`LMQ_ENTRIES-1] ldqe_mkill;
wire [0:`LMQ_ENTRIES-1] ldqe_mkill_d;
wire [0:`LMQ_ENTRIES-1] ldqe_mkill_q;
wire [0:`LMQ_ENTRIES-1] ldqe_resolved;
wire [0:`LMQ_ENTRIES-1] ldqe_resolved_d;
wire [0:`LMQ_ENTRIES-1] ldqe_resolved_q;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_d;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_q;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_nFlush_d;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_nFlush_q;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_np1Flush_d;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_np1Flush_q;
wire [0:`LMQ_ENTRIES-1] ex5_ldm_hit_d;
wire [0:`LMQ_ENTRIES-1] ex5_ldm_hit_q;
wire spr_xucr0_cls_d;
wire spr_xucr0_cls_q;
wire spr_lsucr0_lge_d;
wire spr_lsucr0_lge_q;
wire [0:2] spr_lsucr0_lca_d;
wire [0:2] spr_lsucr0_lca_q;
wire spr_lsucr0_lca_zero;
wire [0:2] spr_lsucr0_lca_ovrd;
wire [0:`THREADS-1] iu_lq_cp_flush_d;
wire [0:`THREADS-1] iu_lq_cp_flush_q;
wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_q[0:`THREADS-1];
wire ex4_stg_flush;
wire ex5_stg_flush;
wire odq_ldq_n_flush_d;
wire odq_ldq_n_flush_q;
wire odq_ldq_resolved_d;
wire odq_ldq_resolved_q;
wire [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag_d;
wire [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag_q;
wire [0:`THREADS-1] odq_ldq_report_tid_d;
wire [0:`THREADS-1] odq_ldq_report_tid_q;
wire [0:`THREADS-1] rv_lq_rvs_empty_d;
wire [0:`THREADS-1] rv_lq_rvs_empty_q;
wire ldq_rel1_set_rviss_dir_coll;
wire ldq_rel1_set_binv_dir_coll;
wire ldq_rel1_set_rd_dir_coll;
wire rel2_blk_req_d;
wire rel2_blk_req_q;
wire rel2_rviss_blk_d;
wire rel2_rviss_blk_q;
wire [64-`REAL_IFAR_WIDTH:57] l2_back_inv_addr_msk;
wire [64-`REAL_IFAR_WIDTH:57] ex4_p_addr_msk;
wire ex4_ldreq_d;
wire ex4_ldreq_q;
wire ex5_ldreq_val;
wire ex5_ldreq_val_d;
wire ex5_ldreq_val_q;
wire ex5_ldreq_flushed;
wire ex4_pfetch_val_d;
wire ex4_pfetch_val_q;
wire ex5_pfetch_val;
wire ex5_pfetch_val_d;
wire ex5_pfetch_val_q;
wire ex5_pfetch_flushed;
wire ex5_odq_ldreq_val_d;
wire ex5_odq_ldreq_val_q;
wire ex5_streq_val_d;
wire ex5_streq_val_q;
wire ex5_othreq_val_d;
wire ex5_othreq_val_q;
wire [64-`REAL_IFAR_WIDTH:63] ex5_p_addr_d;
wire [64-`REAL_IFAR_WIDTH:63] ex5_p_addr_q;
wire [0:4] ex5_wimge_d;
wire [0:4] ex5_wimge_q;
wire [0:11] ex5_cmmt_events;
wire [0:3] ex5_cmmt_perf_events;
wire [0:3] ex6_cmmt_perf_events_d;
wire [0:3] ex6_cmmt_perf_events_q;
wire [0:`LMQ_ENTRIES-1] ex4_ldqe_set_val;
wire [0:`LMQ_ENTRIES-1] ex4_ldqe_set_all;
wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_all_d;
wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_all_q;
wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_val_d;
wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_val_q;
wire [0:`LMQ_ENTRIES-1] ex6_ldqe_pfetch_val_d;
wire [0:`LMQ_ENTRIES-1] ex6_ldqe_pfetch_val_q;
wire [0:`LMQ_ENTRIES-1] ex7_ldqe_pfetch_val_d;
wire [0:`LMQ_ENTRIES-1] ex7_ldqe_pfetch_val_q;
wire ex7_pfetch_blk_val;
wire [0:`THREADS-1] ex7_pfetch_blk_tid;
wire [0:`LMQ_ENTRIES-1] ex5_ldm_entry;
reg [0:`THREADS-1] ldq_all_req_home;
wire [0:`THREADS-1] lq_xu_quiesce_d;
wire [0:`THREADS-1] lq_xu_quiesce_q;
wire lq_mm_lmq_stq_empty_d;
wire lq_mm_lmq_stq_empty_q;
wire [0:`THREADS-1] lq_pc_ldq_quiesce_d;
wire [0:`THREADS-1] lq_pc_ldq_quiesce_q;
wire [0:`THREADS-1] lq_pc_stq_quiesce_d;
wire [0:`THREADS-1] lq_pc_stq_quiesce_q;
wire [0:`THREADS-1] lq_pc_pfetch_quiesce_d;
wire [0:`THREADS-1] lq_pc_pfetch_quiesce_q;
reg [0:3] ex5_cTag;
reg [0:1] ex5_tid_enc;
wire [0:3] ldqe_beat_init;
wire [0:`LMQ_ENTRIES-1] ldqe_wrt_ptr;
wire [0:`LMQ_ENTRIES-1] ldqe_opposite_ptr;
wire ex4_one_machine_avail;
wire ex4_oldest_load;
wire ex4_reserved_taken;
wire ex5_reserved_taken_d;
wire ex5_reserved_taken_q;
wire ex4_resv_taken_restart;
wire ex5_resv_taken_restart_d;
wire ex5_resv_taken_restart_q;
wire [0:`LMQ_ENTRIES+`LGQ_ENTRIES-1] ldqe_cpl_sel;
wire [0:`LMQ_ENTRIES+`LGQ_ENTRIES-1] ldqe_cpl_sent;
wire [0:`LMQ_ENTRIES-1] ex5_inv_ldqe;
wire ex4_ldq_full;
wire ex5_ldq_full_d;
wire ex5_ldq_full_q;
wire ex4_ldq_full_restart;
wire ex5_ldq_full_restart_d;
wire ex5_ldq_full_restart_q;
wire ex4_ldq_hit;
wire ex5_ldq_hit_d;
wire ex5_ldq_hit_q;
wire ldq_full_qHit_held_set;
wire ldq_full_qHit_held_clr;
wire [0:1] ldq_full_qHit_held_ctrl;
wire ldq_full_qHit_held_d;
wire ldq_full_qHit_held_q;
wire ldq_resv_qHit_held_set;
wire ldq_resv_qHit_held_clr;
wire [0:1] ldq_resv_qHit_held_ctrl;
wire ldq_resv_qHit_held_d;
wire ldq_resv_qHit_held_q;
wire ldq_oth_qHit_clr_d;
wire ldq_oth_qHit_clr_q;
wire ex5_ldq_set_hold_d;
wire ex5_ldq_set_hold_q;
wire ex5_ldq_full_set_hold;
wire ex5_setHold;
wire ldq_clrHold;
wire [0:`THREADS-1] ldq_clrHold_tid;
wire [0:`THREADS-1] ldq_setHold_tid;
wire [0:`THREADS-1] ldq_hold_tid;
wire [0:`THREADS-1] ldq_hold_tid_d;
wire [0:`THREADS-1] ldq_hold_tid_q;
wire ex5_ldq_restart;
wire ex5_ldq_restart_d;
wire ex5_ldq_restart_q;
wire ex6_ldq_full_d;
wire ex6_ldq_full_q;
wire ex6_ldq_hit_d;
wire ex6_ldq_hit_q;
wire ex5_lgq_full_d;
wire ex5_lgq_full_q;
wire ex6_lgq_full_d;
wire ex6_lgq_full_q;
wire ex5_lgq_qwhit_d;
wire ex5_lgq_qwhit_q;
wire ex6_lgq_qwhit_d;
wire ex6_lgq_qwhit_q;
wire ex5_restart_val;
wire ex5_drop_req_val;
wire ex5_drop_gath;
wire perf_ex6_ldq_full_restart;
wire perf_ex6_ldq_hit_restart;
wire perf_ex6_lgq_full_restart;
wire perf_ex6_lgq_qwhit_restart;
wire [0:`LMQ_ENTRIES-1] ldqe_inuse;
wire [0:`THREADS-1] ldqe_tid_inuse[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_req_outstanding;
wire [0:`THREADS-1] ldqe_tid_req_outstanding[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_req_able_to_hold;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_blk_qHit_held;
wire [0:`LMQ_ENTRIES-1] ex4_load_qHit_upd;
wire [0:`LMQ_ENTRIES-1] ex4_addr_m_queue;
wire [0:`LMQ_ENTRIES-1] ex4_qw_hit_queue;
reg [0:`LMQ_ENTRIES-1] ex4_lgq_qw_hit;
wire ex5_ld_gath_d;
wire ex5_ld_gath_q;
wire ex4_ld_gath;
wire [0:`LMQ_ENTRIES-1] ldqe_entry_gatherable;
wire [0:`LMQ_ENTRIES-1] ex4_entry_gatherable;
wire [0:`LMQ_ENTRIES-1] ex4_entry_gath_ld;
wire [0:`LMQ_ENTRIES-1] ex4_entry_gath_full;
wire [0:`LMQ_ENTRIES-1] ex4_entry_gath_qwhit;
wire [0:`LMQ_ENTRIES-1] ex4_thrd_id_m;
wire [0:`LMQ_ENTRIES-1] ex4_larx_hit;
wire [0:`LMQ_ENTRIES-1] ex4_guarded_hit;
wire [0:`LMQ_ENTRIES-1] ex4_req_hit_ldq;
wire [0:`LMQ_ENTRIES-1] ex4_entry_load_qHit;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv;
wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_flush_upd;
wire [0:`THREADS-1] ldqe_cpNext_tid[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_cpNext_val;
wire [0:((((`LMQ_ENTRIES-1)/4)+1)*4)-1] ldqe_sent;
reg [0:`LMQ_ENTRIES-1] ldqe_req_cmpl_d;
wire [0:`LMQ_ENTRIES-1] ldqe_req_cmpl_q;
reg [0:`LMQ_ENTRIES-1] ldqe_val_d;
wire [0:`LMQ_ENTRIES-1] ldqe_val_q;
wire [0:`LMQ_ENTRIES-1] ldqe_ctrl_act;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_inprog;
wire [0:`LMQ_ENTRIES-1] ldqe_zap;
wire [0:`LMQ_ENTRIES-1] ldqe_need_l2send;
wire [0:1] ldqe_beat_ctrl[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_beat_incr[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_beat_cntr_d[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_beat_cntr_q[0:`LMQ_ENTRIES-1];
wire ex5_upd_fifo_val;
wire fifo_ldq_act;
wire fifo_ldq_req_compr_val;
wire fifo_ldq_req_sent;
wire fifo_ldq_req0_mkill;
wire fifo_ldq_req0_avail;
wire [0:1] fifo_ldq_wrt_ptr_cntrl;
wire fifo_ldq_reset_ptr;
wire [0:`LMQ_ENTRIES] fifo_ldq_req_nxt_ptr;
wire [0:`LMQ_ENTRIES] fifo_ldq_req_nxt_ptr_d;
wire [0:`LMQ_ENTRIES] fifo_ldq_req_nxt_ptr_q;
wire [0:`LMQ_ENTRIES] fifo_ldq_req_wrt_ptr;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_upd;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_empty_entry;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_push;
wire [0:1] fifo_ldq_req_cntrl[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_val;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_val_d;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_val_q;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_match;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_send;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_d;
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_q;
wire [0:`THREADS-1] fifo_ldq_req_tid_d[0:`LMQ_ENTRIES-1];
wire [0:`THREADS-1] fifo_ldq_req_tid_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_d[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_q[0:`LMQ_ENTRIES-1];
reg [0:3] ldq_mux_usr_def;
reg [0:4] ldq_mux_wimge;
reg [64-`REAL_IFAR_WIDTH:63] ldq_mux_p_addr;
reg [0:5] ldq_mux_ttype;
reg [0:2] ldq_mux_opsize;
reg [0:`THREADS-1] ldq_mux_tid;
reg [0:1] ldq_mux_tid_enc;
reg [0:3] ldq_mux_cTag;
wire [0:`LMQ_ENTRIES-1] ldqe_relmin1_cTag;
wire [0:`LMQ_ENTRIES-1] ldqe_rel0_cTag;
wire [0:`LMQ_ENTRIES-1] ldqe_rel1_cTag;
wire [0:`LMQ_ENTRIES-1] ldq_relmin1_l2_val;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_l2_val_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_l2_val_q;
wire [0:`LMQ_ENTRIES-1] ldq_relmin1_l2_inval;
wire [0:`LMQ_ENTRIES-1] ldq_rel_l2_l1dumpBlk;
wire [0:`LMQ_ENTRIES-1] ldq_relmin1_l2_qHitBlk;
wire [0:`LMQ_ENTRIES-1] ldqe_cpNext_ecc_err;
wire [0:`LMQ_ENTRIES-1] ldqe_nFlush_ecc_err;
reg [0:6] ldqe_nxt_state[0:`LMQ_ENTRIES-1];
wire [0:6] ldqe_state_d[0:`LMQ_ENTRIES-1];
wire [0:6] ldqe_state_q[0:`LMQ_ENTRIES-1];
wire [0:3] ldq_resp_cTag;
wire [57:59] ldq_resp_qw;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_beats_home;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_beats_home_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_beats_home_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_beats_home_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_beats_home_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_beats_home_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_beats_home_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_beats_home_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_beats_home_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_entrySent;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_entrySent_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_entrySent_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_entrySent_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_entrySent_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_entrySent_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_entrySent_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_sentL1_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_sentL1_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_sentL1_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_sentL1_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_req_noL1done;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_req_done;
wire [0:`LMQ_ENTRIES-1] ldq_rel6_req_done_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel6_req_done_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_ci_done;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_drel_done;
wire ldq_rel1_val_d;
wire ldq_rel1_val_q;
wire ldq_rel1_arb_val_d;
wire ldq_rel1_arb_val_q;
wire ldq_rel0_rdat_sel;
wire [0:2] ldq_rel0_rdat_qw;
wire ldq_rel1_l1_dump_d;
wire ldq_rel1_l1_dump_q;
wire ldq_rel2_l1_dump_d;
wire ldq_rel2_l1_dump_q;
wire ldq_rel3_l1_dump_d;
wire ldq_rel3_l1_dump_q;
wire ldq_rel3_l1_dump_val;
wire ldq_rel3_clr_relq_d;
wire ldq_rel3_clr_relq_q;
wire [0:2] ldq_rel1_resp_qw_d;
wire [0:2] ldq_rel1_resp_qw_q;
wire [0:3] ldq_rel1_cTag_d;
wire [0:3] ldq_rel1_cTag_q;
wire l2_rel1_resp_val_d;
wire l2_rel1_resp_val_q;
wire l2_rel2_resp_val_d;
wire l2_rel2_resp_val_q;
wire ldq_err_inval_rel_d;
wire ldq_err_inval_rel_q;
wire ldq_err_ecc_det_d;
wire ldq_err_ecc_det_q;
wire ldq_err_ue_det_d;
wire ldq_err_ue_det_q;
wire ldq_rel3_rdat_par_err;
reg [0:2] ldq_rel_mux_opsize;
reg ldq_rel_mux_wimge_i;
reg ldq_rel_mux_byte_swap;
reg [64-`REAL_IFAR_WIDTH:63] ldq_rel_mux_p_addr;
wire [64-(`DC_SIZE-3):57] ldq_rel_mux_p_addr_msk;
reg [0:1] ldq_rel_mux_dvcEn;
reg ldq_rel_mux_lockSet;
reg ldq_rel_mux_watchSet;
reg [0:AXU_TARGET_ENC-1] ldq_rel_mux_tGpr;
reg ldq_rel_mux_axu;
reg ldq_rel_mux_algEn;
reg [0:1] ldq_rel_mux_classID;
reg [0:`THREADS-1] ldq_rel_mux_tid;
reg ldq_rel1_mux_back_inv;
reg [0:2] lgq_rel_mux_opsize;
reg [59:63] lgq_rel_mux_p_addr;
reg lgq_rel_mux_byte_swap;
reg [0:1] lgq_rel_mux_dvcEn;
reg [0:AXU_TARGET_ENC-1] lgq_rel_mux_tGpr;
reg lgq_rel_mux_axu;
reg lgq_rel_mux_algEn;
reg [0:`THREADS-1] lgq_rel_mux_tid;
wire [0:2] ldq_rel1_opsize_d;
wire [0:2] ldq_rel1_opsize_q;
wire ldq_rel1_wimge_i_d;
wire ldq_rel1_wimge_i_q;
wire ldq_rel1_byte_swap_d;
wire ldq_rel1_byte_swap_q;
wire ldq_rel2_byte_swap_d;
wire ldq_rel2_byte_swap_q;
wire [64-`REAL_IFAR_WIDTH:63] ldq_rel1_p_addr_d;
wire [64-`REAL_IFAR_WIDTH:63] ldq_rel1_p_addr_q;
wire [0:1] ldq_rel1_dvcEn_d;
wire [0:1] ldq_rel1_dvcEn_q;
wire ldq_rel1_lockSet_d;
wire ldq_rel1_lockSet_q;
wire ldq_rel1_watchSet_d;
wire ldq_rel1_watchSet_q;
wire [0:AXU_TARGET_ENC-1] ldq_rel1_tGpr_d;
wire [0:AXU_TARGET_ENC-1] ldq_rel1_tGpr_q;
wire ldq_rel1_axu_d;
wire ldq_rel1_axu_q;
wire ldq_rel1_algEn_d;
wire ldq_rel1_algEn_q;
wire [0:1] ldq_rel1_classID_d;
wire [0:1] ldq_rel1_classID_q;
wire [0:`THREADS-1] ldq_rel1_tid_d;
wire [0:`THREADS-1] ldq_rel1_tid_q;
wire [0:`THREADS-1] ldq_rel2_tid_d;
wire [0:`THREADS-1] ldq_rel2_tid_q;
wire [0:`THREADS-1] ldq_rel1_dir_tid_d;
wire [0:`THREADS-1] ldq_rel1_dir_tid_q;
reg [0:`ITAG_SIZE_ENC-1] ldqe_relmin1_iTag;
reg [0:`THREADS-1] ldqe_relmin1_tid;
reg [0:`ITAG_SIZE_ENC-1] lgqe_relmin1_iTag;
reg [0:`THREADS-1] lgqe_relmin1_tid;
wire [0:`THREADS-1] ldq_relmin1_tid;
wire [0:`ITAG_SIZE_ENC-1] ldq_relmin1_iTag;
wire [0:7] ldq_rel0_beat_upd;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_sentL1;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_sentL1_blk;
wire [0:1] ldqe_sentRel_ctrl[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_sentRel_incr[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_sentRel_cntr_d[0:`LMQ_ENTRIES-1];
wire [0:3] ldqe_sentRel_cntr_q[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_sentL1;
wire [0:`LMQ_ENTRIES-1] ldqe_last_beat;
wire [0:`LMQ_ENTRIES-1] ldqe_rel2_l1upd_cmpl;
wire [0:1] ldqe_rel_start_ctrl[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_relDir_start;
wire [0:`LMQ_ENTRIES-1] ldqe_relDir_start_d;
wire [0:`LMQ_ENTRIES-1] ldqe_relDir_start_q;
wire ldq_rel0_arb_val;
wire [0:3] ldq_rel0_arb_cTag;
wire ldq_rel0_arb_thresh;
wire [0:2] ldq_rel0_arb_qw;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_arb_sent;
wire ldq_rel0_arr_wren;
wire ldq_rel1_clr_val;
wire ldq_l2_rel0_qHitBlk_d;
wire ldq_l2_rel0_qHitBlk_q;
wire ldq_l2_resp_hold_all;
wire ldq_rel_arb_hold_all;
wire [64-(`DC_SIZE-3):57] ldq_rel2_cclass_d;
wire [64-(`DC_SIZE-3):57] ldq_rel2_cclass_q;
wire [64-(`DC_SIZE-3):57] ldq_rel3_cclass_d;
wire [64-(`DC_SIZE-3):57] ldq_rel3_cclass_q;
wire [64-(`DC_SIZE-3):57] ldq_rel4_cclass_d;
wire [64-(`DC_SIZE-3):57] ldq_rel4_cclass_q;
wire ldq_rel1_set_val;
wire ldq_rel2_set_val_d;
wire ldq_rel2_set_val_q;
wire ldq_rel3_set_val_d;
wire ldq_rel3_set_val_q;
wire ldq_rel4_set_val_d;
wire ldq_rel4_set_val_q;
wire ldq_rel1_data_val;
wire ldq_rel1_data_sel_d;
wire ldq_rel1_data_sel_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_l2_val_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_l2_val_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_l2_val_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_l2_val_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_l2_val_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_l2_val_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_l2_val_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_l2_val_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_l2_val_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_l2_val_q;
reg [0:`LMQ_ENTRIES-1] ldqe_cntr_reset_d;
wire [0:`LMQ_ENTRIES-1] ldqe_cntr_reset_q;
reg [0:`LMQ_ENTRIES-1] ldqe_resent_ecc_err_d;
wire [0:`LMQ_ENTRIES-1] ldqe_resent_ecc_err_q;
reg [0:`LMQ_ENTRIES-1] ldqe_reset_cpl_rpt_d;
wire [0:`LMQ_ENTRIES-1] ldqe_reset_cpl_rpt_q;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_rdat_perr;
reg [0:`LMQ_ENTRIES-1] ldqe_ecc_err_dgpr;
reg [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet;
wire [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet_d;
wire [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet_q;
wire [0:1] ldqe_rel_eccdet_sel[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_d;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_q;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_ue;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_ue_d;
wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_ue_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_gpr_ecc_err;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_gpr_eccue_err;
wire [0:1] ldqe_upd_gpr_ecc_sel[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_ecc;
wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_ecc_d;
wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_ecc_q;
wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_eccue;
wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_eccue_d;
wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_eccue_q;
wire rel0_stg_act;
wire ldq_reload_val;
wire [0:1] ldqe_rel_l1_dump_ctrl[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_drop_reload_val;
wire [0:`LMQ_ENTRIES-1] ldq_rel_l1_dump;
wire [0:`LMQ_ENTRIES-1] ldqe_l1_dump_d;
wire [0:`LMQ_ENTRIES-1] ldqe_l1_dump_q;
wire [57:59] ldq_reload_qw;
wire [0:`LMQ_ENTRIES-1] ldqe_relmin1_upd_gpr;
wire ldq_itag2_rel_val;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_crit_qw;
wire ldq_rel1_gpr_val;
wire ldq_rel1_gpr_val_d;
wire ldq_rel1_gpr_val_q;
wire rel2_eccdet;
wire rel2_eccdet_ue;
wire rel2_eccdet_err;
wire ldq_rel2_rdat_perr;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_upd_gpr_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel0_upd_gpr_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_upd_gpr_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_upd_gpr_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_upd_gpr_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_upd_gpr_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_upd_gpr_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_upd_gpr_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_upd_gpr;
wire [0:`LMQ_ENTRIES-1] ldqe_rel2_drop_cpl_rpt;
wire [0:`LMQ_ENTRIES-1] ldqe_rel3_drop_cpl_rpt_d;
wire [0:`LMQ_ENTRIES-1] ldqe_rel3_drop_cpl_rpt_q;
wire [0:`LMQ_ENTRIES-1] ldqe_reld_cpl_rpt;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_send_cpl_ok;
wire [0:`LMQ_ENTRIES-1] ldq_rel6_send_cpl_ok;
wire [0:`LMQ_ENTRIES-1] ldq_rel_send_cpl_ok;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_odq_cpl;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_odq_cpl_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel4_odq_cpl_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_odq_cpl_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_odq_cpl_q;
wire ldq_l2_req_need_send;
wire ldq_rel0_updating_cache;
wire ldq_rel1_collide_binv_d;
wire ldq_rel1_collide_binv_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel1_dbeat_val;
wire ldq_stq_rel1_blk_store_d;
wire ldq_stq_rel1_blk_store_q;
wire [0:`LMQ_ENTRIES-1] ldq_rel2_qHit_clr;
wire [0:1] ldqe_qHit_clr_sel[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldq_rel_qHit_clr_d;
wire [0:`LMQ_ENTRIES-1] ldq_rel_qHit_clr_q;
wire [0:1] ldqe_qHit_held_sel[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_qHit_held_d;
wire [0:`LMQ_ENTRIES-1] ldqe_qHit_held_q;
wire ldq_rel2_rv_clr_hold;
wire [0:`LMQ_ENTRIES-1] ldqe_available;
wire [0:`LMQ_ENTRIES-1] ldqe_cpl_rpt_done;
wire [0:`LMQ_ENTRIES-1] ldqe_need_cpl_rst;
wire [0:1] ldqe_need_cpl_sel[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_need_cpl_d;
wire [0:`LMQ_ENTRIES-1] ldqe_need_cpl_q;
wire [0:`LMQ_ENTRIES-1] ldqe_send_cpl;
wire [0:1] ldqe_sent_cpl_sel[0:`LMQ_ENTRIES-1];
wire [0:`LMQ_ENTRIES-1] ldqe_sent_cpl_d;
wire [0:`LMQ_ENTRIES-1] ldqe_sent_cpl_q;
wire [0:`LMQ_ENTRIES-1] ldqe_complete;
wire [0:`LMQ_ENTRIES+`LGQ_ENTRIES-1] ldqe_remove;
wire [0:3] cpl_grpEntry_val[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
wire [0:3] cpl_grpEntry_sel[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
wire [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_sent;
wire [0:3] cpl_grpEntry_last_sel_d[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
wire [0:3] cpl_grpEntry_last_sel_q[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
reg [0:`ITAG_SIZE_ENC-1] cpl_grpEntry_iTag[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_ecc;
reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_eccue;
reg [0:1] cpl_grpEntry_dvc[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
reg [0:3] cpl_grpEntry_dacrw[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
reg [0:`THREADS-1] cpl_grpEntry_tid[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_nFlush;
reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_np1Flush;
reg [0:3] cpl_grpEntry_pEvents[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4];
reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_larx;
wire [0:3] cpl_group_val;
wire [0:3] cpl_group_sel;
wire [0:3] cpl_group_last_sel_d;
wire [0:3] cpl_group_last_sel_q;
wire cpl_credit_sent;
reg [0:`ITAG_SIZE_ENC-1] cpl_send_itag;
reg cpl_ecc_dec;
reg cpl_eccue_dec;
reg [0:1] cpl_dvc;
reg [0:3] cpl_dacrw;
reg [0:`THREADS-1] cpl_tid;
reg cpl_nFlush;
reg cpl_np1Flush;
reg [0:3] cpl_pEvents;
reg cpl_larx;
wire ldq_cpl_odq_zap;
wire ldq_cpl_odq_val;
wire ldq_cpl_odq_dbg_int_en;
wire ldq_cpl_odq_n_flush;
wire [0:3] ldq_cpl_odq_dacrw;
wire ldq_cpl_odq_eccue;
wire ldq_cpl_pending;
wire [0:`THREADS-1] ldq_execute_vld;
wire [0:`THREADS-1] odq_execute_vld;
wire [0:`THREADS-1] lq1_iu_execute_vld_d;
wire [0:`THREADS-1] lq1_iu_execute_vld_q;
wire [0:`ITAG_SIZE_ENC-1] lq1_iu_itag_d;
wire [0:`ITAG_SIZE_ENC-1] lq1_iu_itag_q;
wire lq1_iu_n_flush_d;
wire lq1_iu_n_flush_q;
wire lq1_iu_np1_flush_d;
wire lq1_iu_np1_flush_q;
wire lq1_iu_exception_val_d;
wire lq1_iu_exception_val_q;
wire ldq_cpl_dbg_int_en;
wire ldq_cpl_oth_flush;
wire ldq_cpl_n_flush;
wire ldq_cpl_np1_flush;
wire [0:1] ldq_cpl_dvc;
wire [0:3] ldq_cpl_dacrw;
wire [0:3] lq1_iu_dacrw_d;
wire [0:3] lq1_iu_dacrw_q;
wire [0:3] lq1_iu_perf_events_d;
wire [0:3] lq1_iu_perf_events_q;
wire [0:`THREADS-1] ldq_cpl_larx_d;
wire [0:`THREADS-1] ldq_cpl_larx_q;
wire [0:`THREADS-1] ldq_cpl_binv_d;
wire [0:`THREADS-1] ldq_cpl_binv_q;
wire ldq_rel_cmmt_d;
wire ldq_rel_cmmt_q;
wire ldq_rel_need_hole_d;
wire ldq_rel_need_hole_q;
wire ldq_rel_latency_d;
wire ldq_rel_latency_q;
wire [0:`THREADS-1] perf_ldq_cpl_larx;
wire [0:`THREADS-1] perf_ldq_cpl_binv;
wire perf_ldq_rel_attmpt;
wire perf_ldq_rel_cmmt;
wire perf_ldq_rel_need_hole;
wire perf_ldq_rel_latency;
wire ex4_stg_act_d;
wire ex4_stg_act_q;
wire ex5_stg_act_d;
wire ex5_stg_act_q;
wire [0:`LMQ_ENTRIES-1] ex4_ldqe_act;
wire [0:`LMQ_ENTRIES-1] ex5_ldqe_act;
wire [0:`LMQ_ENTRIES-1] ex4_lgqe_act;
wire [0:`LMQ_ENTRIES-1] ex5_lgqe_act;
reg [0:3] ldq_gath_Tag;
wire [0:`LGQ_ENTRIES-1] lgqe_wrt_ptr;
wire ld_gath_not_full;
wire [0:`LGQ_ENTRIES-1] lgqe_available;
wire [0:`LGQ_ENTRIES-1] lgqe_cpl_sent;
wire [0:`LGQ_ENTRIES-1] lgq_reset_val;
wire [0:`LGQ_ENTRIES-1] lgqe_odq_flush;
wire [0:`LGQ_ENTRIES-1] lgqe_cp_flush;
wire [0:`LGQ_ENTRIES-1] lgqe_kill;
wire [0:`LGQ_ENTRIES-1] lgqe_valid_d;
wire [0:`LGQ_ENTRIES-1] lgqe_valid_q;
wire ex4_gath_val;
wire [0:`LGQ_ENTRIES-1] ex4_lgqe_set_val;
wire [0:`LGQ_ENTRIES-1] ex4_lgqe_set_all;
wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_all_d;
wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_all_q;
wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_val_d;
wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_val_q;
wire [0:`LGQ_ENTRIES-1] ex5_lgqe_restart;
wire [0:`LGQ_ENTRIES-1] ex5_lgqe_drop;
wire ex5_lgq_restart;
wire [0:`THREADS-1] lgqe_thrd_id_d[0:`LGQ_ENTRIES-1];
wire [0:`THREADS-1] lgqe_thrd_id_q[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] lgqe_byte_swap_d;
wire [0:`LGQ_ENTRIES-1] lgqe_byte_swap_q;
wire [0:`LGQ_ENTRIES-1] lqg_qw_match;
wire [0:2] lgqe_set_op_size[0:`LGQ_ENTRIES-1];
wire [0:2] lgqe_op_size_d[0:`LGQ_ENTRIES-1];
wire [0:2] lgqe_op_size_q[0:`LGQ_ENTRIES-1];
wire [0:AXU_TARGET_ENC-1] lgqe_set_tgpr[0:`LGQ_ENTRIES-1];
wire [0:AXU_TARGET_ENC-1] lgqe_tgpr_d[0:`LGQ_ENTRIES-1];
wire [0:AXU_TARGET_ENC-1] lgqe_tgpr_q[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] lgqe_set_axu;
wire [0:`LGQ_ENTRIES-1] lgqe_axu_d;
wire [0:`LGQ_ENTRIES-1] lgqe_axu_q;
wire [0:3] lgqe_perf_events_d[0:`LGQ_ENTRIES-1];
wire [0:3] lgqe_perf_events_q[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] lgqe_set_algebraic;
wire [0:`LGQ_ENTRIES-1] lgqe_algebraic_d;
wire [0:`LGQ_ENTRIES-1] lgqe_algebraic_q;
wire [0:`LGQ_ENTRIES-1] lgqe_gpr_done_d;
wire [0:`LGQ_ENTRIES-1] lgqe_gpr_done_q;
wire [0:`LGQ_ENTRIES-1] lgqe_resolved;
wire [0:`LGQ_ENTRIES-1] lgqe_resolved_d;
wire [0:`LGQ_ENTRIES-1] lgqe_resolved_q;
wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_nFlush_d;
wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_nFlush_q;
wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_np1Flush_d;
wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_np1Flush_q;
wire [0:1] lgqe_set_gpr_done[0:`LGQ_ENTRIES-1];
wire [0:1] lgqe_set_dvc[0:`LGQ_ENTRIES-1];
wire [0:1] lgqe_dvc_d[0:`LGQ_ENTRIES-1];
wire [0:1] lgqe_dvc_q[0:`LGQ_ENTRIES-1];
wire [0:3] lgqe_dacrw_d[0:`LGQ_ENTRIES-1];
wire [0:3] lgqe_dacrw_q[0:`LGQ_ENTRIES-1];
wire [0:`ITAG_SIZE_ENC-1] lgqe_itag_d[0:`LGQ_ENTRIES-1];
wire [0:`ITAG_SIZE_ENC-1] lgqe_itag_q[0:`LGQ_ENTRIES-1];
wire [57:63] lgqe_p_addr_d[0:`LGQ_ENTRIES-1];
wire [57:63] lgqe_p_addr_q[0:`LGQ_ENTRIES-1];
wire [0:3] lgqe_ldTag_d[0:`LGQ_ENTRIES-1];
wire [0:3] lgqe_ldTag_q[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] ldq_gath_Tag_1hot[0:`LMQ_ENTRIES-1];
reg [0:`LMQ_ENTRIES-1] ldqe_gather_done;
wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_flush_upd;
wire [0:`THREADS-1] lgqe_cpNext_tid[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] lgqe_cpNext_val;
wire [0:1] lgqe_upd_gpr_ecc_sel[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_ecc;
wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_ecc_d;
wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_ecc_q;
wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_eccue;
wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_eccue_d;
wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_eccue_q;
wire [0:`LGQ_ENTRIES-1] lgqe_cpl_rpt_done;
wire [0:`LGQ_ENTRIES-1] lgqe_need_cpl_rst;
wire [0:1] lgqe_need_cpl_sel[0:`LGQ_ENTRIES-1];
wire [0:`LGQ_ENTRIES-1] lgqe_need_cpl_d;
wire [0:`LGQ_ENTRIES-1] lgqe_need_cpl_q;
wire [0:`LGQ_ENTRIES-1] lgqe_send_cpl;
wire lgq_rel1_gpr_val_d;
wire lgq_rel1_gpr_val_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel0_upd_gpr_d;
wire [0:`LGQ_ENTRIES-1] lgq_rel0_upd_gpr_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel1_upd_gpr_d;
wire [0:`LGQ_ENTRIES-1] lgq_rel1_upd_gpr_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel2_upd_gpr_d;
wire [0:`LGQ_ENTRIES-1] lgq_rel2_upd_gpr_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel3_upd_gpr_d;
wire [0:`LGQ_ENTRIES-1] lgq_rel3_upd_gpr_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel4_upd_gpr_d;
wire [0:`LGQ_ENTRIES-1] lgq_rel4_upd_gpr_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel5_upd_gpr_d;
wire [0:`LGQ_ENTRIES-1] lgq_rel5_upd_gpr_q;
wire [0:`LGQ_ENTRIES-1] lgq_rel1_upd_gpr;
wire [0:`LGQ_ENTRIES-1] lgq_rel2_upd_gpr;
wire [0:`LGQ_ENTRIES-1] lgqe_relmin1_match;
wire [0:`LGQ_ENTRIES-1] lgqe_relmin1_upd_gpr;
wire [0:`LGQ_ENTRIES-1] lgq_rel2_send_cpl_ok;
reg [0:`ITAG_SIZE_ENC-1] ldq_rel3_odq_itag;
reg ldq_rel3_odq_ecc;
reg ldq_rel3_odq_eccue;
reg [0:1] ldq_rel3_odq_dvc;
reg [0:3] ldq_rel3_odq_dacrw;
reg [0:`THREADS-1] ldq_rel3_odq_tid;
reg ldq_rel3_odq_nFlush;
reg ldq_rel3_odq_np1Flush;
reg [0:3] ldq_rel3_odq_pEvents;
wire ldq_rel3_odq_dbg_int_en;
wire ldq_rel3_odq_oth_flush;
wire [0:3] ldq_rel3_dacrw;
wire [0:`LMQ_ENTRIES-1] ldq_rel3_odq_val;
wire [0:`LGQ_ENTRIES-1] lgq_rel3_odq_val;
wire [0:`LMQ_ENTRIES-1] ldq_rel5_odq_cpl;
wire [0:`LGQ_ENTRIES-1] lgq_rel5_odq_cpl;
wire ldq_state_machines_idle;
wire ldq_relmin1_ldq_val;
wire [0:3] ldq_relmin1_cTag;
wire l2_rel0_resp_val_d;
wire l2_rel0_resp_val_q;
wire l2_rel0_resp_ldq_val_d;
wire l2_rel0_resp_ldq_val_q;
wire [0:3] l2_rel0_resp_cTag_d;
wire [0:3] l2_rel0_resp_cTag_q;
wire [57:59] l2_rel0_resp_qw_d;
wire [57:59] l2_rel0_resp_qw_q;
wire l2_rel0_resp_crit_qw_d;
wire l2_rel0_resp_crit_qw_q;
wire l2_rel0_resp_l1_dump_d;
wire l2_rel0_resp_l1_dump_q;
wire [0:2] ldq_rel0_opsize;
wire [59:63] ldq_rel0_p_addr;
wire [0:4] ldq_rel0_opsize_1hot;
wire [0:4] ldq_rel0_rot_size;
wire [0:4] ldq_rel0_rot_max_size_le;
wire [0:4] ldq_rel0_rot_sel_le;
wire [0:3] ldq_rel0_rot_sel;
wire ldq_rel0_byte_swap;
wire [0:3] ldq_rel1_algebraic_sel_d;
wire [0:3] ldq_rel1_algebraic_sel_q;
wire lvl1_sel;
wire [0:1] lvl2_sel;
wire [0:1] lvl3_sel;
wire [0:1] rotate_sel1;
wire [0:3] rotate_sel2;
wire [0:3] rotate_sel3;
wire [0:7] ldq_rel1_rot_sel1_d;
wire [0:7] ldq_rel1_rot_sel1_q;
wire [0:7] ldq_rel1_rot_sel2_d;
wire [0:7] ldq_rel1_rot_sel2_q;
wire [0:7] ldq_rel1_rot_sel3_d;
wire [0:7] ldq_rel1_rot_sel3_q;
wire [0:127] ldq_rel1_data;
wire [0:127] ldq_rel2_rot_data;
wire [0:1] ldq_rel2_dvc;
wire [0:`THREADS-1] dbg_int_en_d;
wire [0:`THREADS-1] dbg_int_en_q;
wire rdat_scan_in;
wire rdat_scan_out;
//--------------------------
// constants
//--------------------------
parameter spr_xucr0_cls_offset = 0;
parameter spr_lsucr0_lge_offset = spr_xucr0_cls_offset + 1;
parameter spr_lsucr0_lca_offset = spr_lsucr0_lge_offset + 1;
parameter l2_rel0_resp_val_offset = spr_lsucr0_lca_offset + 3;
parameter l2_rel0_resp_ldq_val_offset = l2_rel0_resp_val_offset + 1;
parameter l2_rel0_resp_cTag_offset = l2_rel0_resp_ldq_val_offset + 1;
parameter l2_rel0_resp_qw_offset = l2_rel0_resp_cTag_offset + 4;
parameter l2_rel0_resp_crit_qw_offset = l2_rel0_resp_qw_offset + 3;
parameter l2_rel0_resp_l1_dump_offset = l2_rel0_resp_crit_qw_offset + 1;
parameter ldq_rel1_algebraic_sel_offset = l2_rel0_resp_l1_dump_offset + 1;
parameter ldq_rel1_rot_sel1_offset = ldq_rel1_algebraic_sel_offset + 4;
parameter ldq_rel1_rot_sel2_offset = ldq_rel1_rot_sel1_offset + 8;
parameter ldq_rel1_rot_sel3_offset = ldq_rel1_rot_sel2_offset + 8;
parameter iu_lq_cp_flush_offset = ldq_rel1_rot_sel3_offset + 8;
parameter iu_lq_cp_next_itag_offset = iu_lq_cp_flush_offset + `THREADS;
parameter odq_ldq_n_flush_offset = iu_lq_cp_next_itag_offset + (`THREADS) * (`ITAG_SIZE_ENC);
parameter odq_ldq_resolved_offset = odq_ldq_n_flush_offset + 1;
parameter odq_ldq_report_itag_offset = odq_ldq_resolved_offset + 1;
parameter odq_ldq_report_tid_offset = odq_ldq_report_itag_offset + `ITAG_SIZE_ENC;
parameter rv_lq_rvs_empty_offset = odq_ldq_report_tid_offset + `THREADS;
parameter rel2_blk_req_offset = rv_lq_rvs_empty_offset + `THREADS;
parameter rel2_rviss_blk_offset = rel2_blk_req_offset + 1;
parameter ldq_rel1_collide_binv_offset = rel2_rviss_blk_offset + 1;
parameter ldq_stq_rel1_blk_store_offset = ldq_rel1_collide_binv_offset + 1;
parameter ex4_ldreq_offset = ldq_stq_rel1_blk_store_offset + 1;
parameter ex5_ldreq_val_offset = ex4_ldreq_offset + 1;
parameter ex4_pfetch_val_offset = ex5_ldreq_val_offset + 1;
parameter ex5_pfetch_val_offset = ex4_pfetch_val_offset + 1;
parameter ex5_odq_ldreq_val_offset = ex5_pfetch_val_offset + 1;
parameter ex5_streq_val_offset = ex5_odq_ldreq_val_offset + 1;
parameter ex5_othreq_val_offset = ex5_streq_val_offset + 1;
parameter ex5_reserved_taken_offset = ex5_othreq_val_offset + 1;
parameter ex5_resv_taken_restart_offset = ex5_reserved_taken_offset + 1;
parameter lq_xu_quiesce_offset = ex5_resv_taken_restart_offset + 1;
parameter lq_pc_ldq_quiesce_offset = lq_xu_quiesce_offset + `THREADS;
parameter lq_pc_stq_quiesce_offset = lq_pc_ldq_quiesce_offset + `THREADS;
parameter lq_pc_pfetch_quiesce_offset = lq_pc_stq_quiesce_offset + `THREADS;
parameter lq_mm_lmq_stq_empty_offset = lq_pc_pfetch_quiesce_offset + `THREADS;
parameter ex5_ldq_full_offset = lq_mm_lmq_stq_empty_offset + 1;
parameter ex5_ldq_full_restart_offset = ex5_ldq_full_offset + 1;
parameter ex5_ldq_hit_offset = ex5_ldq_full_restart_offset + 1;
parameter ex5_ld_gath_offset = ex5_ldq_hit_offset + 1;
parameter ldq_full_qHit_held_offset = ex5_ld_gath_offset + 1;
parameter ldq_resv_qHit_held_offset = ldq_full_qHit_held_offset + 1;
parameter ldq_oth_qHit_clr_offset = ldq_resv_qHit_held_offset + 1;
parameter ex5_ldq_set_hold_offset = ldq_oth_qHit_clr_offset + 1;
parameter ex5_ldq_restart_offset = ex5_ldq_set_hold_offset + 1;
parameter ex6_ldq_full_offset = ex5_ldq_restart_offset + 1;
parameter ex6_ldq_hit_offset = ex6_ldq_full_offset + 1;
parameter ex5_lgq_full_offset = ex6_ldq_hit_offset + 1;
parameter ex6_lgq_full_offset = ex5_lgq_full_offset + 1;
parameter ex5_lgq_qwhit_offset = ex6_lgq_full_offset + 1;
parameter ex6_lgq_qwhit_offset = ex5_lgq_qwhit_offset + 1;
parameter ex5_p_addr_offset = ex6_lgq_qwhit_offset + 1;
parameter ex5_wimge_offset = ex5_p_addr_offset + `REAL_IFAR_WIDTH;
parameter ex6_cmmt_perf_events_offset = ex5_wimge_offset + 5;
parameter ex5_ldqe_set_all_offset = ex6_cmmt_perf_events_offset + 4;
parameter ex5_ldqe_set_val_offset = ex5_ldqe_set_all_offset + `LMQ_ENTRIES;
parameter ex6_ldqe_pfetch_val_offset = ex5_ldqe_set_val_offset + `LMQ_ENTRIES;
parameter ex7_ldqe_pfetch_val_offset = ex6_ldqe_pfetch_val_offset + `LMQ_ENTRIES;
parameter ex5_ldm_hit_offset = ex7_ldqe_pfetch_val_offset + `LMQ_ENTRIES;
parameter ldq_hold_tid_offset = ex5_ldm_hit_offset + `LMQ_ENTRIES;
parameter fifo_ldq_req_nxt_ptr_offset = ldq_hold_tid_offset + `THREADS;
parameter fifo_ldq_req_val_offset = fifo_ldq_req_nxt_ptr_offset + `LMQ_ENTRIES + 1;
parameter fifo_ldq_req_pfetch_offset = fifo_ldq_req_val_offset + `LMQ_ENTRIES;
parameter fifo_ldq_req_tid_offset = fifo_ldq_req_pfetch_offset + `LMQ_ENTRIES;
parameter fifo_ldq_req_offset = fifo_ldq_req_tid_offset + (`THREADS) * `LMQ_ENTRIES;
parameter ldqe_val_offset = fifo_ldq_req_offset + (`LMQ_ENTRIES) * `LMQ_ENTRIES;
parameter ldqe_req_cmpl_offset = ldqe_val_offset + `LMQ_ENTRIES;
parameter ldqe_cntr_reset_offset = ldqe_req_cmpl_offset + `LMQ_ENTRIES;
parameter ldqe_resent_ecc_err_offset = ldqe_cntr_reset_offset + `LMQ_ENTRIES;
parameter ldqe_reset_cpl_rpt_offset = ldqe_resent_ecc_err_offset + `LMQ_ENTRIES;
parameter ldqe_itag_offset = ldqe_reset_cpl_rpt_offset + `LMQ_ENTRIES;
parameter ldqe_thrd_id_offset = ldqe_itag_offset + (`ITAG_SIZE_ENC) * `LMQ_ENTRIES;
parameter ldqe_wimge_offset = ldqe_thrd_id_offset + `THREADS * `LMQ_ENTRIES;
parameter ldqe_byte_swap_offset = ldqe_wimge_offset + 5 * `LMQ_ENTRIES;
parameter ldqe_resv_offset = ldqe_byte_swap_offset + `LMQ_ENTRIES;
parameter ldqe_pfetch_offset = ldqe_resv_offset + `LMQ_ENTRIES;
parameter ldqe_op_size_offset = ldqe_pfetch_offset + `LMQ_ENTRIES;
parameter ldqe_tgpr_offset = ldqe_op_size_offset + 3 * `LMQ_ENTRIES;
parameter ldqe_usr_def_offset = ldqe_tgpr_offset + (`LMQ_ENTRIES) * (AXU_TARGET_ENC);
parameter ldqe_class_id_offset = ldqe_usr_def_offset + 4 * `LMQ_ENTRIES;
parameter ldqe_perf_events_offset = ldqe_class_id_offset + 2 * `LMQ_ENTRIES;
parameter ldqe_dvc_offset = ldqe_perf_events_offset + 4 * `LMQ_ENTRIES;
parameter ldqe_ttype_offset = ldqe_dvc_offset + 2 * `LMQ_ENTRIES;
parameter ldqe_dacrw_offset = ldqe_ttype_offset + 6 * `LMQ_ENTRIES;
parameter ldqe_p_addr_offset = ldqe_dacrw_offset + 4 * `LMQ_ENTRIES;
parameter ldqe_mkill_offset = ldqe_p_addr_offset + `REAL_IFAR_WIDTH * `LMQ_ENTRIES;
parameter ldqe_resolved_offset = ldqe_mkill_offset + `LMQ_ENTRIES;
parameter ldqe_back_inv_offset = ldqe_resolved_offset + `LMQ_ENTRIES;
parameter ldqe_back_inv_nFlush_offset = ldqe_back_inv_offset + `LMQ_ENTRIES;
parameter ldqe_back_inv_np1Flush_offset = ldqe_back_inv_nFlush_offset + `LMQ_ENTRIES;
parameter ldqe_beat_cntr_offset = ldqe_back_inv_np1Flush_offset + `LMQ_ENTRIES;
parameter ldqe_dRel_offset = ldqe_beat_cntr_offset + 4 * `LMQ_ENTRIES;
parameter ldqe_l1_dump_offset = ldqe_dRel_offset + `LMQ_ENTRIES;
parameter ldqe_dGpr_offset = ldqe_l1_dump_offset + `LMQ_ENTRIES;
parameter ldqe_axu_offset = ldqe_dGpr_offset + `LMQ_ENTRIES;
parameter ldqe_lock_set_offset = ldqe_axu_offset + `LMQ_ENTRIES;
parameter ldqe_watch_set_offset = ldqe_lock_set_offset + `LMQ_ENTRIES;
parameter ldqe_algebraic_offset = ldqe_watch_set_offset + `LMQ_ENTRIES;
parameter ldqe_state_offset = ldqe_algebraic_offset + `LMQ_ENTRIES;
parameter ldqe_sentRel_cntr_offset = ldqe_state_offset + 7 * `LMQ_ENTRIES;
parameter ex5_lgqe_set_all_offset = ldqe_sentRel_cntr_offset + 4 * `LMQ_ENTRIES;
parameter ex5_lgqe_set_val_offset = ex5_lgqe_set_all_offset + `LGQ_ENTRIES;
parameter lgqe_valid_offset = ex5_lgqe_set_val_offset + `LGQ_ENTRIES;
parameter lgqe_iTag_offset = lgqe_valid_offset + `LGQ_ENTRIES;
parameter lgqe_ldTag_offset = lgqe_iTag_offset + (`ITAG_SIZE_ENC) * `LGQ_ENTRIES;
parameter lgqe_thrd_id_offset = lgqe_ldTag_offset + 4 * `LGQ_ENTRIES;
parameter lgqe_byte_swap_offset = lgqe_thrd_id_offset + `THREADS * `LGQ_ENTRIES;
parameter lgqe_op_size_offset = lgqe_byte_swap_offset + `LGQ_ENTRIES;
parameter lgqe_tgpr_offset = lgqe_op_size_offset + 3 * `LGQ_ENTRIES;
parameter lgqe_gpr_done_offset = lgqe_tgpr_offset + (`LGQ_ENTRIES) * (AXU_TARGET_ENC);
parameter lgqe_resolved_offset = lgqe_gpr_done_offset + `LGQ_ENTRIES;
parameter lgqe_back_inv_nFlush_offset = lgqe_resolved_offset + `LGQ_ENTRIES;
parameter lgqe_back_inv_np1Flush_offset = lgqe_back_inv_nFlush_offset + `LGQ_ENTRIES;
parameter lgqe_dacrw_offset = lgqe_back_inv_np1Flush_offset + `LGQ_ENTRIES;
parameter lgqe_dvc_offset = lgqe_dacrw_offset + 4 * `LGQ_ENTRIES;
parameter lgqe_p_addr_offset = lgqe_dvc_offset + 2 * `LGQ_ENTRIES;
parameter lgqe_axu_offset = lgqe_p_addr_offset + 7 * `LGQ_ENTRIES;
parameter lgqe_perf_events_offset = lgqe_axu_offset + `LGQ_ENTRIES;
parameter lgqe_upd_gpr_ecc_offset = lgqe_perf_events_offset + 4 * `LGQ_ENTRIES;
parameter lgqe_upd_gpr_eccue_offset = lgqe_upd_gpr_ecc_offset + `LGQ_ENTRIES;
parameter lgqe_need_cpl_offset = lgqe_upd_gpr_eccue_offset + `LGQ_ENTRIES;
parameter lgqe_algebraic_offset = lgqe_need_cpl_offset + `LGQ_ENTRIES;
parameter ldqe_rst_eccdet_offset = lgqe_algebraic_offset + `LMQ_ENTRIES;
parameter ldq_rel2_beats_home_offset = ldqe_rst_eccdet_offset + `LMQ_ENTRIES;
parameter ldq_rel3_beats_home_offset = ldq_rel2_beats_home_offset + `LMQ_ENTRIES;
parameter ldq_rel4_beats_home_offset = ldq_rel3_beats_home_offset + `LMQ_ENTRIES;
parameter ldq_rel5_beats_home_offset = ldq_rel4_beats_home_offset + `LMQ_ENTRIES;
parameter ldq_rel1_entrySent_offset = ldq_rel5_beats_home_offset + `LMQ_ENTRIES;
parameter ldq_rel2_entrySent_offset = ldq_rel1_entrySent_offset + `LMQ_ENTRIES;
parameter ldq_rel3_entrySent_offset = ldq_rel2_entrySent_offset + `LMQ_ENTRIES;
parameter ldq_rel4_sentL1_offset = ldq_rel3_entrySent_offset + `LMQ_ENTRIES;
parameter ldq_rel5_sentL1_offset = ldq_rel4_sentL1_offset + `LMQ_ENTRIES;
parameter ldq_rel6_req_done_offset = ldq_rel5_sentL1_offset + `LMQ_ENTRIES;
parameter l2_rel1_resp_val_offset = ldq_rel6_req_done_offset + `LMQ_ENTRIES;
parameter l2_rel2_resp_val_offset = l2_rel1_resp_val_offset + 1;
parameter ldq_err_inval_rel_offset = l2_rel2_resp_val_offset + 1;
parameter ldq_err_ecc_det_offset = ldq_err_inval_rel_offset + 1;
parameter ldq_err_ue_det_offset = ldq_err_ecc_det_offset + 1;
parameter ldq_rel1_val_offset = ldq_err_ue_det_offset + 1;
parameter ldq_rel1_arb_val_offset = ldq_rel1_val_offset + 1;
parameter ldq_rel1_l1_dump_offset = ldq_rel1_arb_val_offset + 1;
parameter ldq_rel2_l1_dump_offset = ldq_rel1_l1_dump_offset + 1;
parameter ldq_rel3_l1_dump_offset = ldq_rel2_l1_dump_offset + 1;
parameter ldq_rel3_clr_relq_offset = ldq_rel3_l1_dump_offset + 1;
parameter ldq_rel1_resp_qw_offset = ldq_rel3_clr_relq_offset + 1;
parameter ldq_rel1_cTag_offset = ldq_rel1_resp_qw_offset + 3;
parameter ldq_rel1_opsize_offset = ldq_rel1_cTag_offset + 4;
parameter ldq_rel1_wimge_i_offset = ldq_rel1_opsize_offset + 3;
parameter ldq_rel1_byte_swap_offset = ldq_rel1_wimge_i_offset + 1;
parameter ldq_rel2_byte_swap_offset = ldq_rel1_byte_swap_offset + 1;
parameter ldq_rel1_p_addr_offset = ldq_rel2_byte_swap_offset + 1;
parameter ldq_rel1_dvcEn_offset = ldq_rel1_p_addr_offset + `REAL_IFAR_WIDTH;
parameter ldq_rel1_lockSet_offset = ldq_rel1_dvcEn_offset + 2;
parameter ldq_rel1_watchSet_offset = ldq_rel1_lockSet_offset + 1;
parameter ldq_rel1_tGpr_offset = ldq_rel1_watchSet_offset + 1;
parameter ldq_rel1_axu_offset = ldq_rel1_tGpr_offset + AXU_TARGET_ENC;
parameter ldq_rel1_algEn_offset = ldq_rel1_axu_offset + 1;
parameter ldq_rel1_classID_offset = ldq_rel1_algEn_offset + 1;
parameter ldq_rel1_tid_offset = ldq_rel1_classID_offset + 2;
parameter ldq_rel2_tid_offset = ldq_rel1_tid_offset + `THREADS;
parameter ldq_rel1_dir_tid_offset = ldq_rel2_tid_offset + `THREADS;
parameter ldqe_relDir_start_offset = ldq_rel1_dir_tid_offset + `THREADS;
parameter ldq_rel2_set_val_offset = ldqe_relDir_start_offset + `LMQ_ENTRIES;
parameter ldq_rel3_set_val_offset = ldq_rel2_set_val_offset + 1;
parameter ldq_rel4_set_val_offset = ldq_rel3_set_val_offset + 1;
parameter ldq_rel2_cclass_offset = ldq_rel4_set_val_offset + 1;
parameter ldq_rel3_cclass_offset = ldq_rel2_cclass_offset + (57-(64-(`DC_SIZE-3))+1);
parameter ldq_rel4_cclass_offset = ldq_rel3_cclass_offset + (57-(64-(`DC_SIZE-3))+1);
parameter ldq_rel1_data_sel_offset = ldq_rel4_cclass_offset + (57-(64-(`DC_SIZE-3))+1);
parameter ldq_rel0_l2_val_offset = ldq_rel1_data_sel_offset + 1;
parameter ldq_rel1_l2_val_offset = ldq_rel0_l2_val_offset + `LMQ_ENTRIES;
parameter ldq_rel2_l2_val_offset = ldq_rel1_l2_val_offset + `LMQ_ENTRIES;
parameter ldq_rel3_l2_val_offset = ldq_rel2_l2_val_offset + `LMQ_ENTRIES;
parameter ldq_rel4_l2_val_offset = ldq_rel3_l2_val_offset + `LMQ_ENTRIES;
parameter ldq_rel5_l2_val_offset = ldq_rel4_l2_val_offset + `LMQ_ENTRIES;
parameter ldqe_rel_eccdet_offset = ldq_rel5_l2_val_offset + `LMQ_ENTRIES;
parameter ldqe_rel_eccdet_ue_offset = ldqe_rel_eccdet_offset + `LMQ_ENTRIES;
parameter ldqe_upd_gpr_ecc_offset = ldqe_rel_eccdet_ue_offset + `LMQ_ENTRIES;
parameter ldqe_upd_gpr_eccue_offset = ldqe_upd_gpr_ecc_offset + `LMQ_ENTRIES;
parameter ldqe_need_cpl_offset = ldqe_upd_gpr_eccue_offset + `LMQ_ENTRIES;
parameter ldqe_sent_cpl_offset = ldqe_need_cpl_offset + `LMQ_ENTRIES;
parameter ldq_rel1_gpr_val_offset = ldqe_sent_cpl_offset + `LMQ_ENTRIES;
parameter ldq_rel0_upd_gpr_offset = ldq_rel1_gpr_val_offset + 1;
parameter ldq_rel1_upd_gpr_offset = ldq_rel0_upd_gpr_offset + `LMQ_ENTRIES;
parameter ldq_rel2_upd_gpr_offset = ldq_rel1_upd_gpr_offset + `LMQ_ENTRIES;
parameter ldq_rel3_upd_gpr_offset = ldq_rel2_upd_gpr_offset + `LMQ_ENTRIES;
parameter ldqe_rel3_drop_cpl_rpt_offset = ldq_rel3_upd_gpr_offset + `LMQ_ENTRIES;
parameter ldq_l2_rel0_qHitBlk_offset = ldqe_rel3_drop_cpl_rpt_offset + `LMQ_ENTRIES;
parameter lgq_rel1_gpr_val_offset = ldq_l2_rel0_qHitBlk_offset + 1;
parameter lgq_rel0_upd_gpr_offset = lgq_rel1_gpr_val_offset + 1;
parameter lgq_rel1_upd_gpr_offset = lgq_rel0_upd_gpr_offset + `LGQ_ENTRIES;
parameter lgq_rel2_upd_gpr_offset = lgq_rel1_upd_gpr_offset + `LGQ_ENTRIES;
parameter lgq_rel3_upd_gpr_offset = lgq_rel2_upd_gpr_offset + `LGQ_ENTRIES;
parameter lgq_rel4_upd_gpr_offset = lgq_rel3_upd_gpr_offset + `LGQ_ENTRIES;
parameter lgq_rel5_upd_gpr_offset = lgq_rel4_upd_gpr_offset + `LGQ_ENTRIES;
parameter ldq_rel4_odq_cpl_offset = lgq_rel5_upd_gpr_offset + `LGQ_ENTRIES;
parameter ldq_rel5_odq_cpl_offset = ldq_rel4_odq_cpl_offset + `LMQ_ENTRIES;
parameter ldq_rel_qHit_clr_offset = ldq_rel5_odq_cpl_offset + `LMQ_ENTRIES;
parameter ldqe_qHit_held_offset = ldq_rel_qHit_clr_offset + `LMQ_ENTRIES;
parameter cpl_grpEntry_last_sel_offset = ldqe_qHit_held_offset + `LMQ_ENTRIES;
parameter cpl_group_last_sel_offset = cpl_grpEntry_last_sel_offset + 4 * (((`LMQ_ENTRIES + `LGQ_ENTRIES - 1)/4) + 1);
parameter lq1_iu_execute_vld_offset = cpl_group_last_sel_offset + 4;
parameter lq1_iu_itag_offset = lq1_iu_execute_vld_offset + `THREADS;
parameter lq1_iu_n_flush_offset = lq1_iu_itag_offset + `ITAG_SIZE_ENC;
parameter lq1_iu_np1_flush_offset = lq1_iu_n_flush_offset + 1;
parameter lq1_iu_exception_val_offset = lq1_iu_np1_flush_offset + 1;
parameter lq1_iu_dacrw_offset = lq1_iu_exception_val_offset + 1;
parameter lq1_iu_perf_events_offset = lq1_iu_dacrw_offset + 4;
parameter ldq_cpl_larx_offset = lq1_iu_perf_events_offset + 4;
parameter ldq_cpl_binv_offset = ldq_cpl_larx_offset + `THREADS;
parameter ldq_rel_cmmt_offset = ldq_cpl_binv_offset + `THREADS;
parameter ldq_rel_need_hole_offset = ldq_rel_cmmt_offset + 1;
parameter ldq_rel_latency_offset = ldq_rel_need_hole_offset + 1;
parameter dbg_int_en_offset = ldq_rel_latency_offset + 1;
parameter ex4_stg_act_offset = dbg_int_en_offset + `THREADS;
parameter ex5_stg_act_offset = ex4_stg_act_offset + 1;
parameter rrot_scan_offset = ex5_stg_act_offset + 1;
parameter scan_right = rrot_scan_offset + 1 - 1;
parameter [0:6] LDQ_IDLE = 7'b1000000; // Idle State, Wait for valid request
parameter [0:6] LDQ_VAL = 7'b0100000; // Valid Request, need to send request to L2
parameter [0:6] LDQ_RPEN = 7'b0010000; // Waiting for Reload
parameter [0:6] LDQ_BEATM = 7'b0001000; // Mulitple Beat Request and all have arrived
parameter [0:6] LDQ_ECC = 7'b0000100; // Check for ECC error
parameter [0:6] LDQ_DCACHE = 7'b0000010; // Reload updated L1D$ with all its beats
parameter [0:6] LDQ_CMPL = 7'b0000001; // Report ITAG completion
parameter [0:4] rot_max_size = 5'b10000;
wire tiup;
wire tidn;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
(* analysis_not_referenced="true" *)
wire unused;
//!! Bugspray Include: lq_ldq
assign tiup = 1'b1;
assign tidn = 1'b0;
assign unused = l2_lsq_resp_isComing | tidn | ldq_rel0_rot_sel_le[0] | fifo_ldq_req_wrt_ptr[8] | ldq_state_machines_idle;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// ACT Generation
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
assign ex4_stg_act_d = ctl_lsq_ex3_ldreq_val | ctl_lsq_ex3_pfetch_val;
assign ex5_stg_act_d = ex4_stg_act_q;
// EX4 Loadmiss Queue Entry Update ACT
assign ex4_ldqe_act = ldqe_wrt_ptr & {`LMQ_ENTRIES{ex4_stg_act_q}};
assign ex5_ldqe_act = ex5_ldqe_set_all_q & {`LMQ_ENTRIES{ex5_stg_act_q}};
assign ex4_lgqe_act = lgqe_wrt_ptr & {`LMQ_ENTRIES{ex4_stg_act_q}};
assign ex5_lgqe_act = ex5_lgqe_set_all_q & {`LMQ_ENTRIES{ex5_stg_act_q}};
// Reload Pipeline ACT
assign rel0_stg_act = ldq_reload_val;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// XU Config Bits
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// XUCR0[CLS] 128 Byte Cacheline Enabled
// 1 => 128 Byte Cacheline
// 0 => 64 Byte Cacheline
assign spr_xucr0_cls_d = xu_lq_spr_xucr0_cls;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// LSU Config Bits
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// LSUCR0[LGE] Load gather Enable
// 1 => load gathering enabled
// 0 => load gathering disabled
assign spr_lsucr0_lge_d = ctl_lsq_spr_lsucr0_lge;
// LSUCR0[LCA] Loadmiss Reload Attempts Count
assign spr_lsucr0_lca_d = ctl_lsq_spr_lsucr0_lca;
assign spr_lsucr0_lca_zero = ~(|(spr_lsucr0_lca_q));
assign spr_lsucr0_lca_ovrd = spr_lsucr0_lca_zero ? 3'b001 : spr_lsucr0_lca_q;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Completion Interface
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
assign iu_lq_cp_flush_d = iu_lq_cp_flush;
assign ex4_stg_flush = |(ctl_lsq_ex4_thrd_id & iu_lq_cp_flush_q);
assign ex5_stg_flush = |(ctl_lsq_ex5_thrd_id & iu_lq_cp_flush_q) | ctl_lsq_ex5_flush_req;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// ODQ->LDQ Resolved Interface
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
assign odq_ldq_n_flush_d = odq_ldq_resolved & odq_ldq_n_flush & ~ldq_cpl_odq_zap;
//odq_ldq_np1_flush_d <= odq_ldq_resolved and not odq_ldq_report_needed and odq_ldq_np1_flush;
assign odq_ldq_resolved_d = odq_ldq_resolved & (~odq_ldq_report_needed) & ~ldq_cpl_odq_zap;
assign odq_ldq_report_itag_d = odq_ldq_report_itag;
assign odq_ldq_report_tid_d = odq_ldq_report_tid;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// L2 Reload Interface
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// cTag(1) = 1 => either an IU reload or MMU reload
assign l2_rel0_resp_val_d = l2_lsq_resp_val;
assign l2_rel0_resp_ldq_val_d = ldq_relmin1_ldq_val;
assign l2_rel0_resp_cTag_d = ldq_relmin1_cTag;
assign l2_rel0_resp_qw_d = l2_lsq_resp_qw;
assign l2_rel0_resp_crit_qw_d = l2_lsq_resp_crit_qw;
assign l2_rel0_resp_l1_dump_d = l2_lsq_resp_l1_dump;
assign ldq_relmin1_ldq_val = l2_lsq_resp_val & (~l2_lsq_resp_cTag[1]);
assign ldq_relmin1_cTag = {l2_lsq_resp_cTag[0], l2_lsq_resp_cTag[2:4]};
assign ldq_rel1_data = l2_lsq_resp_data;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// LOAD QUEUE
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// RV is empty indicator
assign rv_lq_rvs_empty_d = rv_lq_rvs_empty;
// Need to block reloads
// 1) RV issued an instruction
// 2) Back-Invalidate Congruence Class collided with Valid Reload Set/Clear Congruence Class
// 3) SPR Directory Read Operation
// 4) REL1 attempt and ECC error detected for same core Tag
// Need to block reloads
// 1) RV issued an instruction with valid reload set congruence class
assign ldq_rel1_set_rviss_dir_coll = |(rv_lq_vld) & rv_lq_isLoad & ldq_rel1_set_val;
// 2) Back-Invalidate Congruence Class collided with Valid Reload Set/Clear Congruence Class
assign ldq_rel1_set_binv_dir_coll = ldq_rel1_collide_binv_q & ldq_rel1_set_val;
// 3) SPR Directory Read Operation and valid reload set congruence class
assign ldq_rel1_set_rd_dir_coll = ctl_lsq_rv1_dir_rd_val & ldq_rel1_set_val;
assign rel2_blk_req_d = ldq_rel1_set_rviss_dir_coll | ldq_rel1_set_binv_dir_coll | ldq_rel1_set_rd_dir_coll;
assign rel2_rviss_blk_d = ldq_rel1_set_rviss_dir_coll;
// EX4 Address that is used to compare against all loadmiss queue entries
assign ex4_ldreq_d = ctl_lsq_ex3_ldreq_val;
assign ex4_pfetch_val_d = ctl_lsq_ex3_pfetch_val;
assign ex4_p_addr_msk = {ctl_lsq_ex4_p_addr[64-`REAL_IFAR_WIDTH:56], (ctl_lsq_ex4_p_addr[57] | spr_xucr0_cls_q)};
assign ex5_ldreq_val_d = ctl_lsq_ex4_ldreq_val & (~(ex4_ldq_full | ctl_lsq_ex4_dReq_val | ex4_stg_flush));
assign ex5_ldreq_val = ex5_ldreq_val_q & ~ex5_stg_flush;
assign ex5_ldreq_flushed = ex5_ldreq_val_q & ex5_stg_flush;
assign ex5_pfetch_val_d = ex4_pfetch_val_q & (~(ex4_ldq_full | ctl_lsq_ex4_dReq_val));
assign ex5_pfetch_val = ex5_pfetch_val_q & ~ctl_lsq_ex5_flush_pfetch;
assign ex5_pfetch_flushed = ex5_pfetch_val_q & ctl_lsq_ex5_flush_pfetch;
assign ex5_odq_ldreq_val_d = ctl_lsq_ex4_ldreq_val & (~ex4_stg_flush);
assign ex5_streq_val_d = ctl_lsq_ex4_streq_val & (~ex4_stg_flush);
assign ex5_othreq_val_d = ctl_lsq_ex4_othreq_val & (~ex4_stg_flush);
assign ex5_p_addr_d = ctl_lsq_ex4_p_addr;
assign ex5_wimge_d = ctl_lsq_ex4_wimge;
// Performance Events that need to go to the Completion Unit
assign ex5_cmmt_events = {ctl_lsq_ex5_cmmt_events, ex5_ld_gath_q};
assign ex5_cmmt_perf_events[0] = ctl_lsq_ex5_perf_val0 & ((ctl_lsq_ex5_perf_sel0 == 4'b1111) ? ex5_cmmt_events[11] :
(ctl_lsq_ex5_perf_sel0 == 4'b1110) ? ex5_cmmt_events[10] :
(ctl_lsq_ex5_perf_sel0 == 4'b1101) ? ex5_cmmt_events[9] :
(ctl_lsq_ex5_perf_sel0 == 4'b1100) ? ex5_cmmt_events[8] :
(ctl_lsq_ex5_perf_sel0 == 4'b1011) ? ex5_cmmt_events[7] :
(ctl_lsq_ex5_perf_sel0 == 4'b1010) ? ex5_cmmt_events[6] :
(ctl_lsq_ex5_perf_sel0 == 4'b1001) ? ex5_cmmt_events[5] :
(ctl_lsq_ex5_perf_sel0 == 4'b1000) ? ex5_cmmt_events[4] :
(ctl_lsq_ex5_perf_sel0 == 4'b0111) ? ex5_cmmt_events[3] :
(ctl_lsq_ex5_perf_sel0 == 4'b0110) ? ex5_cmmt_events[2] :
(ctl_lsq_ex5_perf_sel0 == 4'b0101) ? ex5_cmmt_events[1] :
(ctl_lsq_ex5_perf_sel0 == 4'b0100) ? ex5_cmmt_events[0] :
1'b0);
assign ex5_cmmt_perf_events[1] = ctl_lsq_ex5_perf_val1 & ((ctl_lsq_ex5_perf_sel1 == 4'b1111) ? ex5_cmmt_events[11] :
(ctl_lsq_ex5_perf_sel1 == 4'b1110) ? ex5_cmmt_events[10] :
(ctl_lsq_ex5_perf_sel1 == 4'b1101) ? ex5_cmmt_events[9] :
(ctl_lsq_ex5_perf_sel1 == 4'b1100) ? ex5_cmmt_events[8] :
(ctl_lsq_ex5_perf_sel1 == 4'b1011) ? ex5_cmmt_events[7] :
(ctl_lsq_ex5_perf_sel1 == 4'b1010) ? ex5_cmmt_events[6] :
(ctl_lsq_ex5_perf_sel1 == 4'b1001) ? ex5_cmmt_events[5] :
(ctl_lsq_ex5_perf_sel1 == 4'b1000) ? ex5_cmmt_events[4] :
(ctl_lsq_ex5_perf_sel1 == 4'b0111) ? ex5_cmmt_events[3] :
(ctl_lsq_ex5_perf_sel1 == 4'b0110) ? ex5_cmmt_events[2] :
(ctl_lsq_ex5_perf_sel1 == 4'b0101) ? ex5_cmmt_events[1] :
(ctl_lsq_ex5_perf_sel1 == 4'b0100) ? ex5_cmmt_events[0] :
1'b0);
assign ex5_cmmt_perf_events[2] = ctl_lsq_ex5_perf_val2 & ((ctl_lsq_ex5_perf_sel2 == 4'b1111) ? ex5_cmmt_events[11] :
(ctl_lsq_ex5_perf_sel2 == 4'b1110) ? ex5_cmmt_events[10] :
(ctl_lsq_ex5_perf_sel2 == 4'b1101) ? ex5_cmmt_events[9] :
(ctl_lsq_ex5_perf_sel2 == 4'b1100) ? ex5_cmmt_events[8] :
(ctl_lsq_ex5_perf_sel2 == 4'b1011) ? ex5_cmmt_events[7] :
(ctl_lsq_ex5_perf_sel2 == 4'b1010) ? ex5_cmmt_events[6] :
(ctl_lsq_ex5_perf_sel2 == 4'b1001) ? ex5_cmmt_events[5] :
(ctl_lsq_ex5_perf_sel2 == 4'b1000) ? ex5_cmmt_events[4] :
(ctl_lsq_ex5_perf_sel2 == 4'b0111) ? ex5_cmmt_events[3] :
(ctl_lsq_ex5_perf_sel2 == 4'b0110) ? ex5_cmmt_events[2] :
(ctl_lsq_ex5_perf_sel2 == 4'b0101) ? ex5_cmmt_events[1] :
(ctl_lsq_ex5_perf_sel2 == 4'b0100) ? ex5_cmmt_events[0] :
1'b0);
assign ex5_cmmt_perf_events[3] = ctl_lsq_ex5_perf_val3 & ((ctl_lsq_ex5_perf_sel3 == 4'b1111) ? ex5_cmmt_events[11] :
(ctl_lsq_ex5_perf_sel3 == 4'b1110) ? ex5_cmmt_events[10] :
(ctl_lsq_ex5_perf_sel3 == 4'b1101) ? ex5_cmmt_events[9] :
(ctl_lsq_ex5_perf_sel3 == 4'b1100) ? ex5_cmmt_events[8] :
(ctl_lsq_ex5_perf_sel3 == 4'b1011) ? ex5_cmmt_events[7] :
(ctl_lsq_ex5_perf_sel3 == 4'b1010) ? ex5_cmmt_events[6] :
(ctl_lsq_ex5_perf_sel3 == 4'b1001) ? ex5_cmmt_events[5] :
(ctl_lsq_ex5_perf_sel3 == 4'b1000) ? ex5_cmmt_events[4] :
(ctl_lsq_ex5_perf_sel3 == 4'b0111) ? ex5_cmmt_events[3] :
(ctl_lsq_ex5_perf_sel3 == 4'b0110) ? ex5_cmmt_events[2] :
(ctl_lsq_ex5_perf_sel3 == 4'b0101) ? ex5_cmmt_events[1] :
(ctl_lsq_ex5_perf_sel3 == 4'b0100) ? ex5_cmmt_events[0] :
1'b0);
assign ex6_cmmt_perf_events_d = ex5_cmmt_perf_events;
// Need to Mask off bit 57 of Back-Invalidate Address depending on the Cacheline Size we are running with
assign l2_back_inv_addr_msk = l2_back_inv_addr[64 - `REAL_IFAR_WIDTH:57];
// Init Number of expected Beats
assign ldqe_beat_init = {1'b0, ((~spr_xucr0_cls_q)), 2'b00};
// LDQ Entry WRT Pointer Logic
// Look for first IDLE state machine from LOADMISSQ(0) -> LOADMISSQ(`LMQ_ENTRIES-1)
assign ldqe_wrt_ptr[0] = ldqe_available[0];
generate begin : LdPriWrt
genvar ldq;
for (ldq=1; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : LdPriWrt
assign ldqe_wrt_ptr[ldq] = &((~ldqe_available[0:ldq - 1])) & ldqe_available[ldq];
end
end
endgenerate
// Check for only 1 entry available
// Look for first IDLE state machine from LOADMISSQ(`LMQ_ENTRIES-1) -> LOADMISSQ(0)
assign ldqe_opposite_ptr[`LMQ_ENTRIES - 1] = ldqe_available[`LMQ_ENTRIES - 1];
generate begin : lastMach
genvar ldq;
for (ldq = 0; ldq <= `LMQ_ENTRIES-2; ldq=ldq+1) begin : lastMach
assign ldqe_opposite_ptr[ldq] = &((~ldqe_available[ldq + 1:`LMQ_ENTRIES - 1])) & ldqe_available[ldq];
end
end
endgenerate
assign ex4_one_machine_avail = |(ldqe_wrt_ptr & ldqe_opposite_ptr);
// Oldest Load can use state machine
assign ex4_oldest_load = (odq_ldq_oldest_ld_itag == ctl_lsq_ex4_itag) & |(odq_ldq_oldest_ld_tid & ctl_lsq_ex4_thrd_id);
assign ex4_reserved_taken = (ctl_lsq_ex4_ldreq_val | ex4_pfetch_val_q) & ex4_one_machine_avail & (~ex4_oldest_load);
assign ex5_reserved_taken_d = ex4_reserved_taken;
assign ex4_resv_taken_restart = ctl_lsq_ex4_ldreq_val & ex4_one_machine_avail & (~(ex4_oldest_load | ex4_stg_flush));
assign ex5_resv_taken_restart_d = ex4_resv_taken_restart;
// Load Queue Entry Update Control
assign ex4_ldqe_set_val = ldqe_wrt_ptr & {`LMQ_ENTRIES{((ctl_lsq_ex4_ldreq_val & (~ex4_stg_flush)) | ex4_pfetch_val_q)}};
assign ex4_ldqe_set_all = ldqe_wrt_ptr & {`LMQ_ENTRIES{(ex4_ldreq_q | ex4_pfetch_val_q)}};
assign ex5_ldqe_set_all_d = ex4_ldqe_set_all;
assign ex5_ldqe_set_val_d = ex4_ldqe_set_val;
assign ex5_ldm_entry = ex5_ldqe_set_val_q & {`LMQ_ENTRIES{(ex5_ldreq_val_q | ex5_pfetch_val_q)}};
assign ex6_ldqe_pfetch_val_d = ex5_ldqe_set_all_q & {`LMQ_ENTRIES{(ex5_pfetch_val & ~ex5_drop_req_val)}};
assign ex7_ldqe_pfetch_val_d = ex6_ldqe_pfetch_val_q;
assign ex7_pfetch_blk_val = |(ex7_ldqe_pfetch_val_q) & odq_ldq_ex7_pfetch_blk;
assign ex7_pfetch_blk_tid = ctl_lsq_ex7_thrd_id & {`THREADS{ex7_pfetch_blk_val}};
// Thread Quiesced OR reduce
always @(*) begin: tidQuiesce
reg [0:`THREADS-1] tidQ;
//(* analysis_not_referenced="true" *)
integer ldq;
tidQ = {`THREADS{1'b0}};
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin
tidQ = (ldqe_tid_inuse[ldq]) | tidQ;
end
ldq_all_req_home = ~tidQ;
end
assign lq_xu_quiesce_d = ldq_all_req_home & stq_ldq_empty & rv_lq_rvs_empty_q & ctl_lsq_pf_empty & ctl_lsq_ldp_idle;
assign lq_mm_lmq_stq_empty_d = &(ldq_all_req_home & stq_ldq_empty & rv_lq_rvs_empty_q & ctl_lsq_pf_empty & ctl_lsq_ldp_idle);
assign lq_pc_ldq_quiesce_d = ldq_all_req_home & ctl_lsq_ldp_idle;
assign lq_pc_stq_quiesce_d = stq_ldq_empty;
assign lq_pc_pfetch_quiesce_d = ctl_lsq_pf_empty;
generate begin : loadQ
genvar ldq;
for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : loadQ
wire [0:3] ldqDummy;
assign ldqDummy = ldq[3:0];
// ##############################################
// ##############################################
// LDQ ENTRY State Machine
// ##############################################
// ##############################################
assign ldqe_complete[ldq] = (ldqe_sent_cpl_q[ldq] | ldqe_kill[ldq]) & ldqe_gather_done[ldq];
always @(*) begin: ldqState
ldqe_nxt_state[ldq] = LDQ_IDLE;
ldqe_val_d[ldq] = ldqe_val_q[ldq];
ldqe_req_cmpl_d[ldq] = 1'b0;
ldqe_rst_eccdet[ldq] = 1'b0;
ldqe_cntr_reset_d[ldq] = 1'b0;
ldqe_resent_ecc_err_d[ldq] = ldqe_resent_ecc_err_q[ldq];
ldqe_ecc_err_dgpr[ldq] = 1'b0;
ldqe_reset_cpl_rpt_d[ldq] = 1'b0;
case (ldqe_state_q[ldq])
// IDLE State
LDQ_IDLE : // STATE(0)
if (ex4_ldqe_set_val[ldq] == 1'b1 & ctl_lsq_ex4_dReq_val == 1'b0) begin // Instructions going to L2
ldqe_nxt_state[ldq] = LDQ_VAL;
ldqe_val_d[ldq] = 1'b1;
ldqe_cntr_reset_d[ldq] = 1'b1;
ldqe_resent_ecc_err_d[ldq] = 1'b0;
ldqe_reset_cpl_rpt_d[ldq] = 1'b1;
end
else
begin
ldqe_nxt_state[ldq] = LDQ_IDLE;
ldqe_val_d[ldq] = 1'b0;
ldqe_cntr_reset_d[ldq] = 1'b0;
ldqe_resent_ecc_err_d[ldq] = 1'b0;
ldqe_reset_cpl_rpt_d[ldq] = 1'b1;
end
// VALID State
LDQ_VAL : // STATE(1)
if (ex4_ldqe_set_val[ldq] == 1'b1 & ctl_lsq_ex4_dReq_val == 1'b0) begin // Load Hit in the L1D$ and back-to-back load wants to use same entry
ldqe_nxt_state[ldq] = LDQ_VAL;
ldqe_val_d[ldq] = 1'b1;
end
else if (ldqe_zap[ldq] == 1'b1 & ldqe_sent[ldq] == 1'b0) begin // Entry Zap and havent Sent
ldqe_nxt_state[ldq] = LDQ_IDLE;
ldqe_req_cmpl_d[ldq] = 1'b1;
ldqe_val_d[ldq] = 1'b0;
end
else if (ldqe_sent[ldq] == 1'b1) begin // Request sent to L2
ldqe_nxt_state[ldq] = LDQ_RPEN;
ldqe_val_d[ldq] = 1'b0;
end
else
ldqe_nxt_state[ldq] = LDQ_VAL;
// RELOAD PENDING State
LDQ_RPEN : // STATE(2)
if (ldqe_wimge_q[ldq][1] == 1'b1 & ldq_relmin1_l2_val[ldq] == 1'b1) // Cache-Inhibited Reload
ldqe_nxt_state[ldq] = LDQ_ECC;
else if (ldqe_wimge_q[ldq][1] == 1'b0 & ldq_relmin1_l2_val[ldq] == 1'b1) // Cacheable Reload Beat0 Received
ldqe_nxt_state[ldq] = LDQ_BEATM;
else
ldqe_nxt_state[ldq] = LDQ_RPEN;
// RELOAD MULTIPLE BEATS State
LDQ_BEATM : // STATE(3)
if (ldq_rel1_beats_home[ldq] == 1'b1 & ldq_rel1_l2_val_q[ldq] == 1'b1)
ldqe_nxt_state[ldq] = LDQ_ECC;
else
ldqe_nxt_state[ldq] = LDQ_BEATM;
// RELOAD CHECK ECC State
LDQ_ECC : // STATE(4)
if (ldq_rel2_l2_val_q[ldq] == 1'b1 & ldqe_rel_eccdet[ldq] == 1'b1) begin // Correctable ECC Error detected on any Beats
ldqe_nxt_state[ldq] = LDQ_RPEN;
ldqe_rst_eccdet[ldq] = 1'b1;
ldqe_cntr_reset_d[ldq] = 1'b1;
ldqe_resent_ecc_err_d[ldq] = 1'b1;
ldqe_ecc_err_dgpr[ldq] = 1'b1;
end
else if (ldq_rel2_l2_val_q[ldq] == 1'b1) // Uncorrectable or Reload Complete
ldqe_nxt_state[ldq] = LDQ_DCACHE;
else
ldqe_nxt_state[ldq] = LDQ_ECC;
// RELOAD UPDATE CACHE State
LDQ_DCACHE : // STATE(5)
if (ldq_rel6_req_done_q[ldq] == 1'b1) begin // Data Cache and Directory has been updated
if (ldqe_complete[ldq] == 1'b1) begin // Entry was Machine Killed or Already sent completion report
ldqe_nxt_state[ldq] = LDQ_IDLE;
ldqe_reset_cpl_rpt_d[ldq] = 1'b1;
ldqe_resent_ecc_err_d[ldq] = 1'b0;
ldqe_req_cmpl_d[ldq] = 1'b1;
ldqe_rst_eccdet[ldq] = 1'b1; // Reset ECC Error Indicator
end
else
// Entry has not been Machine Killed
ldqe_nxt_state[ldq] = LDQ_CMPL;
end
else
ldqe_nxt_state[ldq] = LDQ_DCACHE;
// COMPLETION REPORT
LDQ_CMPL : // STATE(6)
if (ldqe_complete[ldq] == 1'b1) begin // Entry was Machine Killed or Completion report returned
ldqe_nxt_state[ldq] = LDQ_IDLE;
ldqe_reset_cpl_rpt_d[ldq] = 1'b1;
ldqe_resent_ecc_err_d[ldq] = 1'b0;
ldqe_req_cmpl_d[ldq] = 1'b1;
ldqe_rst_eccdet[ldq] = 1'b1; // Reset ECC Error Indicator
end
else
ldqe_nxt_state[ldq] = LDQ_CMPL;
default :
begin
ldqe_nxt_state[ldq] = LDQ_IDLE;
ldqe_val_d[ldq] = ldqe_val_q[ldq];
ldqe_req_cmpl_d[ldq] = 1'b0;
ldqe_rst_eccdet[ldq] = 1'b0;
ldqe_cntr_reset_d[ldq] = 1'b0;
ldqe_resent_ecc_err_d[ldq] = ldqe_resent_ecc_err_q[ldq];
ldqe_ecc_err_dgpr[ldq] = 1'b0;
ldqe_reset_cpl_rpt_d[ldq] = 1'b0;
end
endcase
end
assign ldqe_state_d[ldq] = ldqe_nxt_state[ldq];
assign ldqe_rst_eccdet_d[ldq] = ldqe_rst_eccdet[ldq];
// ##############################################
// Load Queue Contents
// Drop Reload
assign ldqe_dRel_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_drop_rel : ldqe_dRel_q[ldq];
// Instructions ITAG
assign ldqe_itag_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_itag : ldqe_itag_q[ldq];
// Request Physical Address Bits
assign ldqe_p_addr_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_p_addr : ldqe_p_addr_q[ldq];
// WIMGE Bits
assign ldqe_wimge_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_wimge : ldqe_wimge_q[ldq];
assign ldqe_wimge_i[ldq] = ldqe_wimge_q[ldq][1];
assign ldqe_wimge_g[ldq] = ldqe_wimge_q[ldq][3];
// Byte Swap Bits
assign ldqe_byte_swap_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_byte_swap : ldqe_byte_swap_q[ldq];
// LARX Bits
assign ldqe_resv_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_is_resv : ldqe_resv_q[ldq];
// PreFetch Valid Bits
assign ldqe_pfetch_d[ldq] = ex4_ldqe_set_all[ldq] ? ex4_pfetch_val_q : ldqe_pfetch_q[ldq];
// `THREADS Bits
assign ldqe_thrd_id_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_thrd_id : ldqe_thrd_id_q[ldq];
// lock_set Bits
assign ldqe_lock_set_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_lock_set : ldqe_lock_set_q[ldq];
// watch_set Bits
assign ldqe_watch_set_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_watch_set : ldqe_watch_set_q[ldq];
// op_size Bits
assign ldqe_op_size_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_opsize : ldqe_op_size_q[ldq];
// tgpr Bits
assign ldqe_tgpr_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_tgpr : ldqe_tgpr_q[ldq];
// axu Bits
assign ldqe_axu_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_axu_val : ldqe_axu_q[ldq];
// usr_def Bits
assign ldqe_usr_def_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_usr_def : ldqe_usr_def_q[ldq];
// algebraic Bits
assign ldqe_algebraic_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_algebraic : ldqe_algebraic_q[ldq];
// class_id Bits
assign ldqe_class_id_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_class_id : ldqe_class_id_q[ldq];
// performance events
assign ldqe_perf_events_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ex5_cmmt_perf_events : ldqe_perf_events_q[ldq];
// GPR Update is done
// ldqe_set_gpr_done = "11" => This should never occur, will need bugspray here
assign ldqe_set_gpr_done[ldq] = {ex5_ldqe_set_all_q[ldq], ldq_rel2_upd_gpr_q[ldq]};
// DVC Bits
assign ldqe_dvc_d[ldq] = (ldqe_set_gpr_done[ldq] == 2'b01) ? ldq_rel2_dvc :
(ldqe_set_gpr_done[ldq] == 2'b00) ? ldqe_dvc_q[ldq] :
ctl_lsq_ex5_dvc;
// ttype Bits
assign ldqe_ttype_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_ttype : ldqe_ttype_q[ldq];
// DAC Status Bits
assign ldqe_dacrw_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_dacrw : ldqe_dacrw_q[ldq];
// Load Request was restarted due to load-hit-load
assign ldqe_qHit_held_sel[ldq] = {ex4_load_qHit_upd[ldq], ldq_rel2_qHit_clr[ldq]};
assign ldqe_qHit_held_d[ldq] = (ldqe_qHit_held_sel[ldq] == 2'b00) ? ldqe_qHit_held_q[ldq] :
(ldqe_qHit_held_sel[ldq] == 2'b10) ? 1'b1 :
1'b0;
// ##############################################
// ##############################################
// ##############################################
// LDQ Control
// ##############################################
// ##############################################
// Request Hit Detect Logic
// Detecting QHits for loads hitting against other loadmisses, used for the entry snoop detection
assign ldqe_p_addr_msk[ldq] = {ldqe_p_addr_q[ldq][64 - `REAL_IFAR_WIDTH:56], (ldqe_p_addr_q[ldq][57] | spr_xucr0_cls_q)};
assign ex4_addr_m_queue[ldq] = (ldqe_p_addr_msk[ldq] == ex4_p_addr_msk);
assign ex4_qw_hit_queue[ldq] = ~spr_xucr0_cls_q ? (ldqe_p_addr_q[ldq][58:59] == ctl_lsq_ex4_p_addr[58:59]) :
(ldqe_p_addr_q[ldq][57:59] == ctl_lsq_ex4_p_addr[57:59]);
assign ex4_thrd_id_m[ldq] = |(ldqe_thrd_id_q[ldq] & ctl_lsq_ex4_thrd_id);
assign ex4_larx_hit[ldq] = ex4_thrd_id_m[ldq] & ldqe_resv_q[ldq];
assign ex4_guarded_hit[ldq] = ex4_thrd_id_m[ldq] & ldqe_wimge_g[ldq] & ctl_lsq_ex4_wimge[3];
assign ex4_req_hit_ldq[ldq] = ex4_larx_hit[ldq] | ex4_guarded_hit[ldq] | ex4_addr_m_queue[ldq];
// Want to only gather from request that hasnt been sent to the L2 only if the thread matches, if the thread doesnt match,
// the request in ldm queue may get flushed and the gathered request will still be valid which causes the gathered request
// to match on an invalid reload.
// It is not thread dependent if the request has already been sent to the L2, we are guaranteed to get data back if the request in ldm queue
// is flushed.
assign ldqe_entry_gatherable[ldq] = ((ldqe_state_q[ldq][1] & ex4_thrd_id_m[ldq] & (~ex5_inv_ldqe[ldq])) | ldqe_state_q[ldq][2]) &
(~(ldq_relmin1_l2_val[ldq] | ldqe_wimge_q[ldq][1] | ldqe_resv_q[ldq]));
assign ex4_entry_gatherable[ldq] = ex4_addr_m_queue[ldq] & ctl_lsq_ex4_gath_load & spr_lsucr0_lge_q & ~ex4_qw_hit_queue[ldq];
assign ex4_entry_gath_ld[ldq] = ex4_entry_gatherable[ldq] & ldqe_entry_gatherable[ldq] & ld_gath_not_full & ~ex4_lgq_qw_hit[ldq];
// Performance Events
assign ex4_entry_gath_full[ldq] = ex4_entry_gatherable[ldq] & ldqe_entry_gatherable[ldq] & ~ld_gath_not_full;
assign ex4_entry_gath_qwhit[ldq] = ex4_entry_gatherable[ldq] & ldqe_entry_gatherable[ldq] & ld_gath_not_full & ex4_lgq_qw_hit[ldq];
// THIS STATEMENT CHANGES WHEN THE LDQ DOESNT HOLD UNRESOLVED ITAGS WHEN THE RELOAD IS COMPLETE
// WILL HAVE TO CHANGE LDQE_STATE_Q(LDQ)(2 TO 6)
// ldqe_inuse(ldq) = (ldqe_state_q(ldq)(1) and not ex5_inv_ldqe(ldq)) or or_reduce(ldqe_state_q(ldq)(2 to 5));
assign ldqe_inuse[ldq] = (ldqe_state_q[ldq][1] & (~ex5_inv_ldqe[ldq])) | |(ldqe_state_q[ldq][2:6]);
assign ldqe_tid_inuse[ldq] = (ldqe_thrd_id_q[ldq] & {`THREADS{ldqe_inuse[ldq]}});
assign ldqe_req_outstanding[ldq] = (ldqe_state_q[ldq][1] & (~ex5_inv_ldqe[ldq])) | |(ldqe_state_q[ldq][2:5]);
assign ldqe_tid_req_outstanding[ldq] = ldqe_thrd_id_q[ldq] & {`THREADS{ldqe_req_outstanding[ldq]}};
assign ldqe_req_able_to_hold[ldq] = (ldqe_state_q[ldq][1] & ex4_thrd_id_m[ldq] & (~ex5_inv_ldqe[ldq])) | |(ldqe_state_q[ldq][2:5]);
assign ex4_entry_load_qHit[ldq] = ldqe_req_outstanding[ldq] & ex4_req_hit_ldq[ldq] & (ctl_lsq_ex4_ldreq_val | ex4_pfetch_val_q) & (~ctl_lsq_ex4_dReq_val);
// Detect when to update qHit_held and when to report SET_HOLD to RV for a particular itag
assign ldqe_rel_blk_qHit_held[ldq] = ldq_rel2_qHit_clr[ldq] | ldq_rel_qHit_clr_q[ldq] | ex4_entry_gath_ld[ldq];
assign ex4_load_qHit_upd[ldq] = ldqe_req_able_to_hold[ldq] & ex4_req_hit_ldq[ldq] & (~ldqe_rel_blk_qHit_held[ldq]) & ctl_lsq_ex4_ldreq_val & (~ctl_lsq_ex4_dReq_val);
// Store Request Hit against outstanding Loadmiss Request
// It shouldnt matter if the outstanding load was zapped, the sync still needs to wait for the reload to complete if the request was sent out
// this is the case where a load went out, took forever to come back, got zapped while waiting for reload, sync came down the pipe,
// sync cant go out until reload is back, dci needs to look at all threads with outstanding requests, dci needs to wait until they are all back
assign ex5_ldm_hit_d[ldq] = ctl_lsq_ex4_streq_val & ldqe_req_outstanding[ldq] & (ex4_req_hit_ldq[ldq] | (ex4_thrd_id_m[ldq] & ctl_lsq_ex4_is_sync) | ctl_lsq_ex4_all_thrd_chk);
// Entry Was Back-Invalidated
assign ldqe_back_inv[ldq] = (ldqe_p_addr_msk[ldq] == l2_back_inv_addr_msk) & ldqe_inuse[ldq] & l2_back_inv_val;
assign ldqe_back_inv_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_back_inv[ldq]} == 2'b00) ? ldqe_back_inv_q[ldq] :
({ex4_ldqe_set_all[ldq], ldqe_back_inv[ldq]} == 2'b01) ? 1'b1 :
1'b0;
// Determine if this entry was for the CP_NEXT itag
begin : ldqeItagTid
genvar tid;
for (tid=0; tid<`THREADS; tid=tid+1) begin : ldqeItagTid
assign ldqe_cpNext_tid[ldq][tid] = ldqe_thrd_id_q[ldq][tid] & (ldqe_itag_q[ldq] == iu_lq_cp_next_itag_q[tid]);
end
end
assign ldqe_cpNext_val[ldq] = |(ldqe_cpNext_tid[ldq]);
// Want to Flush if the loadqueue was back-invalidated or the L1 Dump signal is on for the reload
assign ldqe_back_inv_flush_upd[ldq] = ldqe_back_inv[ldq] | ldq_rel_l1_dump[ldq];
// NEED TO REVISIT THIS STATEMENT, I BELIEVE THIS SCENARIO ONLY EXISTS IF THE LDQ HOLDS UNRESOLVED ITAGS WHEN THE RELOAD IS COMPLETE
// Want to only capture the first back-invalidate
// There is a hole where it was a cp_next itag when the back-invalidate hit
// then an older loadmiss went to the L2, got newer data
// another back-invalidate comes in and sets the cpnext_val indicator causing an NP1 flush
// when we really wanted an N flush
assign ldqe_back_inv_nFlush_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b00) ? ldqe_back_inv_nFlush_q[ldq] :
({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b01) ? (ldqe_back_inv_nFlush_q[ldq] | ((~ldqe_cpNext_val[ldq]))) :
1'b0;
assign ldqe_back_inv_np1Flush_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b00) ? ldqe_back_inv_np1Flush_q[ldq] :
({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b01) ? (ldqe_back_inv_np1Flush_q[ldq] | ldqe_cpNext_val[ldq]) :
1'b0;
// Load Request access to L2 Available
assign ldqe_need_l2send[ldq] = ldqe_val_q[ldq] & (~ex5_ldqe_set_all_q[ldq]);
// Load Entry Sent to L2
assign ldqe_sent[ldq] = ((fifo_ldq_req0_avail & fifo_ldq_req_q[0][ldq]) | // Sent from FIFO
((ex5_ldreq_val | ex5_pfetch_val) & ex5_ldqe_set_all_q[ldq] &
(~(ex5_drop_req_val | ldq_l2_req_need_send)))) & // Sent from Pipe
arb_ldq_ldq_unit_sel;
// entry needs to be invalidated
// 1) Load was a Load Hit in the L1D$
// 2) There was only 1 state machine and non oldest load took it
assign ex5_inv_ldqe[ldq] = ex5_ldqe_set_all_q[ldq] & (ex5_drop_req_val | ex5_ldreq_flushed | ex5_pfetch_flushed);
// Determine if Entry should be Flushed
// CP Flush
assign ldqe_cp_flush[ldq] = |(iu_lq_cp_flush_q & ldqe_thrd_id_q[ldq]) & ~ldqe_pfetch_q[ldq];
// OrderQ Flush
assign ldqe_odq_flush[ldq] = (odq_ldq_report_itag_q == ldqe_itag_q[ldq]) & |(odq_ldq_report_tid_q & ldqe_thrd_id_q[ldq]) & odq_ldq_n_flush_q;
// OrderQ Prefetch Block due to the prefetch would have caused an NFlush of user code
assign ldqe_pfetch_flush[ldq] = ex7_ldqe_pfetch_val_q[ldq] & odq_ldq_ex7_pfetch_blk;
assign ldqe_flush[ldq] = (ldqe_cp_flush[ldq] | ldqe_odq_flush[ldq] | ldqe_pfetch_flush[ldq]) & (~ldqe_state_q[ldq][0]);
// Entry is Deleted when the entry is flushed or when we determine the entry was a load hit
assign ldqe_mkill[ldq] = ldqe_flush[ldq];
assign ldqe_kill[ldq] = ldqe_mkill[ldq] | ldqe_mkill_q[ldq];
assign ldqe_zap[ldq] = ldqe_mkill[ldq] | ex5_inv_ldqe[ldq];
// Load Request got Machine Killed
assign ldqe_mkill_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_mkill[ldq]} == 2'b00) ? ldqe_mkill_q[ldq] :
({ex4_ldqe_set_all[ldq], ldqe_mkill[ldq]} == 2'b01) ? 1'b1 :
1'b0;
// Load Entry Has Resolved In Order Queue
assign ldqe_resolved[ldq] = (ldqe_itag_q[ldq] == odq_ldq_report_itag_q) & |(odq_ldq_report_tid_q & ldqe_thrd_id_q[ldq]) & odq_ldq_resolved_q & (~ldqe_state_q[ldq][0]);
assign ldqe_resolved_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_resolved[ldq]} == 2'b00) ? ldqe_resolved_q[ldq] :
({ex4_ldqe_set_all[ldq], ldqe_resolved[ldq]} == 2'b01) ? 1'b1 :
1'b0;
// ##############################################
// ##############################################
// LDQ Reload Control
// ##############################################
// ##############################################
// Reload for Entry is valid
assign ldqe_ctrl_act[ldq] = ~ldqe_state_q[ldq][0];
assign ldqe_rel_inprog[ldq] = |(ldqe_state_q[ldq][2:3]);
assign ldqe_rel0_cTag[ldq] = (ldqDummy == ldq_resp_cTag);
assign ldqe_rel1_cTag[ldq] = (ldqDummy == ldq_rel1_cTag_q);
assign ldqe_relmin1_cTag[ldq] = (ldqDummy == ldq_relmin1_cTag);
assign ldq_relmin1_l2_val[ldq] = ldq_relmin1_ldq_val & ldqe_relmin1_cTag[ldq] & ldqe_rel_inprog[ldq];
assign ldq_rel0_l2_val_d[ldq] = ldq_relmin1_l2_val[ldq];
assign ldq_relmin1_l2_inval[ldq] = ldq_relmin1_ldq_val & ldqe_relmin1_cTag[ldq] & (~ldqe_rel_inprog[ldq]);
assign ldq_rel_l1_dump[ldq] = ldq_rel0_l2_val_q[ldq] & l2_rel0_resp_l1_dump_q;
assign ldq_rel0_arb_sent[ldq] = ldq_rel0_arb_val & ldqe_rel0_cTag[ldq];
assign ldq_rel_l2_l1dumpBlk[