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10362 lines
678 KiB
Verilog

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
`timescale 1 ns / 1 ns
//******************************************************************************
//* TITLE: Data Side Effective to Real Address Translation
//* NAME: lq_derat.vhdl
//******************************************************************************
`include "tri_a2o.vh"
module lq_derat(
gnd,
vdd,
vcs,
clk,
rst,
pc_xu_init_reset,
pc_xu_ccflush_dc,
tc_scan_dis_dc_b,
tc_scan_diag_dc,
tc_lbist_en_dc,
an_ac_atpg_en_dc,
an_ac_grffence_en_dc,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_act_dis_dc,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
pc_func_sl_thold_2,
pc_func_slp_sl_thold_2,
pc_func_slp_nsl_thold_2,
pc_cfg_slp_sl_thold_2,
pc_regf_slp_sl_thold_2,
pc_time_sl_thold_2,
pc_sg_2,
pc_fce_2,
cam_clkoff_dc_b,
cam_act_dis_dc,
cam_d_mode_dc,
cam_delay_lclkr_dc,
cam_mpw1_dc_b,
cam_mpw2_dc_b,
ac_func_scan_in,
ac_func_scan_out,
ac_ccfg_scan_in,
ac_ccfg_scan_out,
time_scan_in,
time_scan_out,
regf_scan_in,
regf_scan_out,
dec_derat_ex1_derat_act,
dec_derat_ex0_val,
dec_derat_ex0_is_extload,
dec_derat_ex0_is_extstore,
dec_derat_ex1_itag,
dec_derat_ex1_pfetch_val,
dec_derat_ex1_is_load,
dec_derat_ex1_is_store,
dec_derat_ex1_is_touch,
dec_derat_ex1_icbtls_instr,
dec_derat_ex1_icblc_instr,
dec_derat_ex1_ra_eq_ea,
dec_derat_ex1_byte_rev,
byp_derat_ex2_req_aborted,
dcc_derat_ex3_strg_noop,
dcc_derat_ex5_blk_tlb_req,
dcc_derat_ex6_cplt,
dcc_derat_ex6_cplt_itag,
dir_derat_ex2_epn_arr,
dir_derat_ex2_epn_nonarr,
iu_lq_recirc_val,
iu_lq_cp_next_itag,
lsq_ctl_oldest_tid,
lsq_ctl_oldest_itag,
derat_dcc_ex4_restart,
derat_dcc_ex4_setHold,
derat_dcc_clr_hold,
derat_dcc_emq_idle,
xu_lq_act,
xu_lq_val,
xu_lq_is_eratre,
xu_lq_is_eratwe,
xu_lq_is_eratsx,
xu_lq_is_eratilx,
xu_lq_ws,
xu_lq_ra_entry,
xu_lq_rs_data,
lq_xu_ex5_data,
lq_xu_ord_par_err,
lq_xu_ord_read_done,
lq_xu_ord_write_done,
iu_lq_isync,
iu_lq_csync,
mm_derat_rel_val,
mm_derat_rel_data,
mm_derat_rel_emq,
mm_lq_itag,
mm_lq_tlb_miss,
mm_lq_tlb_inelig,
mm_lq_pt_fault,
mm_lq_lrat_miss,
mm_lq_tlb_multihit,
mm_lq_tlb_par_err,
mm_lq_lru_par_err,
lsq_ctl_rv0_binv_val,
mm_lq_snoop_coming,
mm_lq_snoop_val,
mm_lq_snoop_attr,
mm_lq_snoop_vpn,
lq_mm_snoop_ack,
derat_dec_rv1_snoop_addr,
derat_rv1_snoop_val,
iu_lq_cp_flush,
derat_dec_hole_all,
derat_dcc_ex3_e,
derat_dcc_ex3_itagHit,
derat_dcc_ex4_rpn,
derat_dcc_ex4_wimge,
derat_dcc_ex4_u,
derat_dcc_ex4_wlc,
derat_dcc_ex4_attr,
derat_dcc_ex4_vf,
derat_dcc_ex4_miss,
derat_dcc_ex4_tlb_err,
derat_dcc_ex4_dsi,
derat_dcc_ex4_par_err_flush,
derat_dcc_ex4_multihit_err_flush,
derat_dcc_ex4_par_err_det,
derat_dcc_ex4_multihit_err_det,
derat_dcc_ex4_noop_touch,
derat_dcc_ex4_tlb_inelig,
derat_dcc_ex4_pt_fault,
derat_dcc_ex4_lrat_miss,
derat_dcc_ex4_tlb_multihit,
derat_dcc_ex4_tlb_par_err,
derat_dcc_ex4_lru_par_err,
derat_fir_par_err,
derat_fir_multihit,
lq_mm_req,
lq_mm_req_nonspec,
lq_mm_req_itag,
lq_mm_req_epn,
lq_mm_thdid,
lq_mm_req_emq,
lq_mm_ttype,
lq_mm_state,
lq_mm_lpid,
lq_mm_tid,
lq_mm_perf_dtlb,
lq_mm_mmucr0_we,
lq_mm_mmucr0,
lq_mm_mmucr1_we,
lq_mm_mmucr1,
spr_xucr0_clkg_ctl_b1,
xu_lq_spr_msr_hv,
xu_lq_spr_msr_pr,
xu_lq_spr_msr_ds,
xu_lq_spr_msr_cm,
xu_lq_spr_ccr2_notlb,
xu_lq_spr_ccr2_dfrat,
xu_lq_spr_ccr2_dfratsc,
xu_lq_spr_xucr4_mmu_mchk,
spr_derat_eplc_wr,
spr_derat_eplc_epr,
spr_derat_eplc_eas,
spr_derat_eplc_egs,
spr_derat_eplc_elpid,
spr_derat_eplc_epid,
spr_derat_epsc_wr,
spr_derat_epsc_epr,
spr_derat_epsc_eas,
spr_derat_epsc_egs,
spr_derat_epsc_elpid,
spr_derat_epsc_epid,
mm_lq_pid,
mm_lq_mmucr0,
mm_lq_mmucr1,
derat_xu_debug_group0,
derat_xu_debug_group1,
derat_xu_debug_group2,
derat_xu_debug_group3
);
inout gnd;
inout vdd;
inout vcs;
input clk;
input rst;
input pc_xu_init_reset;
input pc_xu_ccflush_dc;
input tc_scan_dis_dc_b;
input tc_scan_diag_dc;
input tc_lbist_en_dc;
input an_ac_atpg_en_dc;
input an_ac_grffence_en_dc;
input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input lcb_act_dis_dc;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;
input pc_func_sl_thold_2;
input pc_func_slp_sl_thold_2;
input pc_func_slp_nsl_thold_2;
input pc_cfg_slp_sl_thold_2;
input pc_regf_slp_sl_thold_2;
input pc_time_sl_thold_2;
input pc_sg_2;
input pc_fce_2;
input cam_clkoff_dc_b;
input cam_act_dis_dc;
input cam_d_mode_dc;
input [0:4] cam_delay_lclkr_dc;
input [0:4] cam_mpw1_dc_b;
input cam_mpw2_dc_b;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input [0:1] ac_func_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output [0:1] ac_func_scan_out;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input ac_ccfg_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output ac_ccfg_scan_out;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input time_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output time_scan_out;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input [0:6] regf_scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output [0:6] regf_scan_out;
input dec_derat_ex1_derat_act;
input [0:`THREADS-1] dec_derat_ex0_val;
input dec_derat_ex0_is_extload;
input dec_derat_ex0_is_extstore;
input [0:`ITAG_SIZE_ENC-1] dec_derat_ex1_itag;
input [0:`THREADS-1] dec_derat_ex1_pfetch_val;
input dec_derat_ex1_is_load;
input dec_derat_ex1_is_store;
input dec_derat_ex1_is_touch;
input dec_derat_ex1_icbtls_instr;
input dec_derat_ex1_icblc_instr;
input dec_derat_ex1_ra_eq_ea;
input dec_derat_ex1_byte_rev;
input byp_derat_ex2_req_aborted;
input dcc_derat_ex3_strg_noop;
input dcc_derat_ex5_blk_tlb_req;
input [0:`THREADS-1] dcc_derat_ex6_cplt;
input [0:`ITAG_SIZE_ENC-1] dcc_derat_ex6_cplt_itag;
input [64-(2**`GPR_WIDTH_ENC):51] dir_derat_ex2_epn_arr;
input [64-(2**`GPR_WIDTH_ENC):51] dir_derat_ex2_epn_nonarr;
input [0:`THREADS-1] iu_lq_recirc_val;
input [0:(`THREADS*`ITAG_SIZE_ENC)-1] iu_lq_cp_next_itag;
input [0:`THREADS-1] lsq_ctl_oldest_tid;
input [0:`ITAG_SIZE_ENC-1] lsq_ctl_oldest_itag;
output derat_dcc_ex4_restart;
output derat_dcc_ex4_setHold;
output [0:`THREADS-1] derat_dcc_clr_hold;
output [0:`THREADS-1] derat_dcc_emq_idle;
input xu_lq_act;
input [0:`THREADS-1] xu_lq_val;
input xu_lq_is_eratre;
input xu_lq_is_eratwe;
input xu_lq_is_eratsx;
input xu_lq_is_eratilx;
input [0:1] xu_lq_ws;
input [0:4] xu_lq_ra_entry;
input [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data;
output [64-(2**`GPR_WIDTH_ENC):63] lq_xu_ex5_data;
output lq_xu_ord_par_err;
output lq_xu_ord_read_done;
output lq_xu_ord_write_done;
input iu_lq_isync;
input iu_lq_csync;
input [0:4] mm_derat_rel_val;
input [0:131] mm_derat_rel_data;
input [0:`EMQ_ENTRIES-1] mm_derat_rel_emq;
input [0:`ITAG_SIZE_ENC-1] mm_lq_itag;
input [0:`THREADS-1] mm_lq_tlb_miss;
input [0:`THREADS-1] mm_lq_tlb_inelig;
input [0:`THREADS-1] mm_lq_pt_fault;
input [0:`THREADS-1] mm_lq_lrat_miss;
input [0:`THREADS-1] mm_lq_tlb_multihit;
input [0:`THREADS-1] mm_lq_tlb_par_err;
input [0:`THREADS-1] mm_lq_lru_par_err;
input lsq_ctl_rv0_binv_val;
input mm_lq_snoop_coming;
input mm_lq_snoop_val;
input [0:25] mm_lq_snoop_attr;
input [0:51] mm_lq_snoop_vpn;
output lq_mm_snoop_ack;
output [0:51] derat_dec_rv1_snoop_addr;
output derat_rv1_snoop_val;
input [0:`THREADS-1] iu_lq_cp_flush;
output derat_dec_hole_all;
output derat_dcc_ex3_e;
output derat_dcc_ex3_itagHit;
output [22:51] derat_dcc_ex4_rpn;
output [0:4] derat_dcc_ex4_wimge;
output [0:3] derat_dcc_ex4_u;
output [0:1] derat_dcc_ex4_wlc;
output [0:5] derat_dcc_ex4_attr;
output derat_dcc_ex4_vf;
output derat_dcc_ex4_miss;
output derat_dcc_ex4_tlb_err;
output derat_dcc_ex4_dsi;
output derat_dcc_ex4_par_err_flush;
output derat_dcc_ex4_multihit_err_flush;
output derat_dcc_ex4_par_err_det;
output derat_dcc_ex4_multihit_err_det;
output derat_dcc_ex4_noop_touch;
output derat_dcc_ex4_tlb_inelig;
output derat_dcc_ex4_pt_fault;
output derat_dcc_ex4_lrat_miss;
output derat_dcc_ex4_tlb_multihit;
output derat_dcc_ex4_tlb_par_err;
output derat_dcc_ex4_lru_par_err;
output derat_fir_par_err;
output derat_fir_multihit;
output lq_mm_req;
output lq_mm_req_nonspec;
output [0:`ITAG_SIZE_ENC-1] lq_mm_req_itag;
output [64-(2**`GPR_WIDTH_ENC):51] lq_mm_req_epn;
output [0:`THREADS-1] lq_mm_thdid;
output [0:`EMQ_ENTRIES-1] lq_mm_req_emq;
output [0:1] lq_mm_ttype;
output [0:3] lq_mm_state;
output [0:7] lq_mm_lpid;
output [0:13] lq_mm_tid;
output [0:`THREADS-1] lq_mm_mmucr0_we;
output [0:17] lq_mm_mmucr0;
output [0:`THREADS-1] lq_mm_mmucr1_we;
output [0:4] lq_mm_mmucr1;
output [0:`THREADS-1] lq_mm_perf_dtlb;
input spr_xucr0_clkg_ctl_b1;
input [0:`THREADS-1] xu_lq_spr_msr_hv;
input [0:`THREADS-1] xu_lq_spr_msr_pr;
input [0:`THREADS-1] xu_lq_spr_msr_ds;
input [0:`THREADS-1] xu_lq_spr_msr_cm;
input xu_lq_spr_ccr2_notlb;
input xu_lq_spr_ccr2_dfrat;
input [0:8] xu_lq_spr_ccr2_dfratsc;
input xu_lq_spr_xucr4_mmu_mchk;
input [0:`THREADS-1] spr_derat_eplc_wr;
input [0:`THREADS-1] spr_derat_eplc_epr;
input [0:`THREADS-1] spr_derat_eplc_eas;
input [0:`THREADS-1] spr_derat_eplc_egs;
input [0:(8*`THREADS)-1] spr_derat_eplc_elpid;
input [0:(14*`THREADS)-1] spr_derat_eplc_epid;
input [0:`THREADS-1] spr_derat_epsc_wr;
input [0:`THREADS-1] spr_derat_epsc_epr;
input [0:`THREADS-1] spr_derat_epsc_eas;
input [0:`THREADS-1] spr_derat_epsc_egs;
input [0:(8*`THREADS)-1] spr_derat_epsc_elpid;
input [0:(14*`THREADS)-1] spr_derat_epsc_epid;
input [0:(`THREADS*14)-1] mm_lq_pid;
input [0:(`THREADS*20)-1] mm_lq_mmucr0;
input [0:9] mm_lq_mmucr1;
output [0:87] derat_xu_debug_group0;
output [0:87] derat_xu_debug_group1;
output [0:87] derat_xu_debug_group2;
output [0:87] derat_xu_debug_group3;
//@@ Signal Declarations
wire [1:19] CAM_MASK_BITS_PT;
wire [1:31] EX3_FIRST_HIT_ENTRY_PT;
wire [1:32] EX3_MULTIHIT_B_PT;
wire [1:32] LRU_RMT_VEC_D_PT;
wire [1:161] LRU_SET_RESET_VEC_PT;
wire [1:31] LRU_WAY_ENCODE_PT;
//--------------------------
// components
//--------------------------
//--------------------------
// constants
//--------------------------
parameter GPR_WIDTH = 2 ** `GPR_WIDTH_ENC;
parameter [0:2] EMQ_IDLE = 3'b100;
parameter [0:2] EMQ_RPEN = 3'b010;
parameter [0:2] EMQ_REXCP = 3'b001;
// Field/Signal sizes
parameter ttype_width = 12;
parameter state_width = 4;
parameter lpid_width = 8;
parameter pid_width = 14;
parameter pid_width_erat = 8;
parameter extclass_width = 2;
parameter tlbsel_width = 2;
parameter epn_width = 52;
parameter vpn_width = 61;
parameter rpn_width = 30;
parameter ws_width = 2;
parameter rs_is_width = 9;
parameter error_width = 3;
parameter cam_data_width = 84;
parameter array_data_width = 68;
parameter num_entry = 32;
parameter num_entry_log2 = 5;
parameter por_seq_width = 3;
parameter watermark_width = 5;
parameter eptr_width = 5;
parameter lru_width = 31;
parameter bcfg_width = 123;
parameter ex3_epn_width = 30;
// Generate flags
parameter check_parity = 1;
parameter MMU_Mode_Value = 1'b0;
parameter [0:1] TlbSel_Tlb = 2'b00;
parameter [0:1] TlbSel_IErat = 2'b10;
parameter [0:1] TlbSel_DErat = 2'b11;
parameter [0:2] CAM_PgSize_1GB = 3'b110;
parameter [0:2] CAM_PgSize_16MB = 3'b111;
parameter [0:2] CAM_PgSize_1MB = 3'b101;
parameter [0:2] CAM_PgSize_64KB = 3'b011;
parameter [0:2] CAM_PgSize_4KB = 3'b001;
parameter [0:3] WS0_PgSize_1GB = 4'b1010;
parameter [0:3] WS0_PgSize_16MB = 4'b0111;
parameter [0:3] WS0_PgSize_1MB = 4'b0101;
parameter [0:3] WS0_PgSize_64KB = 4'b0011;
parameter [0:3] WS0_PgSize_4KB = 4'b0001;
parameter eratpos_epn = 0;
parameter eratpos_x = 52;
parameter eratpos_size = 53;
parameter eratpos_v = 56;
parameter eratpos_thdid = 57;
parameter eratpos_class = 61;
parameter eratpos_extclass = 63;
parameter eratpos_wren = 65;
parameter eratpos_rpnrsvd = 66;
parameter eratpos_rpn = 70;
parameter eratpos_r = 100;
parameter eratpos_c = 101;
parameter eratpos_relsoon = 102;
parameter eratpos_wlc = 103;
parameter eratpos_resvattr = 105;
parameter eratpos_vf = 106;
parameter eratpos_ubits = 107;
parameter eratpos_wimge = 111;
parameter eratpos_usxwr = 116;
parameter eratpos_gs = 122;
parameter eratpos_ts = 123;
parameter eratpos_tid = 124;
parameter [0:2] PorSeq_Idle = 3'b000;
parameter [0:2] PorSeq_Stg1 = 3'b001;
parameter [0:2] PorSeq_Stg2 = 3'b011;
parameter [0:2] PorSeq_Stg3 = 3'b010;
parameter [0:2] PorSeq_Stg4 = 3'b110;
parameter [0:2] PorSeq_Stg5 = 3'b100;
parameter [0:2] PorSeq_Stg6 = 3'b101;
parameter [0:2] PorSeq_Stg7 = 3'b111;
parameter [0:num_entry_log2-1] Por_Wr_Entry_Num1 = 5'b11110;
parameter [0:num_entry_log2-1] Por_Wr_Entry_Num2 = 5'b11111;
// wr_cam_data -----------------------------------------------------------------
// 0:51 - EPN
// 52 - X
// 53:55 - SIZE
// 56 - V
// 57:60 - ThdID
// 61:62 - Class
// 63:64 - ExtClass | TID_NZ
// 65 - TGS
// 66 - TS
// 67:74 - TID
// 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51
// 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51
// 83 - parity for 75:82
parameter [0:83] Por_Wr_Cam_Data1 = {52'b0000000000000000000000000000000011111111111111111111, 1'b0, 3'b001, 1'b1, 4'b1111, 2'b00, 2'b00, 2'b00, 8'b00000000, 8'b11110000, 1'b0};
parameter [0:83] Por_Wr_Cam_Data2 = {52'b0000000000000000000000000000000000000000000000000000, 1'b0, 3'b001, 1'b1, 4'b1111, 2'b00, 2'b10, 2'b00, 8'b00000000, 8'b11110000, 1'b0};
// 16x143 version, 42b RA
// wr_array_data
// 0:29 - RPN
// 30:31 - R,C
// 32:35 - ResvAttr
// 36:39 - U0-U3
// 40:44 - WIMGE
// 45:46 - UX,SX
// 47:48 - UW,SW
// 49:50 - UR,SR
// 51:60 - CAM parity
// 61:67 - Array parity
parameter [0:67] Por_Wr_Array_Data1 = {30'b111111111111111111111111111111, 2'b00, 4'b0000, 4'b0000, 5'b01010, 2'b01, 2'b00, 2'b01, 10'b0000001000, 7'b0000000};
parameter [0:67] Por_Wr_Array_Data2 = {30'b000000000000000000000000000000, 2'b00, 4'b0000, 4'b0000, 5'b01010, 2'b01, 2'b00, 2'b01, 10'b0000001010, 7'b0000000};
parameter spr_msr_hv_offset = 0;
parameter spr_msr_pr_offset = spr_msr_hv_offset + `THREADS;
parameter spr_msr_ds_offset = spr_msr_pr_offset + `THREADS;
parameter spr_msr_cm_offset = spr_msr_ds_offset + `THREADS;
parameter spr_ccr2_notlb_offset = spr_msr_cm_offset + `THREADS;
parameter xucr4_mmu_mchk_offset = spr_ccr2_notlb_offset + 1;
parameter mchk_flash_inv_offset = xucr4_mmu_mchk_offset + 1;
parameter cp_next_val_offset = mchk_flash_inv_offset + 4;
parameter cp_next_itag_offset = cp_next_val_offset + `THREADS;
parameter ex2_byte_rev_offset = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC;
parameter ex3_byte_rev_offset = ex2_byte_rev_offset + 1;
parameter ex1_valid_offset = ex3_byte_rev_offset + 1;
parameter ex1_ttype_offset = ex1_valid_offset + `THREADS;
parameter ex2_valid_offset = ex1_ttype_offset + 2;
parameter ex2_pfetch_val_offset = ex2_valid_offset + `THREADS;
parameter ex2_itag_offset = ex2_pfetch_val_offset + `THREADS;
parameter ex2_ttype_offset = ex2_itag_offset + `ITAG_SIZE_ENC;
parameter ex2_ws_offset = ex2_ttype_offset + ttype_width;
parameter ex2_rs_is_offset = ex2_ws_offset + ws_width;
parameter ex2_ra_entry_offset = ex2_rs_is_offset + rs_is_width;
parameter ex2_state_offset = ex2_ra_entry_offset + 5;
parameter ex2_pid_offset = ex2_state_offset + state_width;
parameter ex2_extclass_offset = ex2_pid_offset + pid_width;
parameter ex2_tlbsel_offset = ex2_extclass_offset + extclass_width;
parameter ex2_data_in_offset = ex2_tlbsel_offset + tlbsel_width;
parameter ex3_valid_offset = ex2_data_in_offset + GPR_WIDTH;
parameter ex3_pfetch_val_offset = ex3_valid_offset + `THREADS;
parameter ex3_itag_offset = ex3_pfetch_val_offset + `THREADS;
parameter ex3_ttype_offset = ex3_itag_offset + `ITAG_SIZE_ENC;
parameter ex3_ws_offset = ex3_ttype_offset + ttype_width;
parameter ex3_rs_is_offset = ex3_ws_offset + ws_width;
parameter ex3_ra_entry_offset = ex3_rs_is_offset + rs_is_width;
parameter ex3_state_offset = ex3_ra_entry_offset + 5;
parameter ex3_pid_offset = ex3_state_offset + state_width;
parameter ex3_extclass_offset = ex3_pid_offset + pid_width;
parameter ex3_tlbsel_offset = ex3_extclass_offset + extclass_width;
parameter ex4_valid_offset = ex3_tlbsel_offset + tlbsel_width;
parameter ex4_pfetch_val_offset = ex4_valid_offset + `THREADS;
parameter ex4_itag_offset = ex4_pfetch_val_offset + `THREADS;
parameter ex4_ttype_offset = ex4_itag_offset + `ITAG_SIZE_ENC;
parameter ex4_ws_offset = ex4_ttype_offset + ttype_width;
parameter ex4_rs_is_offset = ex4_ws_offset + ws_width;
parameter ex4_ra_entry_offset = ex4_rs_is_offset + rs_is_width;
parameter ex4_state_offset = ex4_ra_entry_offset + 5;
parameter ex4_pid_offset = ex4_state_offset + state_width;
parameter ex4_lpid_offset = ex4_pid_offset + pid_width;
parameter ex4_extclass_offset = ex4_lpid_offset + lpid_width;
parameter ex4_tlbsel_offset = ex4_extclass_offset + extclass_width;
parameter ex5_valid_offset = ex4_tlbsel_offset + tlbsel_width;
parameter ex5_pfetch_val_offset = ex5_valid_offset + `THREADS;
parameter ex5_itag_offset = ex5_pfetch_val_offset + `THREADS;
parameter ex5_ttype_offset = ex5_itag_offset + `ITAG_SIZE_ENC;
parameter ex5_ws_offset = ex5_ttype_offset + ttype_width;
parameter ex5_rs_is_offset = ex5_ws_offset + ws_width;
parameter ex5_ra_entry_offset = ex5_rs_is_offset + rs_is_width;
parameter ex5_state_offset = ex5_ra_entry_offset + 5;
parameter ex5_pid_offset = ex5_state_offset + state_width;
parameter ex5_lpid_offset = ex5_pid_offset + pid_width;
parameter ex5_extclass_offset = ex5_lpid_offset + lpid_width;
parameter ex5_tlbsel_offset = ex5_extclass_offset + extclass_width;
parameter ex6_valid_offset = ex5_tlbsel_offset + tlbsel_width;
parameter ex6_pfetch_val_offset = ex6_valid_offset + `THREADS;
parameter ex6_itag_offset = ex6_pfetch_val_offset + `THREADS;
parameter ex6_ttype_offset = ex6_itag_offset + `ITAG_SIZE_ENC;
parameter ex6_ws_offset = ex6_ttype_offset + ttype_width;
parameter ex6_rs_is_offset = ex6_ws_offset + ws_width;
parameter ex6_ra_entry_offset = ex6_rs_is_offset + rs_is_width;
parameter ex6_state_offset = ex6_ra_entry_offset + 5;
parameter ex6_pid_offset = ex6_state_offset + state_width;
parameter ex6_extclass_offset = ex6_pid_offset + pid_width;
parameter ex6_tlbsel_offset = ex6_extclass_offset + extclass_width;
parameter ex7_valid_offset = ex6_tlbsel_offset + tlbsel_width;
parameter ex7_pfetch_val_offset = ex7_valid_offset + `THREADS;
parameter ex7_ttype_offset = ex7_pfetch_val_offset + `THREADS;
parameter ex7_ws_offset = ex7_ttype_offset + ttype_width;
parameter ex7_rs_is_offset = ex7_ws_offset + ws_width;
parameter ex7_ra_entry_offset = ex7_rs_is_offset + rs_is_width;
parameter ex7_state_offset = ex7_ra_entry_offset + 5;
parameter ex7_pid_offset = ex7_state_offset + state_width;
parameter ex7_extclass_offset = ex7_pid_offset + pid_width;
parameter ex7_tlbsel_offset = ex7_extclass_offset + extclass_width;
parameter ex8_valid_offset = ex7_tlbsel_offset + tlbsel_width;
parameter ex8_pfetch_val_offset = ex8_valid_offset + `THREADS;
parameter ex8_ttype_offset = ex8_pfetch_val_offset + `THREADS;
parameter ex8_tlbsel_offset = ex8_ttype_offset + ttype_width;
parameter ex5_data_out_offset = ex8_tlbsel_offset + tlbsel_width;
parameter tlb_req_inprogress_offset = ex5_data_out_offset + GPR_WIDTH;
parameter ex3_dsi_offset = tlb_req_inprogress_offset + 1;
parameter ex3_noop_touch_offset = ex3_dsi_offset + 8 + 2 * `THREADS;
parameter ex4_miss_offset = ex3_noop_touch_offset + 8 + 2 * `THREADS;
parameter ex4_dsi_offset = ex4_miss_offset + `THREADS;
parameter ex4_noop_touch_offset = ex4_dsi_offset + 8 + 2 * `THREADS;
parameter ex4_multihit_offset = ex4_noop_touch_offset + 8 + 2 * `THREADS;
parameter ex4_multihit_b_pt_offset = ex4_multihit_offset + `THREADS;
parameter ex4_first_hit_entry_pt_offset = ex4_multihit_b_pt_offset + num_entry;
parameter ex4_parerr_offset = ex4_first_hit_entry_pt_offset + num_entry - 1;
parameter ex4_attr_offset = ex4_parerr_offset + `THREADS + 2;
parameter ex4_hit_offset = ex4_attr_offset + 6;
parameter ex4_cam_hit_offset = ex4_hit_offset + 1;
parameter ex3_debug_offset = ex4_cam_hit_offset + 1;
parameter ex4_debug_offset = ex3_debug_offset + 11;
parameter rw_entry_offset = ex4_debug_offset + 17;
parameter rw_entry_val_offset = rw_entry_offset + 5;
parameter rw_entry_le_offset = rw_entry_val_offset + 1;
parameter cam_entry_le_offset = rw_entry_le_offset + 1;
parameter spare_a_offset = cam_entry_le_offset + 32;
parameter scan_right_0 = spare_a_offset + 16 - 1;
// parerr macro is commented out below
parameter ex3_comp_addr_offset = 0;
parameter ex4_rpn_offset = ex3_comp_addr_offset + 30;
parameter ex4_wimge_offset = ex4_rpn_offset + 30;
parameter ex4_cam_cmp_data_offset = ex4_wimge_offset + 5;
parameter ex4_array_cmp_data_offset = ex4_cam_cmp_data_offset + cam_data_width;
parameter ex4_rd_cam_data_offset = ex4_array_cmp_data_offset + array_data_width;
parameter ex4_rd_array_data_offset = ex4_rd_cam_data_offset + cam_data_width;
parameter ex5_parerr_offset = ex4_rd_array_data_offset + array_data_width;
parameter ex5_fir_parerr_offset = ex5_parerr_offset + `THREADS + 5;
parameter ex5_fir_multihit_offset = ex5_fir_parerr_offset + `THREADS + 3;
parameter ex5_deen_offset = ex5_fir_multihit_offset + `THREADS;
parameter ex5_hit_offset = ex5_deen_offset + num_entry_log2 + `THREADS;
parameter ex6_deen_offset = ex5_hit_offset + 1;
parameter ex6_hit_offset = ex6_deen_offset + num_entry_log2 + `THREADS;
parameter ex7_deen_offset = ex6_hit_offset + 1;
parameter ex7_hit_offset = ex7_deen_offset + num_entry_log2 + `THREADS;
parameter barrier_done_offset = ex7_hit_offset + 1;
parameter mmucr1_offset = barrier_done_offset + `THREADS;
parameter rpn_holdreg_offset = mmucr1_offset + 10;
parameter entry_valid_offset = rpn_holdreg_offset + 64 * `THREADS;
parameter entry_match_offset = entry_valid_offset + 32;
parameter watermark_offset = entry_match_offset + 32;
parameter mmucr1_b0_cpy_offset = watermark_offset + watermark_width;
parameter lru_rmt_vec_offset = mmucr1_b0_cpy_offset + 1;
parameter eptr_offset = lru_rmt_vec_offset + lru_width + 1;
parameter lru_offset = eptr_offset + eptr_width;
parameter lru_update_event_offset = lru_offset + lru_width;
parameter lru_debug_offset = lru_update_event_offset + 10;
parameter snoop_val_offset = lru_debug_offset + 41;
parameter snoop_attr_offset = snoop_val_offset + 3;
parameter snoop_addr_offset = snoop_attr_offset + 26;
parameter ex3_epn_offset = snoop_addr_offset + epn_width;
parameter ex4_epn_offset = ex3_epn_offset + (2 ** `GPR_WIDTH_ENC) - 12;
parameter ex5_epn_offset = ex4_epn_offset + (2 ** `GPR_WIDTH_ENC) - 12;
parameter por_seq_offset = ex5_epn_offset + (2 ** `GPR_WIDTH_ENC) - 12;
parameter pc_xu_init_reset_offset = por_seq_offset + 3;
parameter tlb_rel_val_offset = pc_xu_init_reset_offset + 1;
parameter tlb_rel_data_offset = tlb_rel_val_offset + 5;
parameter tlb_rel_emq_offset = tlb_rel_data_offset + 132;
parameter eplc_wr_offset = tlb_rel_emq_offset + `EMQ_ENTRIES;
parameter epsc_wr_offset = eplc_wr_offset + 2 * `THREADS + 1;
parameter ccr2_frat_paranoia_offset = epsc_wr_offset + 2 * `THREADS + 1;
parameter clkg_ctl_override_offset = ccr2_frat_paranoia_offset + 12;
parameter ex1_stg_act_offset = clkg_ctl_override_offset + 1;
parameter ex2_stg_act_offset = ex1_stg_act_offset + 1;
parameter ex3_stg_act_offset = ex2_stg_act_offset + 1;
parameter ex4_stg_act_offset = ex3_stg_act_offset + 1;
parameter ex5_stg_act_offset = ex4_stg_act_offset + 1;
parameter ex6_stg_act_offset = ex5_stg_act_offset + 1;
parameter tlb_rel_act_offset = ex6_stg_act_offset + 1;
parameter snoopp_act_offset = tlb_rel_act_offset + 1;
parameter an_ac_grffence_en_dc_offset = snoopp_act_offset + 1;
parameter spare_b_offset = an_ac_grffence_en_dc_offset + 1;
parameter csync_val_offset = spare_b_offset + 16;
parameter isync_val_offset = csync_val_offset + 2;
parameter rel_val_offset = isync_val_offset + 2;
parameter rel_hit_offset = rel_val_offset + 4;
parameter rel_data_offset = rel_hit_offset + 1;
parameter rel_emq_offset = rel_data_offset + 132;
parameter rel_int_upd_val_offset = rel_emq_offset + `EMQ_ENTRIES;
parameter epsc_wr_val_offset = rel_int_upd_val_offset + `EMQ_ENTRIES;
parameter eplc_wr_val_offset = epsc_wr_val_offset + `THREADS;
parameter rv1_binv_val_offset = eplc_wr_val_offset + `THREADS;
parameter snoopp_val_offset = rv1_binv_val_offset + 1;
parameter snoopp_attr_offset = snoopp_val_offset + 1;
parameter snoopp_vpn_offset = snoopp_attr_offset + 26;
parameter ttype_val_offset = snoopp_vpn_offset + epn_width;
parameter ttype_offset = ttype_val_offset + `THREADS;
parameter ws_offset = ttype_offset + 4;
parameter ra_entry_offset = ws_offset + ws_width;
parameter rs_data_offset = ra_entry_offset + 5;
parameter eratre_hole_offset = rs_data_offset + GPR_WIDTH;
parameter eratwe_hole_offset = eratre_hole_offset + 4;
parameter rv1_csync_val_offset = eratwe_hole_offset + 4;
parameter ex0_csync_val_offset = rv1_csync_val_offset + 1;
parameter rv1_isync_val_offset = ex0_csync_val_offset + 1;
parameter ex0_isync_val_offset = rv1_isync_val_offset + 1;
parameter rv1_rel_val_offset = ex0_isync_val_offset + 1;
parameter ex0_rel_val_offset = rv1_rel_val_offset + 4;
parameter ex1_rel_val_offset = ex0_rel_val_offset + 4;
parameter rv1_epsc_wr_val_offset = ex1_rel_val_offset + 4;
parameter ex0_epsc_wr_val_offset = rv1_epsc_wr_val_offset + `THREADS;
parameter rv1_eplc_wr_val_offset = ex0_epsc_wr_val_offset + `THREADS;
parameter ex0_eplc_wr_val_offset = rv1_eplc_wr_val_offset + `THREADS;
parameter ex0_binv_val_offset = ex0_eplc_wr_val_offset + `THREADS;
parameter ex1_binv_val_offset = ex0_binv_val_offset + 1;
parameter rv1_snoop_val_offset = ex1_binv_val_offset + 1;
parameter ex0_snoop_val_offset = rv1_snoop_val_offset + 1;
parameter ex1_snoop_val_offset = ex0_snoop_val_offset + 1;
parameter rv1_ttype_val_offset = ex1_snoop_val_offset + 1;
parameter ex0_ttype_val_offset = rv1_ttype_val_offset + `THREADS;
parameter rv1_ttype_offset = ex0_ttype_val_offset + `THREADS;
parameter ex0_ttype_offset = rv1_ttype_offset + 4;
parameter ex1_ttype03_offset = ex0_ttype_offset + 4;
parameter ex1_ttype67_offset = ex1_ttype03_offset + 4;
parameter ex1_valid_op_offset = ex1_ttype67_offset + 2;
parameter ex2_valid_op_offset = ex1_valid_op_offset + `THREADS;
parameter ex3_valid_op_offset = ex2_valid_op_offset + `THREADS;
parameter ex4_valid_op_offset = ex3_valid_op_offset + `THREADS;
parameter ex5_valid_op_offset = ex4_valid_op_offset + `THREADS;
parameter ex6_valid_op_offset = ex5_valid_op_offset + `THREADS;
parameter ex7_valid_op_offset = ex6_valid_op_offset + `THREADS;
parameter ex8_valid_op_offset = ex7_valid_op_offset + `THREADS;
parameter lq_xu_ord_write_done_offset = ex8_valid_op_offset + `THREADS;
parameter lq_xu_ord_read_done_offset = lq_xu_ord_write_done_offset + 1;
parameter xu_lq_act_offset = lq_xu_ord_read_done_offset + 1;
parameter xu_lq_val_offset = xu_lq_act_offset + 1;
parameter xu_lq_is_eratre_offset = xu_lq_val_offset + `THREADS;
parameter xu_lq_is_eratwe_offset = xu_lq_is_eratre_offset + 1;
parameter xu_lq_is_eratsx_offset = xu_lq_is_eratwe_offset + 1;
parameter xu_lq_is_eratilx_offset = xu_lq_is_eratsx_offset + 1;
parameter xu_lq_ws_offset = xu_lq_is_eratilx_offset + 1;
parameter xu_lq_ra_entry_offset = xu_lq_ws_offset + 2;
parameter xu_lq_rs_data_offset = xu_lq_ra_entry_offset + 5;
parameter cp_flush_offset = xu_lq_rs_data_offset + GPR_WIDTH;
parameter ex4_oldest_itag_offset = cp_flush_offset + `THREADS;
parameter ex4_nonspec_val_offset = ex4_oldest_itag_offset + 1;
parameter ex4_tlbmiss_offset = ex4_nonspec_val_offset + 1;
parameter ex4_tlbinelig_offset = ex4_tlbmiss_offset + 1;
parameter ex4_ptfault_offset = ex4_tlbinelig_offset + 1;
parameter ex4_lratmiss_offset = ex4_ptfault_offset + 1;
parameter ex4_tlb_multihit_offset = ex4_lratmiss_offset + 1;
parameter ex4_tlb_par_err_offset = ex4_tlb_multihit_offset + 1;
parameter ex4_lru_par_err_offset = ex4_tlb_par_err_offset + 1;
parameter ex4_tlb_excp_det_offset = ex4_lru_par_err_offset + 1;
parameter ex3_eratm_itag_hit_offset = ex4_tlb_excp_det_offset + 1;
parameter ex4_emq_excp_rpt_offset = ex3_eratm_itag_hit_offset + `EMQ_ENTRIES;
parameter ex5_emq_excp_rpt_offset = ex4_emq_excp_rpt_offset + `EMQ_ENTRIES;
parameter ex6_emq_excp_rpt_offset = ex5_emq_excp_rpt_offset + `EMQ_ENTRIES;
parameter ex5_tlb_excp_val_offset = ex6_emq_excp_rpt_offset + `EMQ_ENTRIES;
parameter ex6_tlb_excp_val_offset = ex5_tlb_excp_val_offset + `THREADS;
parameter ex4_gate_miss_offset = ex6_tlb_excp_val_offset + `THREADS;
parameter ex4_full_restart_offset = ex4_gate_miss_offset + 1;
parameter ex4_itag_hit_restart_offset = ex4_full_restart_offset + 1;
parameter ex4_epn_hit_restart_offset = ex4_itag_hit_restart_offset + 1;
parameter ex4_setHold_offset = ex4_epn_hit_restart_offset + 1;
parameter ex5_tlbreq_val_offset = ex4_setHold_offset + 1;
parameter ex5_tlbreq_nonspec_offset = ex5_tlbreq_val_offset + 1;
parameter ex5_thdid_offset = ex5_tlbreq_nonspec_offset + 1;
parameter ex5_emq_offset = ex5_thdid_offset + `THREADS;
parameter ex5_tlbreq_ttype_offset = ex5_emq_offset + `EMQ_ENTRIES;
parameter ex5_perf_dtlb_offset = ex5_tlbreq_ttype_offset + 2;
parameter derat_dcc_clr_hold_offset = ex5_perf_dtlb_offset + `THREADS;
parameter eratm_entry_state_offset = derat_dcc_clr_hold_offset + `THREADS;
parameter eratm_entry_itag_offset = eratm_entry_state_offset + 3 * `EMQ_ENTRIES;
parameter eratm_entry_tid_offset = eratm_entry_itag_offset + `ITAG_SIZE_ENC * `EMQ_ENTRIES;
parameter eratm_entry_epn_offset = eratm_entry_tid_offset + `THREADS * `EMQ_ENTRIES;
parameter eratm_entry_nonspec_val_offset = eratm_entry_epn_offset + ((2 ** `GPR_WIDTH_ENC) - 12) * `EMQ_ENTRIES;
parameter eratm_entry_mkill_offset = eratm_entry_nonspec_val_offset + `EMQ_ENTRIES;
parameter eratm_hold_tid_offset = eratm_entry_mkill_offset + `EMQ_ENTRIES;
parameter mm_int_rpt_itag_offset = eratm_hold_tid_offset + `THREADS;
parameter mm_int_rpt_tlbmiss_offset = mm_int_rpt_itag_offset + `ITAG_SIZE_ENC;
parameter mm_int_rpt_tlbinelig_offset = mm_int_rpt_tlbmiss_offset + 1;
parameter mm_int_rpt_ptfault_offset = mm_int_rpt_tlbinelig_offset + 1;
parameter mm_int_rpt_lratmiss_offset = mm_int_rpt_ptfault_offset + 1;
parameter mm_int_rpt_tlb_multihit_offset = mm_int_rpt_lratmiss_offset + 1;
parameter mm_int_rpt_tlb_par_err_offset = mm_int_rpt_tlb_multihit_offset + 1;
parameter mm_int_rpt_lru_par_err_offset = mm_int_rpt_tlb_par_err_offset + 1;
parameter eratm_entry_tlbmiss_offset = mm_int_rpt_lru_par_err_offset + 1;
parameter eratm_entry_tlbinelig_offset = eratm_entry_tlbmiss_offset + `EMQ_ENTRIES;
parameter eratm_entry_ptfault_offset = eratm_entry_tlbinelig_offset + `EMQ_ENTRIES;
parameter eratm_entry_lratmiss_offset = eratm_entry_ptfault_offset + `EMQ_ENTRIES;
parameter eratm_entry_tlb_multihit_offset = eratm_entry_lratmiss_offset + `EMQ_ENTRIES;
parameter eratm_entry_tlb_par_err_offset = eratm_entry_tlb_multihit_offset + `EMQ_ENTRIES;
parameter eratm_entry_lru_par_err_offset = eratm_entry_tlb_par_err_offset + `EMQ_ENTRIES;
parameter scan_right_1 = eratm_entry_lru_par_err_offset + `EMQ_ENTRIES - 1;
parameter bcfg_offset = 0;
parameter boot_scan_right = bcfg_offset + bcfg_width - 1;
//--------------------------
// signals
//--------------------------
// Latch signals
wire [0:`THREADS-1] ex1_valid_d;
wire [0:`THREADS-1] ex1_valid_q;
wire [10:11] ex1_ttype_d;
wire [10:11] ex1_ttype_q;
wire [0:`THREADS-1] ex2_valid_d;
wire [0:`THREADS-1] ex2_valid_q;
wire [0:`THREADS-1] ex2_pfetch_val_d;
wire [0:`THREADS-1] ex2_pfetch_val_q;
wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q;
wire [0:ttype_width-1] ex2_ttype_d;
wire [0:ttype_width-1] ex2_ttype_q;
wire [0:ws_width-1] ex2_ws_d;
wire [0:ws_width-1] ex2_ws_q;
wire [0:rs_is_width-1] ex2_rs_is_d;
wire [0:rs_is_width-1] ex2_rs_is_q;
wire [0:4] ex2_ra_entry_d;
wire [0:4] ex2_ra_entry_q;
wire [0:state_width-1] ex2_state_d;
wire [0:state_width-1] ex2_state_q;
wire [0:pid_width-1] ex2_pid_d;
wire [0:pid_width-1] ex2_pid_q;
reg [0:extclass_width-1] ex2_extclass_d;
wire [0:extclass_width-1] ex2_extclass_q;
reg [0:tlbsel_width-1] ex2_tlbsel_d;
wire [0:tlbsel_width-1] ex2_tlbsel_q;
wire [0:`THREADS-1] ex3_valid_d;
wire [0:`THREADS-1] ex3_valid_q;
wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q;
wire [0:`THREADS-1] ex3_pfetch_val_d;
wire [0:`THREADS-1] ex3_pfetch_val_q;
wire [0:ttype_width-1] ex3_ttype_d;
wire [0:ttype_width-1] ex3_ttype_q;
wire [0:ws_width-1] ex3_ws_d;
wire [0:ws_width-1] ex3_ws_q;
wire [0:rs_is_width-1] ex3_rs_is_d;
wire [0:rs_is_width-1] ex3_rs_is_q;
wire [0:4] ex3_ra_entry_d;
wire [0:4] ex3_ra_entry_q;
wire [0:state_width-1] ex3_state_d;
wire [0:state_width-1] ex3_state_q;
wire [0:pid_width-1] ex3_pid_d;
wire [0:pid_width-1] ex3_pid_q;
wire [0:extclass_width-1] ex3_extclass_d;
wire [0:extclass_width-1] ex3_extclass_q;
wire [0:tlbsel_width-1] ex3_tlbsel_d;
wire [0:tlbsel_width-1] ex3_tlbsel_q;
wire [0:`THREADS-1] ex4_valid_d;
wire [0:`THREADS-1] ex4_valid_q;
wire [0:`THREADS-1] ex4_pfetch_val_d;
wire [0:`THREADS-1] ex4_pfetch_val_q;
wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q;
wire [0:ttype_width-1] ex4_ttype_d;
wire [0:ttype_width-1] ex4_ttype_q;
wire [0:ws_width-1] ex4_ws_d;
wire [0:ws_width-1] ex4_ws_q;
wire [0:rs_is_width-1] ex4_rs_is_d;
wire [0:rs_is_width-1] ex4_rs_is_q;
wire [0:4] ex4_ra_entry_d;
wire [0:4] ex4_ra_entry_q;
wire [0:state_width-1] ex4_state_d;
wire [0:state_width-1] ex4_state_q;
wire [0:pid_width-1] ex4_pid_d;
wire [0:pid_width-1] ex4_pid_q;
wire [0:lpid_width-1] ex4_lpid_d;
wire [0:lpid_width-1] ex4_lpid_q;
wire [0:extclass_width-1] ex4_extclass_d;
wire [0:extclass_width-1] ex4_extclass_q;
wire [0:tlbsel_width-1] ex4_tlbsel_d;
wire [0:tlbsel_width-1] ex4_tlbsel_q;
wire [0:`THREADS-1] ex5_valid_d;
wire [0:`THREADS-1] ex5_valid_q;
wire [0:`THREADS-1] ex5_pfetch_val_d;
wire [0:`THREADS-1] ex5_pfetch_val_q;
wire [0:`ITAG_SIZE_ENC-1] ex5_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex5_itag_q;
wire [0:ttype_width-1] ex5_ttype_d;
wire [0:ttype_width-1] ex5_ttype_q;
wire [0:ws_width-1] ex5_ws_d;
wire [0:ws_width-1] ex5_ws_q;
wire [0:rs_is_width-1] ex5_rs_is_d;
wire [0:rs_is_width-1] ex5_rs_is_q;
wire [0:4] ex5_ra_entry_d;
wire [0:4] ex5_ra_entry_q;
wire [0:state_width-1] ex5_state_d;
wire [0:state_width-1] ex5_state_q;
wire [0:pid_width-1] ex5_pid_d;
wire [0:pid_width-1] ex5_pid_q;
wire [0:lpid_width-1] ex5_lpid_d;
wire [0:lpid_width-1] ex5_lpid_q;
wire [0:extclass_width-1] ex5_extclass_d;
wire [0:extclass_width-1] ex5_extclass_q;
wire [0:tlbsel_width-1] ex5_tlbsel_d;
wire [0:tlbsel_width-1] ex5_tlbsel_q;
wire [0:`THREADS-1] ex6_valid_d;
wire [0:`THREADS-1] ex6_valid_q;
wire [0:`THREADS-1] ex6_pfetch_val_d;
wire [0:`THREADS-1] ex6_pfetch_val_q;
wire [0:`ITAG_SIZE_ENC-1] ex6_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex6_itag_q;
wire [0:ttype_width-1] ex6_ttype_d;
wire [0:ttype_width-1] ex6_ttype_q;
wire [0:ws_width-1] ex6_ws_d;
wire [0:ws_width-1] ex6_ws_q;
wire [0:rs_is_width-1] ex6_rs_is_d;
wire [0:rs_is_width-1] ex6_rs_is_q;
wire [0:4] ex6_ra_entry_d;
wire [0:4] ex6_ra_entry_q;
wire [0:state_width-1] ex6_state_d;
wire [0:state_width-1] ex6_state_q;
wire [0:pid_width-1] ex6_pid_d;
wire [0:pid_width-1] ex6_pid_q;
wire [0:extclass_width-1] ex6_extclass_d;
wire [0:extclass_width-1] ex6_extclass_q;
wire [0:tlbsel_width-1] ex6_tlbsel_d;
wire [0:tlbsel_width-1] ex6_tlbsel_q;
wire [0:`THREADS-1] ex7_valid_d;
wire [0:`THREADS-1] ex7_valid_q;
wire [0:`THREADS-1] ex7_pfetch_val_d;
wire [0:`THREADS-1] ex7_pfetch_val_q;
wire [0:ttype_width-1] ex7_ttype_d;
wire [0:ttype_width-1] ex7_ttype_q;
wire [0:ws_width-1] ex7_ws_d;
wire [0:ws_width-1] ex7_ws_q;
wire [0:rs_is_width-1] ex7_rs_is_d;
wire [0:rs_is_width-1] ex7_rs_is_q;
wire [0:4] ex7_ra_entry_d;
wire [0:4] ex7_ra_entry_q;
wire [0:state_width-1] ex7_state_d;
wire [0:state_width-1] ex7_state_q;
wire [0:pid_width-1] ex7_pid_d;
wire [0:pid_width-1] ex7_pid_q;
wire [0:extclass_width-1] ex7_extclass_d;
wire [0:extclass_width-1] ex7_extclass_q;
wire [0:tlbsel_width-1] ex7_tlbsel_d;
wire [0:tlbsel_width-1] ex7_tlbsel_q;
wire [0:`THREADS-1] ex8_valid_d;
wire [0:`THREADS-1] ex8_valid_q;
wire [0:`THREADS-1] ex8_pfetch_val_d;
wire [0:`THREADS-1] ex8_pfetch_val_q;
wire [0:ttype_width-1] ex8_ttype_d;
wire [0:ttype_width-1] ex8_ttype_q;
wire [0:tlbsel_width-1] ex8_tlbsel_d;
wire [0:tlbsel_width-1] ex8_tlbsel_q;
wire [64-GPR_WIDTH:63] ex2_data_in_d;
wire [64-GPR_WIDTH:63] ex2_data_in_q;
wire [64-GPR_WIDTH:63] ex5_data_out_d;
wire [64-GPR_WIDTH:63] ex5_data_out_q;
wire tlb_req_inprogress_d;
wire tlb_req_inprogress_q;
wire ex2_deratre;
wire ex2_deratwe;
wire ex2_deratsx;
wire ex2_deratwe_ws3;
wire [0:7+2*`THREADS] ex3_dsi_d;
wire [0:7+2*`THREADS] ex3_dsi_q;
wire [0:7+2*`THREADS] ex3_noop_touch_d;
wire [0:7+2*`THREADS] ex3_noop_touch_q;
wire [0:`THREADS-1] ex4_miss_d;
wire [0:`THREADS-1] ex4_miss_q;
wire [0:7+2*`THREADS] ex4_dsi_d;
wire [0:7+2*`THREADS] ex4_dsi_q;
wire [0:7+2*`THREADS] ex4_noop_touch_d;
wire [0:7+2*`THREADS] ex4_noop_touch_q;
wire [0:`THREADS-1] ex4_multihit_d;
wire [0:`THREADS-1] ex4_multihit_q;
wire [1:num_entry] ex4_multihit_b_pt_d;
wire [1:num_entry] ex4_multihit_b_pt_q;
wire [1:num_entry-1] ex4_first_hit_entry_pt_d;
wire [1:num_entry-1] ex4_first_hit_entry_pt_q;
wire [0:`THREADS+1] ex4_parerr_d;
wire [0:`THREADS+1] ex4_parerr_q;
wire [0:5] ex4_attr_d;
wire [0:5] ex4_attr_q;
wire ex4_hit_d;
wire ex4_hit_q;
wire ex4_cam_hit_q;
wire [0:10] ex3_debug_d;
wire [0:10] ex3_debug_q;
wire [0:16] ex4_debug_d;
wire [0:16] ex4_debug_q;
wire [0:cam_data_width-1] ex4_cam_cmp_data_d;
wire [0:cam_data_width-1] ex4_cam_cmp_data_q;
wire [0:array_data_width-1] ex4_array_cmp_data_d;
wire [0:array_data_width-1] ex4_array_cmp_data_q;
wire [0:array_data_width-1] ex4_rd_array_data_d;
wire [0:array_data_width-1] ex4_rd_array_data_q;
wire [0:cam_data_width-1] ex4_rd_cam_data_d;
wire [0:cam_data_width-1] ex4_rd_cam_data_q;
wire [0:`THREADS+4] ex5_parerr_d;
wire [0:`THREADS+4] ex5_parerr_q;
wire [0:`THREADS+2] ex5_fir_parerr_d;
wire [0:`THREADS+2] ex5_fir_parerr_q;
wire [0:`THREADS-1] ex5_fir_multihit_d;
wire [0:`THREADS-1] ex5_fir_multihit_q;
wire [0:`THREADS+num_entry_log2-1] ex5_deen_d;
wire [0:`THREADS+num_entry_log2-1] ex5_deen_q;
wire ex5_hit_d;
wire ex5_hit_q;
wire [0:`THREADS+num_entry_log2-1] ex6_deen_d;
wire [0:`THREADS+num_entry_log2-1] ex6_deen_q;
wire ex6_hit_d;
wire ex6_hit_q;
wire [0:`THREADS+num_entry_log2-1] ex7_deen_d;
wire [0:`THREADS+num_entry_log2-1] ex7_deen_q;
wire ex7_hit_d;
wire ex7_hit_q;
wire ex4_deratwe;
wire ex5_deratwe;
wire ex6_deratwe;
wire ex7_deratwe;
wire ex8_deratwe;
wire [0:`THREADS-1] barrier_done_d;
wire [0:`THREADS-1] barrier_done_q;
wire [0:9] mmucr1_d;
wire [0:9] mmucr1_q;
wire [22:51] ex3_comp_addr_d;
wire [22:51] ex3_comp_addr_q;
wire [22:51] ex4_rpn_d;
wire [22:51] ex4_rpn_q;
wire [0:4] ex4_wimge_d;
wire [0:4] ex4_wimge_q;
wire mmucr1_b0_cpy_d;
wire mmucr1_b0_cpy_q;
wire [0:lru_width] lru_rmt_vec_d;
wire [0:lru_width] lru_rmt_vec_q;
wire [0:7] ex4_dsi;
wire [3:7] ex4_noop_touch;
reg [0:2] por_seq_d;
wire [0:2] por_seq_q;
wire [0:63] rpn_holdreg_d[0:`THREADS-1];
wire [0:63] rpn_holdreg_q[0:`THREADS-1];
reg [0:63] ex2_rpn_holdreg;
wire [0:watermark_width-1] watermark_d;
wire [0:watermark_width-1] watermark_q;
wire [0:eptr_width-1] eptr_d;
wire [0:eptr_width-1] eptr_q;
wire [1:lru_width] lru_d;
wire [1:lru_width] lru_q;
wire [0:9] lru_update_event_d;
wire [0:9] lru_update_event_q;
wire [0:40] lru_debug_d;
wire [0:40] lru_debug_q;
wire [0:2] snoop_val_d;
wire [0:2] snoop_val_q;
wire [0:25] snoop_attr_d;
wire [0:25] snoop_attr_q;
wire [52-epn_width:51] snoop_addr_d;
wire [52-epn_width:51] snoop_addr_q;
wire [64-(2**`GPR_WIDTH_ENC):51] ex3_epn_d;
wire [64-(2**`GPR_WIDTH_ENC):51] ex3_epn_q;
wire [64-(2**`GPR_WIDTH_ENC):51] ex4_epn_q;
wire [64-(2**`GPR_WIDTH_ENC):51] ex5_epn_q;
wire pc_xu_init_reset_q;
wire [0:4] tlb_rel_val_d;
wire [0:4] tlb_rel_val_q;
wire [0:131] tlb_rel_data_d;
wire [0:131] tlb_rel_data_q;
wire [0:`EMQ_ENTRIES-1] tlb_rel_emq_d;
wire [0:`EMQ_ENTRIES-1] tlb_rel_emq_q;
wire [0:2*`THREADS] eplc_wr_d;
wire [0:2*`THREADS] eplc_wr_q;
wire [0:2*`THREADS] epsc_wr_d;
wire [0:2*`THREADS] epsc_wr_q;
wire [0:11] ccr2_frat_paranoia_d;
wire [0:11] ccr2_frat_paranoia_q;
wire ex2_byte_rev_d;
wire ex2_byte_rev_q;
wire ex3_byte_rev_d;
wire ex3_byte_rev_q;
wire [0:bcfg_width-1] bcfg_q;
wire [0:bcfg_width-1] bcfg_q_b;
// logic signals
reg [0:1] por_wr_cam_val;
reg [0:1] por_wr_array_val;
reg [0:cam_data_width-1] por_wr_cam_data;
reg [0:array_data_width-1] por_wr_array_data;
reg [0:num_entry_log2-1] por_wr_entry;
reg [0:`THREADS-1] por_hold_req;
wire ex3_multihit;
wire ex3_multihit_b;
wire [0:num_entry_log2-1] ex3_first_hit_entry;
wire [0:num_entry_log2-1] ex4_first_hit_entry;
wire ex4_dsi_enab;
wire ex4_noop_touch_enab;
wire ex4_multihit_enab;
wire [0:1] ex4_parerr_enab;
wire [0:2+num_entry_log2-1] ex4_eratsx_data;
wire [0:num_entry_log2-1] lru_way_encode;
wire [0:lru_width] lru_rmt_vec;
wire [1:lru_width] lru_reset_vec;
wire [1:lru_width] lru_set_vec;
wire [1:lru_width] lru_op_vec;
wire [1:lru_width] lru_vp_vec;
wire [1:lru_width] lru_eff;
wire [0:lru_width] lru_watermark_mask;
wire [0:lru_width] entry_valid_watermarked;
//signal lru_update_event : std_ulogic;
wire [0:eptr_width-1] eptr_p1;
//signal ex4_valid_32b : std_ulogic;
wire ex1_is_icbtlslc;
wire [50:67] ex4_cmp_data_calc_par;
wire ex4_cmp_data_parerr_epn_mac;
wire ex4_cmp_data_parerr_rpn_mac;
wire ex4_cmp_data_parerr_epn;
wire ex4_cmp_data_parerr_rpn;
wire [50:67] ex4_rd_data_calc_par;
wire ex4_rd_data_parerr_epn;
wire ex4_rd_data_parerr_rpn;
wire ex5_parerr_enab;
wire ex5_fir_parerr_enab;
wire ex1_mmucr0_gs;
wire ex1_mmucr0_ts;
wire ex1_eplc_epr;
wire ex1_epsc_epr;
wire ex1_eplc_egs;
wire ex1_epsc_egs;
wire ex1_eplc_eas;
wire ex1_epsc_eas;
reg [0:pid_width-1] ex1_pid;
reg [0:pid_width-1] ex1_mmucr0_pid;
reg [0:pid_width-1] ex1_eplc_epid;
reg [0:pid_width-1] ex1_epsc_epid;
wire [0:3] tlb_rel_cmpmask;
wire [0:3] tlb_rel_xbitmask;
wire tlb_rel_maskpar;
wire [0:3] ex2_data_cmpmask;
wire [0:3] ex2_data_xbitmask;
wire ex2_data_maskpar;
wire [0:`THREADS-1] cp_flush_d;
wire [0:`THREADS-1] cp_flush_q;
// CAM/Array signals
// Read Port
wire rd_val;
wire [0:4] rw_entry;
// Write Port
wire [51:67] wr_array_par;
wire [0:array_data_width-1-10-7] wr_array_data_nopar;
wire [0:array_data_width-1] wr_array_data;
wire [0:cam_data_width-1] wr_cam_data;
wire [0:1] wr_array_val;
wire [0:1] wr_cam_val;
wire wr_val_early;
// CAM Port
wire comp_request;
wire [0:51] comp_addr;
wire [0:1] addr_enable;
wire [0:2] comp_pgsize;
wire pgsize_enable;
wire [0:1] comp_class;
wire [0:2] class_enable;
wire [0:1] comp_extclass;
wire [0:1] extclass_enable;
wire [0:1] comp_state;
wire [0:1] state_enable;
wire [0:3] comp_thdid;
wire [0:1] thdid_enable;
wire [0:7] comp_pid;
wire pid_enable;
wire comp_invalidate;
wire flash_invalidate;
// Array Outputs
wire [0:array_data_width-1] array_cmp_data;
wire [0:array_data_width-1] rd_array_data;
// CAM Outputs
wire [0:cam_data_width-1] cam_cmp_data;
wire cam_hit;
wire [0:4] cam_hit_entry;
wire [0:31] entry_match;
wire [0:31] entry_match_q;
wire [0:31] entry_valid;
wire [0:31] entry_valid_q;
wire [0:cam_data_width-1] rd_cam_data;
wire [0:2] cam_pgsize;
wire [0:3] ws0_pgsize;
// new cam _np2 signals
wire bypass_mux_enab_np1;
wire [0:20] bypass_attr_np1;
wire [0:20] attr_np2;
wire [22:51] rpn_np2;
// Pervasive
wire pc_sg_1;
wire pc_sg_0;
wire pc_func_sl_thold_1;
wire pc_func_sl_thold_0;
wire pc_func_sl_thold_0_b;
wire pc_func_slp_sl_thold_1;
wire pc_func_slp_sl_thold_0;
wire pc_func_slp_sl_thold_0_b;
wire pc_func_sl_force;
wire pc_func_slp_sl_force;
wire pc_cfg_slp_sl_thold_1;
wire pc_cfg_slp_sl_thold_0;
wire pc_cfg_slp_sl_thold_0_b;
wire pc_cfg_slp_sl_force;
wire lcb_dclk;
//wire [0:`NCLK_WIDTH-1] lcb_lclk;
wire init_alias;
// Clock Gating
wire clkg_ctl_override_d;
wire clkg_ctl_override_q;
wire ex1_stg_act_d;
wire ex1_stg_act_q;
wire ex2_stg_act_d;
wire ex2_stg_act_q;
wire ex3_stg_act_d;
wire ex3_stg_act_q;
wire ex4_stg_act_d;
wire ex4_stg_act_q;
wire ex5_stg_act_d;
wire ex5_stg_act_q;
wire ex6_stg_act_d;
wire ex6_stg_act_q;
wire an_ac_grffence_en_dc_q;
wire ex3_cmp_data_act;
wire ex3_rd_data_act;
wire entry_valid_act;
wire entry_match_act;
wire snoopp_act_q;
wire snoopp_act;
wire snoop_act;
wire tlb_rel_act_d;
wire tlb_rel_act_q;
wire tlb_rel_act;
wire mchk_flash_inv_act;
wire [0:15] spare_a_q;
wire [0:15] spare_b_q;
wire [0:39] unused_dc;
//- new latches and signals for A20 --------------------------------------------
wire [0:1] csync_val_d;
wire [0:1] csync_val_q;
wire [0:1] isync_val_d;
wire [0:1] isync_val_q;
wire [0:3] rel_val_d;
wire [0:3] rel_val_q;
wire rel_hit_d;
wire rel_hit_q;
wire [0:131] rel_data_d;
wire [0:131] rel_data_q;
wire [0:`EMQ_ENTRIES-1] rel_emq_d;
wire [0:`EMQ_ENTRIES-1] rel_emq_q;
wire [0:`EMQ_ENTRIES-1] rel_int_upd_val_d;
wire [0:`EMQ_ENTRIES-1] rel_int_upd_val_q;
wire [0:`THREADS-1] epsc_wr_val_d;
wire [0:`THREADS-1] epsc_wr_val_q;
wire [0:`THREADS-1] eplc_wr_val_d;
wire [0:`THREADS-1] eplc_wr_val_q;
wire snoopp_val_d;
wire snoopp_val_q;
wire [0:25] snoopp_attr_d;
wire [0:25] snoopp_attr_q;
wire [52-epn_width:51] snoopp_vpn_d;
wire [52-epn_width:51] snoopp_vpn_q;
wire [0:`THREADS-1] ttype_val_d;
wire [0:`THREADS-1] ttype_val_q;
wire [0:3] ttype_d;
wire [0:3] ttype_q;
wire [0:ws_width-1] ws_d;
wire [0:ws_width-1] ws_q;
wire [0:4] ra_entry_d;
wire [0:4] ra_entry_q;
wire [64-GPR_WIDTH:63] rs_data_d;
wire [64-GPR_WIDTH:63] rs_data_q;
wire [0:3] eratre_hole_d;
wire [0:3] eratre_hole_q;
wire [0:3] eratwe_hole_d;
wire [0:3] eratwe_hole_q;
wire rv1_csync_val_d;
wire rv1_csync_val_q;
wire ex0_csync_val_d;
wire ex0_csync_val_q;
wire rv1_isync_val_d;
wire rv1_isync_val_q;
wire ex0_isync_val_d;
wire ex0_isync_val_q;
wire [0:3] rv1_rel_val_d;
wire [0:3] rv1_rel_val_q;
wire [0:3] ex0_rel_val_d;
wire [0:3] ex0_rel_val_q;
wire [0:3] ex1_rel_val_d;
wire [0:3] ex1_rel_val_q;
wire [0:`THREADS-1] rv1_epsc_wr_val_d;
wire [0:`THREADS-1] rv1_epsc_wr_val_q;
wire [0:`THREADS-1] ex0_epsc_wr_val_d;
wire [0:`THREADS-1] ex0_epsc_wr_val_q;
wire [0:`THREADS-1] rv1_eplc_wr_val_d;
wire [0:`THREADS-1] rv1_eplc_wr_val_q;
wire [0:`THREADS-1] ex0_eplc_wr_val_d;
wire [0:`THREADS-1] ex0_eplc_wr_val_q;
wire rv1_binv_val_d;
wire rv1_binv_val_q;
wire ex0_binv_val_d;
wire ex0_binv_val_q;
wire ex1_binv_val_d;
wire ex1_binv_val_q;
wire rv1_snoop_val_d;
wire rv1_snoop_val_q;
wire ex0_snoop_val_d;
wire ex0_snoop_val_q;
wire ex1_snoop_val_d;
wire ex1_snoop_val_q;
wire [0:`THREADS-1] rv1_ttype_val_d;
wire [0:`THREADS-1] rv1_ttype_val_q;
wire [0:`THREADS-1] ex0_ttype_val_d;
wire [0:`THREADS-1] ex0_ttype_val_q;
wire [0:3] rv1_ttype_d;
wire [0:3] rv1_ttype_q;
wire [0:3] ex0_ttype_d;
wire [0:3] ex0_ttype_q;
wire [0:3] ex1_ttype03_d;
wire [0:3] ex1_ttype03_q;
wire [0:1] ex1_ttype67_d;
wire [0:1] ex1_ttype67_q;
wire [0:`THREADS-1] ex1_valid_op_d;
wire [0:`THREADS-1] ex1_valid_op_q;
wire [0:`THREADS-1] ex2_valid_op_d;
wire [0:`THREADS-1] ex2_valid_op_q;
wire [0:`THREADS-1] ex3_valid_op_d;
wire [0:`THREADS-1] ex3_valid_op_q;
wire [0:`THREADS-1] ex4_valid_op_d;
wire [0:`THREADS-1] ex4_valid_op_q;
wire [0:`THREADS-1] ex5_valid_op_d;
wire [0:`THREADS-1] ex5_valid_op_q;
wire [0:`THREADS-1] ex6_valid_op_d;
wire [0:`THREADS-1] ex6_valid_op_q;
wire [0:`THREADS-1] ex7_valid_op_d;
wire [0:`THREADS-1] ex7_valid_op_q;
wire [0:`THREADS-1] ex8_valid_op_d;
wire [0:`THREADS-1] ex8_valid_op_q;
wire [0:`THREADS-1] ex1_valid;
wire [0:`THREADS-1] ex2_valid;
wire [0:`THREADS-1] ex3_valid;
wire [0:`THREADS-1] ex3_valid_req;
wire [0:`THREADS-1] ex4_valid;
wire [0:`THREADS-1] ex5_valid;
wire [0:`THREADS-1] ex6_valid;
wire [0:`THREADS-1] ex7_valid;
wire [0:`THREADS-1] ex8_valid;
wire [0:4] arb_pri;
wire eratrw_hole;
wire rel_hole;
wire csync_next;
wire rel_next;
wire epsc_next;
wire eplc_next;
wire snoop_next;
wire eratre_next;
wire eratwe_next;
wire eratsx_next;
wire [0:19] derat_mmucr0[0:`THREADS-1];
wire [0:`THREADS-1] derat_mmucr0_gs;
wire [0:`THREADS-1] derat_mmucr0_ts;
wire [0:7] derat_eplc_elpid[0:`THREADS-1];
wire [0:13] derat_eplc_epid[0:`THREADS-1];
wire [0:7] derat_epsc_elpid[0:`THREADS-1];
wire [0:13] derat_epsc_epid[0:`THREADS-1];
wire [0:13] derat_pid[0:`THREADS-1];
reg [0:7] ex3_eplc_elpid;
reg [0:7] ex3_epsc_elpid;
wire [0:`THREADS-1] spr_msr_hv_d;
wire [0:`THREADS-1] spr_msr_hv_q;
wire [0:`THREADS-1] spr_msr_pr_d;
wire [0:`THREADS-1] spr_msr_pr_q;
wire [0:`THREADS-1] spr_msr_ds_d;
wire [0:`THREADS-1] spr_msr_ds_q;
wire [0:`THREADS-1] spr_msr_cm_d;
wire [0:`THREADS-1] spr_msr_cm_q;
wire spr_ccr2_notlb_d;
wire spr_ccr2_notlb_q;
wire xucr4_mmu_mchk_q;
wire [0:3] mchk_flash_inv_d;
wire [0:3] mchk_flash_inv_q;
wire mchk_flash_inv_enab;
wire [0:`THREADS-1] cp_next_val_d;
wire [0:`THREADS-1] cp_next_val_q;
wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_q[0:`THREADS-1];
wire ex4_eratm_val;
wire [0:`EMQ_ENTRIES-1] ex4_entry_wrt_val;
wire eratm_por_reset;
wire ex3_oldest_itag;
wire ex4_oldest_itag_d;
wire ex4_oldest_itag_q;
wire ex3_eratm_chk_val;
wire ex3_eratm_epn_m;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_epn_hit;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_epn_hit_restart;
wire [0:`EMQ_ENTRIES-1] ex2_eratm_itag_hit;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_d;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_q;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_restart;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_setHold;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_hit_restart;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_hit_setHold;
wire [0:`EMQ_ENTRIES-1] ex3_eratm_hit_report;
wire ex3_eratm_full;
wire [0:`EMQ_ENTRIES-1] ex3_emq_tlbmiss;
wire [0:`EMQ_ENTRIES-1] ex3_emq_tlbinelig;
wire [0:`EMQ_ENTRIES-1] ex3_emq_ptfault;
wire [0:`EMQ_ENTRIES-1] ex3_emq_lratmiss;
wire [0:`EMQ_ENTRIES-1] ex3_emq_multihit;
wire [0:`EMQ_ENTRIES-1] ex3_emq_tlb_par;
wire [0:`EMQ_ENTRIES-1] ex3_emq_lru_par;
wire [0:`EMQ_ENTRIES-1] ex4_emq_excp_rpt_d;
wire [0:`EMQ_ENTRIES-1] ex4_emq_excp_rpt_q;
wire [0:`EMQ_ENTRIES-1] ex5_emq_excp_rpt_d;
wire [0:`EMQ_ENTRIES-1] ex5_emq_excp_rpt_q;
wire [0:`EMQ_ENTRIES-1] ex6_emq_excp_rpt_d;
wire [0:`EMQ_ENTRIES-1] ex6_emq_excp_rpt_q;
wire [0:`THREADS-1] ex5_tlb_excp_val_d;
wire [0:`THREADS-1] ex5_tlb_excp_val_q;
wire [0:`THREADS-1] ex6_tlb_excp_val_d;
wire [0:`THREADS-1] ex6_tlb_excp_val_q;
wire ex6_tlb_cplt_val;
wire [0:`EMQ_ENTRIES-1] ex6_emq_excp_rpt;
wire ex3_tlbmiss;
wire ex4_tlbmiss_d;
wire ex4_tlbmiss_q;
wire ex3_tlbinelig;
wire ex4_tlbinelig_d;
wire ex4_tlbinelig_q;
wire ex3_ptfault;
wire ex4_ptfault_d;
wire ex4_ptfault_q;
wire ex3_lratmiss;
wire ex4_lratmiss_d;
wire ex4_lratmiss_q;
wire ex3_tlb_multihit;
wire ex4_tlb_multihit_d;
wire ex4_tlb_multihit_q;
wire ex3_tlb_par_err;
wire ex4_tlb_par_err_d;
wire ex4_tlb_par_err_q;
wire ex3_lru_par_err;
wire ex4_lru_par_err_d;
wire ex4_lru_par_err_q;
wire ex4_tlb_excp_det_d;
wire ex4_tlb_excp_det_q;
wire [0:`THREADS-1] ex3_cp_next_tid;
reg [0:`THREADS-1] emq_tid_idle;
wire ex3_nonspec_val;
wire ex4_nonspec_val_d;
wire ex4_nonspec_val_q;
wire ex4_gate_miss_d;
wire ex4_gate_miss_q;
wire ex4_full_restart;
wire ex4_full_restart_d;
wire ex4_full_restart_q;
wire ex4_hit_restart;
wire ex4_itag_hit_restart_d;
wire ex4_itag_hit_restart_q;
wire ex4_epn_hit_restart_d;
wire ex4_epn_hit_restart_q;
wire ex4_setHold;
wire [0:`THREADS-1] ex4_setHold_tid;
wire ex4_setHold_d;
wire ex4_setHold_q;
wire [0:`THREADS-1] derat_dcc_clr_hold_d;
wire [0:`THREADS-1] derat_dcc_clr_hold_q;
wire ex4_derat_restart;
wire ex4_tlbreq_val;
wire ex5_tlbreq_val_d;
wire ex5_tlbreq_val_q;
wire ex5_tlbreq_val;
wire ex5_tlbreq_nonspec_d;
wire ex5_tlbreq_nonspec_q;
wire [0:`THREADS-1] ex5_thdid_d;
wire [0:`THREADS-1] ex5_thdid_q;
wire [0:`EMQ_ENTRIES-1] ex5_emq_d;
wire [0:`EMQ_ENTRIES-1] ex5_emq_q;
wire [0:1] ex5_tlbreq_ttype_d;
wire [0:1] ex5_tlbreq_ttype_q;
wire ex5_tlbreq_blk;
wire [0:`EMQ_ENTRIES-1] ex5_emq_tlbreq_blk;
wire [0:`THREADS-1] ex5_perf_dtlb_d, ex5_perf_dtlb_q;
wire ex4_miss_w_tlb;
wire ex4_miss_wo_tlb;
wire [0:`EMQ_ENTRIES-1] eratm_tlb_rel_val;
wire [0:`EMQ_ENTRIES-1] eratm_wrt_ptr;
wire [0:`EMQ_ENTRIES-1] eratm_entry_available;
wire [0:`EMQ_ENTRIES-1] eratm_entry_cpl;
reg [0:2] eratm_entry_nxt_state[0:`EMQ_ENTRIES-1];
wire [0:2] eratm_entry_state_d[0:`EMQ_ENTRIES-1];
wire [0:2] eratm_entry_state_q[0:`EMQ_ENTRIES-1];
wire [0:`ITAG_SIZE_ENC-1] eratm_entry_itag_d[0:`EMQ_ENTRIES-1];
wire [0:`ITAG_SIZE_ENC-1] eratm_entry_itag_q[0:`EMQ_ENTRIES-1];
wire [0:`THREADS-1] eratm_entry_tid_d[0:`EMQ_ENTRIES-1];
wire [0:`THREADS-1] eratm_entry_tid_q[0:`EMQ_ENTRIES-1];
wire [0:`THREADS-1] eratm_entry_tid_inuse[0:`EMQ_ENTRIES-1];
wire [64-(2**`GPR_WIDTH_ENC):51] eratm_entry_epn_d[0:`EMQ_ENTRIES-1];
wire [64-(2**`GPR_WIDTH_ENC):51] eratm_entry_epn_q[0:`EMQ_ENTRIES-1];
reg [0:`EMQ_ENTRIES-1] eratm_entry_nonspec_val_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_nonspec_val_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_mkill;
wire [0:`EMQ_ENTRIES-1] eratm_entry_mkill_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_mkill_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_kill;
wire [0:`EMQ_ENTRIES-1] eratm_entry_inuse;
wire [0:`EMQ_ENTRIES-1] eratm_entry_relPend;
reg [0:`EMQ_ENTRIES-1] eratm_entry_clr_hold;
wire eratm_clrHold;
wire [0:`THREADS-1] eratm_clrHold_tid;
wire [0:1] eratm_setHold_tid_ctrl[0:`THREADS-1];
wire [0:`THREADS-1] eratm_hold_tid_d;
wire [0:`THREADS-1] eratm_hold_tid_q;
wire [0:`ITAG_SIZE_ENC-1] mm_int_rpt_itag_d;
wire [0:`ITAG_SIZE_ENC-1] mm_int_rpt_itag_q;
wire mm_int_rpt_tlbmiss_d;
wire mm_int_rpt_tlbmiss_q;
wire mm_int_rpt_tlbinelig_d;
wire mm_int_rpt_tlbinelig_q;
wire mm_int_rpt_ptfault_d;
wire mm_int_rpt_ptfault_q;
wire mm_int_rpt_lratmiss_d;
wire mm_int_rpt_lratmiss_q;
wire mm_int_rpt_tlb_multihit_d;
wire mm_int_rpt_tlb_multihit_q;
wire mm_int_rpt_tlb_par_err_d;
wire mm_int_rpt_tlb_par_err_q;
wire mm_int_rpt_lru_par_err_d;
wire mm_int_rpt_lru_par_err_q;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlbmiss_val;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlbinelig_val;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_ptfault_val;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_lratmiss_val;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlb_multihit_val;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlb_par_err_val;
wire [0:`EMQ_ENTRIES-1] mm_int_rpt_lru_par_err_val;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbmiss_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbmiss_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbinelig_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbinelig_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_ptfault_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_ptfault_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_lratmiss_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_lratmiss_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_multihit_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_multihit_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_par_err_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_par_err_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_lru_par_err_d;
wire [0:`EMQ_ENTRIES-1] eratm_entry_lru_par_err_q;
wire [0:`EMQ_ENTRIES-1] eratm_entry_int_det;
wire [0:4] rw_entry_d;
wire [0:4] rw_entry_q;
wire rw_entry_val_d;
wire rw_entry_val_q;
wire rw_entry_le_d;
wire rw_entry_le_q;
wire [0:31] cam_entry_le_wr;
wire [0:31] cam_entry_le;
wire [0:31] cam_entry_le_d;
wire [0:31] cam_entry_le_q;
wire [0:31] ex3_cam_byte_rev;
wire [0:31] ex3_cam_entry_le;
wire ex3_cam_hit_le;
wire [0:`THREADS-1] ex3_strg_noop;
wire lq_xu_ord_write_done_d;
wire lq_xu_ord_write_done_q;
wire lq_xu_ord_read_done_d;
wire lq_xu_ord_read_done_q;
wire xu_lq_act_d;
wire xu_lq_act_q;
wire [0:`THREADS-1] xu_lq_val_d;
wire [0:`THREADS-1] xu_lq_val_q;
wire xu_lq_is_eratre_d;
wire xu_lq_is_eratre_q;
wire xu_lq_is_eratwe_d;
wire xu_lq_is_eratwe_q;
wire xu_lq_is_eratsx_d;
wire xu_lq_is_eratsx_q;
wire xu_lq_is_eratilx_d;
wire xu_lq_is_eratilx_q;
wire [0:1] xu_lq_ws_d;
wire [0:1] xu_lq_ws_q;
wire [0:4] xu_lq_ra_entry_d;
wire [0:4] xu_lq_ra_entry_q;
wire [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data_d;
wire [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data_q;
wire csinv_complete;
wire [0:scan_right_0] siv_0;
wire [0:scan_right_0] sov_0;
wire [0:scan_right_1] siv_1;
wire [0:scan_right_1] sov_1;
wire [0:boot_scan_right] bsiv;
wire [0:boot_scan_right] bsov;
// cam component scan chains
wire func_si_cam_int;
wire func_so_cam_int;
//signal tidn : std_ulogic;
wire tiup;
//begin
//@@ START OF EXECUTABLE CODE FOR LQ_DERAT
//## figtree_source: lq_derat.fig;
//---------------------------------------------------------------------
// ACT Generation
//---------------------------------------------------------------------
assign clkg_ctl_override_d = spr_xucr0_clkg_ctl_b1;
assign ex1_stg_act_d = ((|(dec_derat_ex0_val)) | clkg_ctl_override_q | (|(ex0_ttype_val_q)));
assign ex2_stg_act_d = ((dec_derat_ex1_derat_act | dec_derat_ex1_ra_eq_ea | clkg_ctl_override_q) | (|(ex1_valid_op_q)) | |(dec_derat_ex1_pfetch_val));
assign ex3_stg_act_d = ex2_stg_act_q;
assign ex4_stg_act_d = ex3_stg_act_q;
assign ex5_stg_act_d = ex4_stg_act_q;
assign ex6_stg_act_d = ex5_stg_act_q;
assign ex3_cmp_data_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc_q));
assign ex3_rd_data_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc_q));
assign entry_valid_act = (~an_ac_grffence_en_dc_q);
assign entry_match_act = (~an_ac_grffence_en_dc_q);
assign mchk_flash_inv_act = (~an_ac_grffence_en_dc_q);
assign tlb_rel_act_d = mm_derat_rel_data[eratpos_relsoon];
assign tlb_rel_act = (tlb_rel_act_q & (~(spr_ccr2_notlb_q))) | clkg_ctl_override_q;
assign snoopp_act = snoopp_act_q | clkg_ctl_override_q;
assign snoop_act = snoop_next | ex1_snoop_val_q | clkg_ctl_override_q;
assign cp_flush_d = iu_lq_cp_flush;
//---------------------------------------------------------------------
// SPR
//---------------------------------------------------------------------
assign spr_msr_hv_d = xu_lq_spr_msr_hv;
assign spr_msr_pr_d = xu_lq_spr_msr_pr;
assign spr_msr_ds_d = xu_lq_spr_msr_ds;
assign spr_msr_cm_d = xu_lq_spr_msr_cm;
assign spr_ccr2_notlb_d = xu_lq_spr_ccr2_notlb;
//---------------------------------------------------------------------
// Inputs from Completion
//---------------------------------------------------------------------
assign cp_next_val_d = iu_lq_recirc_val;
//---------------------------------------------------------------------
// ERAT Operation Bus
//---------------------------------------------------------------------
assign xu_lq_act_d = xu_lq_act;
assign xu_lq_val_d = xu_lq_val & (~cp_flush_q);
assign xu_lq_is_eratre_d = xu_lq_is_eratre;
assign xu_lq_is_eratwe_d = xu_lq_is_eratwe;
assign xu_lq_is_eratsx_d = xu_lq_is_eratsx;
assign xu_lq_is_eratilx_d = xu_lq_is_eratilx;
assign xu_lq_ws_d = xu_lq_ws;
assign xu_lq_ra_entry_d = xu_lq_ra_entry;
// RS Data contains the following
// either RB Data for eratsx or RS Data for eratwe
assign xu_lq_rs_data_d = xu_lq_rs_data;
//---------------------------------------------------------------------
// Logic
//---------------------------------------------------------------------
assign tiup = 1'b1;
assign init_alias = pc_xu_init_reset_q;
assign mmucr1_d = mm_lq_mmucr1;
assign ex2_byte_rev_d = dec_derat_ex1_byte_rev;
assign ex3_byte_rev_d = ex2_byte_rev_q;
// timing latches for the ifrat delusional paranoia real mode
assign ccr2_frat_paranoia_d[0:3] = xu_lq_spr_ccr2_dfratsc[0:3];
assign ccr2_frat_paranoia_d[4] = xu_lq_spr_ccr2_dfratsc[4];
assign ccr2_frat_paranoia_d[5:8] = xu_lq_spr_ccr2_dfratsc[5:8];
assign ccr2_frat_paranoia_d[9] = xu_lq_spr_ccr2_dfrat;
assign ccr2_frat_paranoia_d[10] = dec_derat_ex1_ra_eq_ea;
assign ccr2_frat_paranoia_d[11] = ccr2_frat_paranoia_q[10];
//- latch incoming valid and data --------------------------------------------
// mmucr1: 0-DRRE, 1-REE, 2-CEE,
// 3-Disable any context sync inst from invalidating extclass=0 erat entries,
// 4-Disable isync inst from invalidating extclass=0 erat entries,
// 5:6-PEI, 7:8-DCTID|DTTID, 9-DCCD
// ttype <= 0-eratre & 1-eratwe & 2-eratsx & 3-eratilx & 4-load & 5-store &
// 6-csync & 7-isync & 8-icbtlslc & 9-touch & 10-extload & 11-extstore;
// context synch operation
assign csync_val_d[0] = iu_lq_csync;
assign isync_val_d[0] = iu_lq_isync;
assign csync_val_d[1] = ((csync_val_q[0] == 1'b1 & mmucr1_q[3] == 1'b0 & spr_ccr2_notlb_q == MMU_Mode_Value)) ? 1'b1 :
(csync_next == 1'b1) ? 1'b0 :
csync_val_q[1];
assign isync_val_d[1] = ((isync_val_q[0] == 1'b1 & mmucr1_q[4] == 1'b0 & spr_ccr2_notlb_q == MMU_Mode_Value)) ? 1'b1 :
(csync_next == 1'b1) ? 1'b0 :
isync_val_q[1];
// tlb reload -- one hot val, 4 reloads
assign rel_val_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_val[0:3] :
(rel_next == 1'b1) ? {4{1'b0}} :
rel_val_q;
assign rel_hit_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_val[4] :
rel_hit_q;
assign rel_data_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_data :
rel_data_q;
assign rel_emq_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_emq :
rel_emq_q;
// Need to update Interrupt Status for each EMQ when the reload is valid
assign rel_int_upd_val_d = (mm_derat_rel_emq & {`EMQ_ENTRIES{(|(mm_derat_rel_val))}});
// write External PID Lo
assign epsc_wr_val_d = (|(spr_derat_epsc_wr) == 1'b1) ? spr_derat_epsc_wr :
(epsc_next == 1'b1) ? {`THREADS{1'b0}} :
epsc_wr_val_q;
assign eplc_wr_val_d = (|(spr_derat_eplc_wr) == 1'b1) ? spr_derat_eplc_wr :
(eplc_next == 1'b1) ? {`THREADS{1'b0}} :
eplc_wr_val_q;
// D$ snoop
assign rv1_binv_val_d = lsq_ctl_rv0_binv_val;
// tlbivax or tlbilx sno
assign snoopp_val_d = (mm_lq_snoop_val == 1'b1) ? 1'b1 :
(snoop_next == 1'b1) ? 1'b0 :
snoopp_val_q;
assign snoopp_attr_d = (mm_lq_snoop_val == 1'b1) ? mm_lq_snoop_attr :
snoopp_attr_q;
assign snoopp_vpn_d = (mm_lq_snoop_val == 1'b1) ? mm_lq_snoop_vpn :
snoopp_vpn_q;
// ordered ttype = 0-eratre 1-eratwe 2-eratsx 3-eratilx
// ttype_val_d, ttype_d, -- fix (is ilx is not needed) check with Jon
assign ttype_val_d = (|(xu_lq_val_q) == 1'b1) ? (xu_lq_val_q & (~cp_flush_q)) :
((eratre_next | eratwe_next | eratsx_next) == 1'b1) ? {`THREADS{1'b0}} :
(ttype_val_q & (~cp_flush_q));
assign ttype_d = (|(xu_lq_val_q) == 1'b1) ? {xu_lq_is_eratre_q, xu_lq_is_eratwe_q, xu_lq_is_eratsx_q, 1'b0} :
((eratre_next | eratwe_next | eratsx_next) == 1'b1) ? 4'b0000 :
ttype_q;
assign ws_d = (|(xu_lq_val_q) == 1'b1) ? xu_lq_ws_q :
ws_q;
assign ra_entry_d = (|(xu_lq_val_q) == 1'b1) ? xu_lq_ra_entry_q :
ra_entry_q;
assign rs_data_d = (|(xu_lq_val_q) == 1'b1) ? xu_lq_rs_data_q :
rs_data_q;
// generate pipeline hole for non-ld/st ops ------------------------------------
// eratre op extended hole
assign eratre_hole_d[3] = (~(|(eratre_hole_q))) & eratre_next;
assign eratre_hole_d[2] = eratre_hole_q[3];
assign eratre_hole_d[1] = eratre_hole_q[2];
assign eratre_hole_d[0] = eratre_hole_q[1];
assign eratwe_hole_d[3] = (~(|(eratwe_hole_q))) & eratwe_next;
assign eratwe_hole_d[2] = eratwe_hole_q[3];
assign eratwe_hole_d[1] = eratwe_hole_q[2];
assign eratwe_hole_d[0] = eratwe_hole_q[1];
assign eratrw_hole = |({eratre_hole_q, eratwe_hole_q});
assign rel_hole = tlb_rel_act_q | lru_update_event_q[0] | |(rel_val_q | rv1_rel_val_q | ex0_rel_val_q | ex1_rel_val_q | tlb_rel_val_q[0:3]);
assign derat_dec_hole_all = |({csync_val_q[1], isync_val_q[1], rel_hole, epsc_wr_val_q, eplc_wr_val_q,
snoopp_val_q, ttype_val_q, eratrw_hole, por_hold_req});
//- arb Priorities -------------------------------------------------------------
assign arb_pri[0] = ~(eratrw_hole);
assign arb_pri[1] = ~(csync_val_q[1] | isync_val_q[1] | eratrw_hole);
assign arb_pri[2] = ~(csync_val_q[1] | isync_val_q[1] | |(rel_val_q[0:3]) | eratrw_hole);
assign arb_pri[3] = ~(csync_val_q[1] | isync_val_q[1] | |(rel_val_q[0:3]) | |(epsc_wr_val_q) | |(eplc_wr_val_q) | eratrw_hole | lsq_ctl_rv0_binv_val);
assign arb_pri[4] = ~(csync_val_q[1] | isync_val_q[1] | |(rel_val_q[0:3]) | |(epsc_wr_val_q) | |(eplc_wr_val_q) | snoopp_val_q | lsq_ctl_rv0_binv_val);
assign csync_next = (csync_val_q[1] | isync_val_q[1]) & arb_pri[0];
assign rel_next = (|(rel_val_q[0:3])) & arb_pri[1];
assign epsc_next = (|(epsc_wr_val_q)) & arb_pri[2];
assign eplc_next = (|(eplc_wr_val_q)) & arb_pri[2];
assign snoop_next = snoopp_val_q & arb_pri[3];
assign eratre_next = (|((ttype_val_q) & (~cp_flush_q))) & ttype_q[0] & arb_pri[4];
assign eratwe_next = (|((ttype_val_q) & (~cp_flush_q))) & ttype_q[1] & arb_pri[4];
assign eratsx_next = (|((ttype_val_q) & (~cp_flush_q))) & ttype_q[2] & arb_pri[4];
// last priority lsu op (load, store, etc)
//- pipe valids to the old interface -------------------------------------------
assign rv1_ttype_val_d = ((eratre_next | eratwe_next | eratsx_next) == 1'b1) ? (ttype_val_q & (~cp_flush_q)) :
{`THREADS{1'b0}};
assign rv1_ttype_d = ttype_q;
assign rv1_csync_val_d = csync_val_q[1] & csync_next;
assign rv1_isync_val_d = isync_val_q[1] & csync_next;
assign rv1_rel_val_d = (rel_next == 1'b1) ? rel_val_q :
{4{1'b0}};
assign rv1_epsc_wr_val_d = (epsc_next == 1'b1) ? epsc_wr_val_q :
{`THREADS{1'b0}};
assign rv1_eplc_wr_val_d = (eplc_next == 1'b1) ? eplc_wr_val_q :
{`THREADS{1'b0}};
assign rv1_snoop_val_d = snoop_next;
assign ex0_ttype_val_d = rv1_ttype_val_q & (~cp_flush_q);
assign ex0_ttype_d = rv1_ttype_q;
assign ex0_isync_val_d = rv1_isync_val_q;
assign ex0_csync_val_d = rv1_csync_val_q;
assign ex0_rel_val_d = rv1_rel_val_q;
assign ex0_epsc_wr_val_d = rv1_epsc_wr_val_q;
assign ex0_eplc_wr_val_d = rv1_eplc_wr_val_q;
assign ex0_snoop_val_d = rv1_snoop_val_q;
assign ex0_binv_val_d = rv1_binv_val_q;
assign ex1_binv_val_d = ex0_binv_val_q;
assign ex1_rel_val_d = ex0_rel_val_q;
assign ex1_snoop_val_d = ex0_snoop_val_q;
assign ex1_ttype03_d = (ex0_ttype_q & {4{(|(ex0_ttype_val_q))}});
assign ex1_ttype67_d = {ex0_csync_val_q, ex0_isync_val_q};
// old logic -------------------------------------------------------------------
// reloads
assign tlb_rel_val_d = {ex1_rel_val_q, (rel_hit_q & (|(ex1_rel_val_q)))};
assign tlb_rel_data_d = rel_data_q;
assign tlb_rel_emq_d = rel_emq_q;
// ex0 -------------------------------------------------------------------------
// Need to separate ex0_csync_val and ex0_isync_val because they should not be blocked by byp_derat_ex2_req_aborted
assign ex1_valid_d = (dec_derat_ex0_val & (~cp_flush_q));
assign ex1_ttype_d = (({dec_derat_ex0_is_extload, dec_derat_ex0_is_extstore}) & {2{(|(dec_derat_ex0_val))}});
assign ex1_valid_op_d = ex0_ttype_val_q & (~cp_flush_q);
// ex1 -------------------------------------------------------------------------
assign ex1_valid = ((ex1_valid_q | ex1_valid_op_q) & (~cp_flush_q)) | dec_derat_ex1_pfetch_val;
assign ex1_is_icbtlslc = dec_derat_ex1_icbtls_instr | dec_derat_ex1_icblc_instr;
assign ex1_eplc_epr = |(spr_derat_eplc_epr & ex1_valid);
assign ex1_eplc_egs = |(spr_derat_eplc_egs & ex1_valid);
assign ex1_eplc_eas = |(spr_derat_eplc_eas & ex1_valid);
assign ex1_epsc_epr = |(spr_derat_epsc_epr & ex1_valid);
assign ex1_epsc_egs = |(spr_derat_epsc_egs & ex1_valid);
assign ex1_epsc_eas = |(spr_derat_epsc_eas & ex1_valid);
assign ex1_mmucr0_gs = |(derat_mmucr0_gs & ex1_valid);
assign ex1_mmucr0_ts = |(derat_mmucr0_ts & ex1_valid);
// ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store
// 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore
assign ex2_valid_d = ex1_valid_q & (~cp_flush_q);
assign ex2_itag_d = dec_derat_ex1_itag;
assign ex2_pfetch_val_d = dec_derat_ex1_pfetch_val;
assign ex2_valid_op_d = ex1_valid_op_q & (~cp_flush_q);
assign ex2_valid = (((ex2_valid_q & {`THREADS{~byp_derat_ex2_req_aborted}}) | ex2_valid_op_q) & (~cp_flush_q)) | ex2_pfetch_val_q;
assign ex2_ttype_d = {ex1_ttype03_q,
(({dec_derat_ex1_is_load, dec_derat_ex1_is_store}) & {2{(~(|(ex1_ttype03_q)))}}),
ex1_ttype67_q,
(({ex1_is_icbtlslc, dec_derat_ex1_is_touch, ex1_ttype_q[10], ex1_ttype_q[11]}) & {4{(~(|(ex1_ttype03_q)))}})};
assign ex2_ws_d = ws_q;
assign ex2_rs_is_d = {rs_is_width{1'b0}};
assign ex2_ra_entry_d = ra_entry_q;
assign csinv_complete = |(ex2_ttype_q[6:7]);
generate
begin : sprThrd
genvar tid;
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin : sprThrd
assign derat_mmucr0[tid] = mm_lq_mmucr0[tid*20:(tid*20)+20-1];
assign derat_mmucr0_gs[tid] = mm_lq_mmucr0[(tid*20)+2];
assign derat_mmucr0_ts[tid] = mm_lq_mmucr0[(tid*20)+3];
assign derat_eplc_elpid[tid] = spr_derat_eplc_elpid[8 * tid:(8 * tid) + 7];
assign derat_eplc_epid[tid] = spr_derat_eplc_epid[14 * tid:(14 * tid) + 13];
assign derat_epsc_elpid[tid] = spr_derat_epsc_elpid[8 * tid:(8 * tid) + 7];
assign derat_epsc_epid[tid] = spr_derat_epsc_epid[14 * tid:(14 * tid) + 13];
assign derat_pid[tid] = mm_lq_pid[tid*14:(tid*14)+14-1];
end
end
endgenerate
//always @(derat_eplc_epid or derat_epsc_epid or derat_mmucr0 or derat_pid or derat_eplc_elpid or derat_epsc_elpid or ex3_ttype_q[10:11] or rpn_holdreg_q or ex1_valid or ex2_valid or ex3_valid_req)
always @(*)
begin: tidSpr
reg [0:13] eplc_epid;
reg [0:13] epsc_epid;
reg [0:13] mmucr0_pid;
reg [0:13] pid;
reg [0:7] eplc_elpid;
reg [0:7] epsc_elpid;
reg [0:1] extclass;
reg [0:1] tlbsel;
reg [0:63] rpnHold;
//(* analysis_not_referenced="true" *)
integer tid;
eplc_epid = {14{1'b0}};
epsc_epid = {14{1'b0}};
mmucr0_pid = {14{1'b0}};
pid = {14{1'b0}};
eplc_elpid = {8{1'b0}};
epsc_elpid = {8{1'b0}};
extclass = {2{1'b0}};
tlbsel = {2{1'b0}};
rpnHold = {64{1'b0}};
for (tid = 0; tid <= `THREADS - 1; tid = tid + 1)
begin
eplc_epid = (derat_eplc_epid[tid] & {14{ex1_valid[tid]}}) | eplc_epid;
epsc_epid = (derat_epsc_epid[tid] & {14{ex1_valid[tid]}}) | epsc_epid;
mmucr0_pid = (derat_mmucr0[tid][6:19] & {14{ex1_valid[tid]}}) | mmucr0_pid;
pid = (derat_pid[tid] & {14{ex1_valid[tid]}}) | pid;
eplc_elpid = (derat_eplc_elpid[tid] & {8{(ex3_valid_req[tid] & ex3_ttype_q[10])}}) | eplc_elpid;
epsc_elpid = (derat_epsc_elpid[tid] & {8{(ex3_valid_req[tid] & ex3_ttype_q[11])}}) | epsc_elpid;
extclass = (derat_mmucr0[tid][0:1] & {2{ex1_valid[tid]}}) | extclass;
tlbsel = (derat_mmucr0[tid][4:5] & {2{ex1_valid[tid]}}) | tlbsel;
rpnHold = (rpn_holdreg_q[tid] & {64{ex2_valid[tid]}}) | rpnHold;
end
ex1_eplc_epid = eplc_epid;
ex1_epsc_epid = epsc_epid;
ex1_mmucr0_pid = mmucr0_pid;
ex1_pid = pid;
ex3_eplc_elpid = eplc_elpid;
ex3_epsc_elpid = epsc_elpid;
ex2_extclass_d = extclass;
ex2_tlbsel_d = tlbsel;
ex2_rpn_holdreg = rpnHold;
end
assign ex2_state_d[0] = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_epr :
(ex1_ttype_q[11] == 1'b1) ? ex1_epsc_epr :
|(spr_msr_pr_q & ex1_valid);
assign ex2_state_d[1] = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_egs :
(ex1_ttype_q[11] == 1'b1) ? ex1_epsc_egs :
((ex1_ttype03_q[1] == 1'b1 | ex1_ttype03_q[2] == 1'b1)) ? ex1_mmucr0_gs :
|(spr_msr_hv_q & ex1_valid);
assign ex2_state_d[2] = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_eas :
(ex1_ttype_q[11] == 1'b1) ? ex1_epsc_eas :
((ex1_ttype03_q[1] == 1'b1 | ex1_ttype03_q[2] == 1'b1)) ? ex1_mmucr0_ts :
|(spr_msr_ds_q & ex1_valid);
assign ex2_state_d[3] = |(spr_msr_cm_q & ex1_valid);
assign ex2_pid_d = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_epid :
(ex1_ttype_q[11] == 1'b1) ? ex1_epsc_epid :
((ex1_ttype03_q[1] == 1'b1 | ex1_ttype03_q[2] == 1'b1)) ? ex1_mmucr0_pid :
ex1_pid;
assign ex2_data_in_d = rs_data_q;
// ex2 -------------------------------------------------------------------------
assign ex2_deratre = (|(ex2_valid_op_q)) & ex2_ttype_q[0] & ex2_tlbsel_q[0] & ex2_tlbsel_q[1];
assign ex2_deratwe = (|(ex2_valid_op_q)) & ex2_ttype_q[1] & ex2_tlbsel_q[0] & ex2_tlbsel_q[1];
assign ex2_deratsx = (|(ex2_valid_op_q)) & ex2_ttype_q[2] & ex2_tlbsel_q[0] & ex2_tlbsel_q[1];
assign ex3_valid_d = (ex2_valid_q & {`THREADS{~byp_derat_ex2_req_aborted}}) & ~cp_flush_q;
assign ex3_itag_d = ex2_itag_q;
assign ex3_pfetch_val_d = ex2_pfetch_val_q;
assign ex3_valid_op_d = ex2_valid_op_q & (~cp_flush_q);
assign ex3_strg_noop = {`THREADS{dcc_derat_ex3_strg_noop}};
assign ex3_valid = (((ex3_valid_q & (~ex3_strg_noop)) | ex3_valid_op_q) & (~(cp_flush_q))) | ex3_pfetch_val_q;
assign ex3_valid_req = ex3_valid_q | ex3_valid_op_q | ex3_pfetch_val_q;
assign ex3_ttype_d = ex2_ttype_q;
assign ex3_ws_d = ex2_ws_q;
assign ex3_rs_is_d = ex2_rs_is_d;
assign ex3_ra_entry_d = ex2_ra_entry_d;
assign ex3_state_d = ex2_state_q;
assign ex3_extclass_d = ex2_extclass_q;
assign ex3_tlbsel_d = ex2_tlbsel_q;
assign ex3_pid_d = ex2_pid_q;
// ex3 -------------------------------------------------------------------------
assign ex4_valid_d = ex3_valid_q & (~(cp_flush_q | ex3_strg_noop));
assign ex4_itag_d = ex3_itag_q;
assign ex4_pfetch_val_d = ex3_pfetch_val_q;
assign ex4_valid_op_d = ex3_valid_op_q & (~cp_flush_q);
assign ex4_ttype_d = ex3_ttype_q;
assign ex4_ws_d = ex3_ws_q;
assign ex4_rs_is_d = ex3_rs_is_q;
assign ex4_ra_entry_d = ex3_ra_entry_q;
// state: 0:pr 1:gs 2:ds 3:cm
assign ex4_state_d = ex3_state_q;
assign ex4_extclass_d = ex3_extclass_q;
assign ex4_tlbsel_d = ex3_tlbsel_q;
assign ex4_pid_d = ex3_pid_q;
assign ex4_lpid_d[0:lpid_width - 1] = ex3_eplc_elpid | ex3_epsc_elpid;
// ex4 -------------------------------------------------------------------------
// ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store
// 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore
assign ex4_valid = ((ex4_valid_q | ex4_valid_op_q) & (~cp_flush_q)) | ex4_pfetch_val_q;
assign ex4_deratwe = (|(ex4_valid)) & ex4_ttype_q[1] & ex4_tlbsel_q[0] & ex4_tlbsel_q[1];
assign ex4_rd_array_data_d = rd_array_data;
assign ex4_rd_cam_data_d = rd_cam_data;
assign ex5_valid_d = ex4_valid_q & (~(cp_flush_q)) & (~(ex4_miss_q));
assign ex5_itag_d = ex4_itag_q;
assign ex5_pfetch_val_d = ex4_pfetch_val_q;
assign ex5_valid_op_d = ex4_valid_op_q & (~cp_flush_q);
assign ex5_ttype_d = ex4_ttype_q;
assign ex5_ws_d = ex4_ws_q;
assign ex5_rs_is_d = ex4_rs_is_q;
// ra_entry becomes hit_entry for search, inval, load, or store
assign ex5_ra_entry_d = (ex4_ttype_q[2:5] != 4'b0000) ? ex4_first_hit_entry :
ex4_ra_entry_q;
assign ex5_tlbsel_d = ex4_tlbsel_q;
// muxes for tlbre and sending mmucr0 ExtClass,State,TID
assign ex5_extclass_d = ((|(ex4_valid) == 1'b1 & ex4_ttype_q[0] == 1'b1 & ex4_ws_q == 2'b00)) ? ex4_rd_cam_data_q[63:64] :
ex4_extclass_q;
assign ex5_state_d = ((|(ex4_valid) == 1'b1 & ex4_ttype_q[0] == 1'b1 & ex4_ws_q == 2'b00)) ? {ex4_state_q[0], ex4_rd_cam_data_q[65:66], ex4_state_q[3]} :
ex4_state_q;
assign ex5_pid_d = ((|(ex4_valid) == 1'b1 & ex4_ttype_q[0] == 1'b1 & ex4_ws_q == 2'b00)) ? {ex4_rd_cam_data_q[61:62], ex4_rd_cam_data_q[57:60], ex4_rd_cam_data_q[67:74]} :
ex4_pid_q;
assign ex5_lpid_d = ex4_lpid_q;
// ex5 -------------------------------------------------------------------------
assign ex5_valid = ((ex5_valid_q | ex5_valid_op_q) & (~cp_flush_q)) | ex5_pfetch_val_q;
assign ex5_deratwe = (|(ex5_valid)) & ex5_ttype_q[1] & ex5_tlbsel_q[0] & ex5_tlbsel_q[1];
assign ex6_valid_d = ex5_valid_q & (~(cp_flush_q));
assign ex6_itag_d = ex5_itag_q;
assign ex6_valid_op_d = ex5_valid_op_q & (~cp_flush_q);
assign ex6_pfetch_val_d = ex5_pfetch_val_q;
assign ex6_ws_d = ex5_ws_q;
assign ex6_rs_is_d = ex5_rs_is_q;
assign ex6_ra_entry_d = ex5_ra_entry_q;
assign ex6_ttype_d = ex5_ttype_q;
assign ex6_extclass_d = ex5_extclass_q;
// state: 0:pr 1:gs 2:ds 3:cm
assign ex6_state_d = ex5_state_q;
assign ex6_pid_d = ex5_pid_q;
assign ex6_tlbsel_d = ex5_tlbsel_q;
// ex6 -------------------------------------------------------------------------
assign ex6_valid = ((ex6_valid_q | ex6_valid_op_q) & (~cp_flush_q)) | ex6_pfetch_val_q;
assign ex6_deratwe = (|(ex6_valid)) & ex6_ttype_q[1] & ex6_tlbsel_q[0] & ex6_tlbsel_q[1];
assign ex7_valid_d = ex6_valid_q & (~(cp_flush_q));
assign ex7_valid_op_d = ex6_valid_op_q & (~cp_flush_q);
assign ex7_pfetch_val_d = ex6_pfetch_val_q;
assign ex7_ws_d = ex6_ws_q;
assign ex7_rs_is_d = ex6_rs_is_q;
assign ex7_ra_entry_d = ex6_ra_entry_q;
assign ex7_extclass_d = ex6_extclass_q;
assign ex7_tlbsel_d = ex6_tlbsel_q;
assign ex7_pid_d = ex6_pid_q;
assign ex7_state_d = ex6_state_q;
assign ex7_ttype_d = ex6_ttype_q;
// mmucr1: 0-DRRE, 1-REE, 2-CEE,
// 3-Disable any context sync inst from invalidating extclass=0 erat entries,
// 4-Disable isync inst from invalidating extclass=0 erat entries,
// 5:6-PEI, 7:8-DCTID|DTTID, 9-DCCD
// ttype <= 0-eratre & 1-eratwe & 2-eratsx & 3-eratilx & 4-load & 5-store &
// 6-csync & 7-isync & 8-icbtlslc & 9-touch & 10-extload & 11-extstore;
// ex7 -------------------------------------------------------------------------
assign ex7_valid = ((ex7_valid_q | ex7_valid_op_q) & (~cp_flush_q)) | ex7_pfetch_val_q;
assign ex7_deratwe = (|(ex7_valid)) & ex7_ttype_q[1] & ex7_tlbsel_q[0] & ex7_tlbsel_q[1];
// for flushing
assign ex8_valid_d = ex7_valid_q;
assign ex8_valid_op_d = ex7_valid_op_q & (~cp_flush_q);
assign ex8_pfetch_val_d = ex7_pfetch_val_q;
assign ex8_ttype_d = ex7_ttype_q;
assign ex8_tlbsel_d = ex7_tlbsel_q;
// ex8 -------------------------------------------------------------------------
assign ex8_valid = ((ex8_valid_q | ex8_valid_op_q) & (~cp_flush_q)) | ex8_pfetch_val_q;
assign ex8_deratwe = (|(ex8_valid)) & ex8_ttype_q[1] & ex8_tlbsel_q[0] & ex8_tlbsel_q[1];
// formation of ex3 phase multihit complement signal
//
// Final Table Listing
// *INPUTS*==============================*OUTPUTS*==========*
// | | |
// | entry_match | ex3_multihit_b |
// | | | | |
// | | | | |
// | | | | |
// | | 1111111111222222222233 | | |
// | 01234567890123456789012345678901 | | |
// *TYPE*================================+==================+
// | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | P |
// *POLARITY*--------------------------->| + |
// *PHASE*------------------------------>| T |
// *OPTIMIZE*--------------------------->| A |
// *TERMS*===============================+==================+
// 1 | -0000000000000000000000000000000 | 1 |
// 2 | 0-000000000000000000000000000000 | 1 |
// 3 | 00-00000000000000000000000000000 | 1 |
// 4 | 000-0000000000000000000000000000 | 1 |
// 5 | 0000-000000000000000000000000000 | 1 |
// 6 | 00000-00000000000000000000000000 | 1 |
// 7 | 000000-0000000000000000000000000 | 1 |
// 8 | 0000000-000000000000000000000000 | 1 |
// 9 | 00000000-00000000000000000000000 | 1 |
// 10 | 000000000-0000000000000000000000 | 1 |
// 11 | 0000000000-000000000000000000000 | 1 |
// 12 | 00000000000-00000000000000000000 | 1 |
// 13 | 000000000000-0000000000000000000 | 1 |
// 14 | 0000000000000-000000000000000000 | 1 |
// 15 | 00000000000000-00000000000000000 | 1 |
// 16 | 000000000000000-0000000000000000 | 1 |
// 17 | 0000000000000000-000000000000000 | 1 |
// 18 | 00000000000000000-00000000000000 | 1 |
// 19 | 000000000000000000-0000000000000 | 1 |
// 20 | 0000000000000000000-000000000000 | 1 |
// 21 | 00000000000000000000-00000000000 | 1 |
// 22 | 000000000000000000000-0000000000 | 1 |
// 23 | 0000000000000000000000-000000000 | 1 |
// 24 | 00000000000000000000000-00000000 | 1 |
// 25 | 000000000000000000000000-0000000 | 1 |
// 26 | 0000000000000000000000000-000000 | 1 |
// 27 | 00000000000000000000000000-00000 | 1 |
// 28 | 000000000000000000000000000-0000 | 1 |
// 29 | 0000000000000000000000000000-000 | 1 |
// 30 | 00000000000000000000000000000-00 | 1 |
// 31 | 000000000000000000000000000000-0 | 1 |
// 32 | 0000000000000000000000000000000- | 1 |
// *========================================================*
//
// Table EX3_MULTIHIT_B Signal Assignments for Product Terms
assign EX3_MULTIHIT_B_PT[1] = (({entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[2] = (({entry_match[0], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[3] = (({entry_match[0], entry_match[1], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[4] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[5] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[6] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[7] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[8] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[9] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[10] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[11] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[12] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[13] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[14] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[15] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[16] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[17] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[18] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[19] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[20] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000);
assign EX3_MULTIHIT_B_PT[21] =