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12908 lines
479 KiB
Verilog

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// Description: XU LSU L1 Data Cache Control
//
//*****************************************************************************
`timescale 1 ns / 1 ns
`include "tri_a2o.vh"
module lq_dcc(
rv_lq_rv1_i0_vld,
rv_lq_rv1_i0_ucode_preissue,
rv_lq_rv1_i0_2ucode,
rv_lq_rv1_i0_ucode_cnt,
rv_lq_rv1_i1_vld,
rv_lq_rv1_i1_ucode_preissue,
rv_lq_rv1_i1_2ucode,
rv_lq_rv1_i1_ucode_cnt,
dec_dcc_ex0_act,
dec_dcc_ex1_cmd_act,
dec_dcc_ex1_ucode_val,
dec_dcc_ex1_ucode_cnt,
dec_dcc_ex1_ucode_op,
dec_dcc_ex1_sfx_val,
dec_dcc_ex1_axu_op_val,
dec_dcc_ex1_axu_falign,
dec_dcc_ex1_axu_fexcpt,
dec_dcc_ex1_axu_instr_type,
dec_dcc_ex1_cache_acc,
dec_dcc_ex1_thrd_id,
dec_dcc_ex1_instr,
dec_dcc_ex1_optype1,
dec_dcc_ex1_optype2,
dec_dcc_ex1_optype4,
dec_dcc_ex1_optype8,
dec_dcc_ex1_optype16,
dec_dcc_ex1_target_gpr,
dec_dcc_ex1_mtspr_trace,
dec_dcc_ex1_load_instr,
dec_dcc_ex1_store_instr,
dec_dcc_ex1_dcbf_instr,
dec_dcc_ex1_sync_instr,
dec_dcc_ex1_l_fld,
dec_dcc_ex1_dcbi_instr,
dec_dcc_ex1_dcbz_instr,
dec_dcc_ex1_dcbt_instr,
dec_dcc_ex1_pfetch_val,
dec_dcc_ex1_dcbtst_instr,
dec_dcc_ex1_th_fld,
dec_dcc_ex1_dcbtls_instr,
dec_dcc_ex1_dcbtstls_instr,
dec_dcc_ex1_dcblc_instr,
dec_dcc_ex1_dcbst_instr,
dec_dcc_ex1_icbi_instr,
dec_dcc_ex1_icblc_instr,
dec_dcc_ex1_icbt_instr,
dec_dcc_ex1_icbtls_instr,
dec_dcc_ex1_icswx_instr,
dec_dcc_ex1_icswxdot_instr,
dec_dcc_ex1_icswx_epid,
dec_dcc_ex1_tlbsync_instr,
dec_dcc_ex1_ldawx_instr,
dec_dcc_ex1_wclr_instr,
dec_dcc_ex1_wchk_instr,
dec_dcc_ex1_resv_instr,
dec_dcc_ex1_mutex_hint,
dec_dcc_ex1_mbar_instr,
dec_dcc_ex1_makeitso_instr,
dec_dcc_ex1_is_msgsnd,
dec_dcc_ex1_dci_instr,
dec_dcc_ex1_ici_instr,
dec_dcc_ex1_mword_instr,
dec_dcc_ex1_algebraic,
dec_dcc_ex1_strg_index,
dec_dcc_ex1_src_gpr,
dec_dcc_ex1_src_axu,
dec_dcc_ex1_src_dp,
dec_dcc_ex1_targ_gpr,
dec_dcc_ex1_targ_axu,
dec_dcc_ex1_targ_dp,
dec_dcc_ex1_upd_form,
dec_dcc_ex1_itag,
dec_dcc_ex1_cr_fld,
dec_dcc_ex1_expt_det,
dec_dcc_ex1_priv_prog,
dec_dcc_ex1_hypv_prog,
dec_dcc_ex1_illeg_prog,
dec_dcc_ex1_dlock_excp,
dec_dcc_ex1_ilock_excp,
dec_dcc_ex1_ehpriv_excp,
dec_dcc_ex2_is_any_load_dac,
dec_dcc_ex5_req_abort_rpt,
dec_dcc_ex5_axu_abort_rpt,
dir_dcc_ex2_eff_addr,
lsq_ctl_rv0_back_inv,
derat_rv1_snoop_val,
dir_dcc_ex4_way_tag_a,
dir_dcc_ex4_way_tag_b,
dir_dcc_ex4_way_tag_c,
dir_dcc_ex4_way_tag_d,
dir_dcc_ex4_way_tag_e,
dir_dcc_ex4_way_tag_f,
dir_dcc_ex4_way_tag_g,
dir_dcc_ex4_way_tag_h,
dir_dcc_ex4_way_par_a,
dir_dcc_ex4_way_par_b,
dir_dcc_ex4_way_par_c,
dir_dcc_ex4_way_par_d,
dir_dcc_ex4_way_par_e,
dir_dcc_ex4_way_par_f,
dir_dcc_ex4_way_par_g,
dir_dcc_ex4_way_par_h,
dir_dcc_ex5_way_a_dir,
dir_dcc_ex5_way_b_dir,
dir_dcc_ex5_way_c_dir,
dir_dcc_ex5_way_d_dir,
dir_dcc_ex5_way_e_dir,
dir_dcc_ex5_way_f_dir,
dir_dcc_ex5_way_g_dir,
dir_dcc_ex5_way_h_dir,
dir_dcc_ex5_dir_lru,
derat_dcc_ex3_wimge_e,
derat_dcc_ex3_itagHit,
derat_dcc_ex4_wimge,
derat_dcc_ex4_usr_bits,
derat_dcc_ex4_wlc,
derat_dcc_ex4_p_addr,
derat_dcc_ex4_noop_touch,
derat_dcc_ex4_miss,
derat_dcc_ex4_tlb_err,
derat_dcc_ex4_dsi,
derat_dcc_ex4_vf,
derat_dcc_ex4_multihit_err_det,
derat_dcc_ex4_par_err_det,
derat_dcc_ex4_multihit_err_flush,
derat_dcc_ex4_par_err_flush,
derat_dcc_ex4_tlb_inelig,
derat_dcc_ex4_pt_fault,
derat_dcc_ex4_lrat_miss,
derat_dcc_ex4_tlb_multihit,
derat_dcc_ex4_tlb_par_err,
derat_dcc_ex4_lru_par_err,
derat_fir_par_err,
derat_fir_multihit,
derat_dcc_ex4_restart,
derat_dcc_ex4_setHold,
derat_dcc_clr_hold,
derat_dcc_emq_idle,
spr_dcc_ex4_dvc1_en,
spr_dcc_ex4_dvc2_en,
spr_dcc_ex4_dacrw1_cmpr,
spr_dcc_ex4_dacrw2_cmpr,
spr_dcc_ex4_dacrw3_cmpr,
spr_dcc_ex4_dacrw4_cmpr,
spr_dcc_spr_lesr,
dir_dcc_ex4_hit,
dir_dcc_ex4_miss,
dir_dcc_ex4_set_rel_coll,
dir_dcc_ex4_byp_restart,
dir_dcc_ex5_dir_perr_det,
dir_dcc_ex5_dc_perr_det,
dir_dcc_ex5_dir_perr_flush,
dir_dcc_ex5_dc_perr_flush,
dir_dcc_ex5_multihit_det,
dir_dcc_ex5_multihit_flush,
dir_dcc_stq4_dir_perr_det,
dir_dcc_stq4_multihit_det,
dir_dcc_ex5_stp_flush,
iu_lq_cp_flush,
iu_lq_recirc_val,
iu_lq_cp_next_itag,
xu_lq_xer_cp_rd,
fgen_ex1_stg_flush,
fgen_ex2_stg_flush,
fgen_ex3_stg_flush,
fgen_ex4_cp_flush,
fgen_ex4_stg_flush,
fgen_ex5_stg_flush,
dir_dcc_rel3_dcarr_upd,
xu_lq_spr_ccr2_en_trace,
xu_lq_spr_ccr2_dfrat,
xu_lq_spr_ccr2_ap,
xu_lq_spr_ccr2_ucode_dis,
xu_lq_spr_ccr2_notlb,
xu_lq_spr_xucr0_clkg_ctl,
xu_lq_spr_xucr0_wlk,
xu_lq_spr_xucr0_mbar_ack,
xu_lq_spr_xucr0_tlbsync,
xu_lq_spr_xucr0_dcdis,
xu_lq_spr_xucr0_aflsta,
xu_lq_spr_xucr0_flsta,
xu_lq_spr_xucr0_trace_um,
xu_lq_spr_xucr0_mddp,
xu_lq_spr_xucr0_mdcp,
xu_lq_spr_xucr4_mmu_mchk,
xu_lq_spr_xucr4_mddmh,
xu_lq_spr_msr_cm,
xu_lq_spr_msr_fp,
xu_lq_spr_msr_spv,
xu_lq_spr_msr_de,
xu_lq_spr_dbcr0_idm,
xu_lq_spr_epcr_duvd,
xu_lq_spr_msr_gs,
xu_lq_spr_msr_pr,
xu_lq_spr_msr_ds,
mm_lq_lsu_lpidr,
mm_lq_pid,
lsq_ctl_ex5_ldq_restart,
lsq_ctl_ex5_stq_restart,
lsq_ctl_ex5_stq_restart_miss,
lsq_ctl_ex5_fwd_val,
lsq_ctl_sync_in_stq,
lsq_ctl_rv_hold_all,
lsq_ctl_rv_set_hold,
lsq_ctl_rv_clr_hold,
lsq_ctl_stq1_stg_act,
lsq_ctl_stq1_val,
lsq_ctl_stq1_thrd_id,
lsq_ctl_stq1_store_val,
lsq_ctl_stq1_watch_clr,
lsq_ctl_stq1_l_fld,
lsq_ctl_stq1_resv,
lsq_ctl_stq1_ci,
lsq_ctl_stq1_axu_val,
lsq_ctl_stq1_epid_val,
lsq_ctl_stq1_mftgpr_val,
lsq_ctl_stq1_mfdpf_val,
lsq_ctl_stq1_mfdpa_val,
lsq_ctl_stq2_blk_req,
lsq_ctl_stq4_xucr0_cul,
lsq_ctl_stq5_itag,
lsq_ctl_stq5_tgpr,
lsq_ctl_rel1_gpr_val,
lsq_ctl_rel1_ta_gpr,
lsq_ctl_rel1_upd_gpr,
lsq_ctl_stq_cpl_ready,
lsq_ctl_stq_cpl_ready_itag,
lsq_ctl_stq_cpl_ready_tid,
lsq_ctl_stq_n_flush,
lsq_ctl_stq_np1_flush,
lsq_ctl_stq_exception_val,
lsq_ctl_stq_exception,
lsq_ctl_stq_dacrw,
ctl_lsq_stq_cpl_blk,
lsq_ctl_ex3_strg_val,
lsq_ctl_ex3_strg_noop,
lsq_ctl_ex3_illeg_lswx,
lsq_ctl_ex3_ct_val,
lsq_ctl_ex3_be_ct,
lsq_ctl_ex3_le_ct,
dir_dcc_stq3_hit,
dir_dcc_ex5_cr_rslt,
dcc_dir_ex2_frc_align2,
dcc_dir_ex2_frc_align4,
dcc_dir_ex2_frc_align8,
dcc_dir_ex2_frc_align16,
dcc_dir_ex2_64bit_agen,
dcc_dir_ex2_thrd_id,
dcc_derat_ex3_strg_noop,
dcc_derat_ex5_blk_tlb_req,
dcc_derat_ex6_cplt,
dcc_derat_ex6_cplt_itag,
dcc_dir_ex3_lru_upd,
dcc_dir_ex3_cache_acc,
dcc_dir_ex3_pfetch_val,
dcc_dir_ex3_lock_set,
dcc_dir_ex3_th_c,
dcc_dir_ex3_watch_set,
dcc_dir_ex3_larx_val,
dcc_dir_ex3_watch_chk,
dcc_dir_ex3_ddir_acc,
dcc_dir_ex4_load_val,
dcc_spr_ex3_data_val,
dcc_spr_ex3_eff_addr,
ctl_dat_ex3_opsize,
ctl_dat_ex3_le_mode,
ctl_dat_ex3_le_ld_rotsel,
ctl_dat_ex3_be_ld_rotsel,
ctl_dat_ex3_algebraic,
ctl_dat_ex3_le_alg_rotsel,
dcc_byp_rel2_stg_act,
dcc_byp_rel3_stg_act,
dcc_byp_ram_act,
byp_dcc_ex2_req_aborted,
dcc_byp_ex4_moveOp_val,
dcc_byp_stq6_moveOp_val,
dcc_byp_ex4_move_data,
dcc_byp_ex5_lq_req_abort,
dcc_byp_ex5_byte_mask,
dcc_byp_ex6_thrd_id,
dcc_byp_ex6_dvc1_en,
dcc_byp_ex6_dvc2_en,
dcc_byp_ex6_dacr_cmpr,
dcc_dir_ex4_p_addr,
dcc_dir_stq6_store_val,
ctl_lsq_ex2_streq_val,
ctl_lsq_ex2_itag,
ctl_lsq_ex2_thrd_id,
ctl_lsq_ex3_ldreq_val,
ctl_lsq_ex3_wchkall_val,
ctl_lsq_ex3_pfetch_val,
ctl_lsq_ex3_byte_en,
ctl_lsq_ex3_p_addr,
ctl_lsq_ex3_thrd_id,
ctl_lsq_ex3_algebraic,
ctl_lsq_ex3_opsize,
ctl_lsq_ex4_ldreq_val,
ctl_lsq_ex4_binvreq_val,
ctl_lsq_ex4_streq_val,
ctl_lsq_ex4_othreq_val,
ctl_lsq_ex4_p_addr,
ctl_lsq_ex4_dReq_val,
ctl_lsq_ex4_gath_load,
ctl_lsq_ex4_send_l2,
ctl_lsq_ex4_has_data,
ctl_lsq_ex4_cline_chk,
ctl_lsq_ex4_wimge,
ctl_lsq_ex4_byte_swap,
ctl_lsq_ex4_is_sync,
ctl_lsq_ex4_all_thrd_chk,
ctl_lsq_ex4_is_store,
ctl_lsq_ex4_is_resv,
ctl_lsq_ex4_is_mfgpr,
ctl_lsq_ex4_is_icswxr,
ctl_lsq_ex4_is_icbi,
ctl_lsq_ex4_watch_clr,
ctl_lsq_ex4_watch_clr_all,
ctl_lsq_ex4_mtspr_trace,
ctl_lsq_ex4_is_inval_op,
ctl_lsq_ex4_is_cinval,
ctl_lsq_ex5_lock_clr,
ctl_lsq_ex5_lock_set,
ctl_lsq_ex5_watch_set,
ctl_lsq_ex5_tgpr,
ctl_lsq_ex5_axu_val,
ctl_lsq_ex5_is_epid,
ctl_lsq_ex5_usr_def,
ctl_lsq_ex5_drop_rel,
ctl_lsq_ex5_flush_req,
ctl_lsq_ex5_flush_pfetch,
ctl_lsq_ex5_cmmt_events,
ctl_lsq_ex5_perf_val0,
ctl_lsq_ex5_perf_sel0,
ctl_lsq_ex5_perf_val1,
ctl_lsq_ex5_perf_sel1,
ctl_lsq_ex5_perf_val2,
ctl_lsq_ex5_perf_sel2,
ctl_lsq_ex5_perf_val3,
ctl_lsq_ex5_perf_sel3,
ctl_lsq_ex5_not_touch,
ctl_lsq_ex5_class_id,
ctl_lsq_ex5_dvc,
ctl_lsq_ex5_dacrw,
ctl_lsq_ex5_ttype,
ctl_lsq_ex5_l_fld,
ctl_lsq_ex5_load_hit,
lsq_ctl_ex6_ldq_events,
lsq_ctl_ex6_stq_events,
ctl_lsq_stq3_icswx_data,
ctl_lsq_dbg_int_en,
ctl_lsq_ldp_idle,
ctl_lsq_rv1_dir_rd_val,
dcc_dec_arr_rd_rv1_val,
dcc_dec_arr_rd_congr_cl,
dcc_dec_stq3_mftgpr_val,
dcc_dec_stq5_mftgpr_val,
lq_xu_spr_xucr0_cul,
dcc_dir_spr_xucr2_rmt,
spr_dcc_spr_xudbg0_exec,
spr_dcc_spr_xudbg0_tid,
spr_dcc_spr_xudbg0_way,
spr_dcc_spr_xudbg0_row,
dcc_spr_spr_xudbg0_done,
dcc_spr_spr_xudbg1_valid,
dcc_spr_spr_xudbg1_watch,
dcc_spr_spr_xudbg1_parity,
dcc_spr_spr_xudbg1_lru,
dcc_spr_spr_xudbg1_lock,
dcc_spr_spr_xudbg2_tag,
spr_dcc_spr_xucr2_rmt,
spr_dcc_spr_lsucr0_clchk,
spr_dcc_spr_acop_ct,
spr_dcc_spr_hacop_ct,
spr_dcc_epsc_epr,
spr_dcc_epsc_eas,
spr_dcc_epsc_egs,
spr_dcc_epsc_elpid,
spr_dcc_epsc_epid,
dcc_dir_ex2_binv_val,
stq4_dcarr_wren,
dcc_byp_ram_sel,
dcc_dec_ex5_wren,
lq_xu_ex5_abort,
lq_xu_gpr_ex5_wa,
lq_rv_gpr_ex6_wa,
lq_xu_axu_rel_we,
lq_xu_gpr_rel_we,
lq_xu_gpr_rel_wa,
lq_rv_gpr_rel_we,
lq_rv_gpr_rel_wa,
lq_xu_cr_ex5_we,
lq_xu_cr_ex5_wa,
lq_xu_ex5_cr,
lq_xu_axu_ex4_addr,
lq_xu_axu_ex5_we,
lq_xu_axu_ex5_le,
lq_rv_itag1_vld,
lq_rv_itag1,
lq_rv_itag1_restart,
lq_rv_itag1_abort,
lq_rv_itag1_hold,
lq_rv_itag1_cord,
lq_rv_clr_hold,
dcc_dec_hold_all,
lq0_iu_execute_vld,
lq0_iu_recirc_val,
lq0_iu_itag,
lq0_iu_flush2ucode,
lq0_iu_flush2ucode_type,
lq0_iu_exception_val,
lq0_iu_exception,
lq0_iu_dear_val,
lq0_iu_n_flush,
lq0_iu_np1_flush,
lq0_iu_dacr_type,
lq0_iu_dacrw,
lq0_iu_instr,
lq0_iu_eff_addr,
dcc_pf_ex5_eff_addr,
dcc_pf_ex5_req_val_4pf,
dcc_pf_ex5_act,
dcc_pf_ex5_thrd_id,
dcc_pf_ex5_loadmiss,
dcc_pf_ex5_itag,
lq_pc_err_derat_parity,
lq_pc_err_dir_ldp_parity,
lq_pc_err_dir_stp_parity,
lq_pc_err_dcache_parity,
lq_pc_err_derat_multihit,
lq_pc_err_dir_ldp_multihit,
lq_pc_err_dir_stp_multihit,
pc_lq_ram_active,
lq_pc_ram_data_val,
ctl_perv_ex6_perf_events,
ctl_perv_stq4_perf_events,
dcc_dir_ex2_stg_act,
dcc_dir_ex3_stg_act,
dcc_dir_ex4_stg_act,
dcc_dir_ex5_stg_act,
dcc_dir_stq1_stg_act,
dcc_dir_stq2_stg_act,
dcc_dir_stq3_stg_act,
dcc_dir_stq4_stg_act,
dcc_dir_stq5_stg_act,
dcc_dir_binv2_ex2_stg_act,
dcc_dir_binv3_ex3_stg_act,
dcc_dir_binv4_ex4_stg_act,
dcc_dir_binv5_ex5_stg_act,
dcc_dir_binv6_ex6_stg_act,
vdd,
gnd,
clk,
rst,
sg_0,
func_sl_thold_0_b,
func_sl_force,
func_nsl_thold_0_b,
func_nsl_force,
func_slp_sl_thold_0_b,
func_slp_sl_force,
func_slp_nsl_thold_0_b,
func_slp_nsl_force,
d_mode_dc,
delay_lclkr_dc,
mpw1_dc_b,
mpw2_dc_b,
scan_in,
scan_out
);
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter ITAG_SIZE_ENC = 7; // Instruction Tag Size
//parameter CR_POOL_ENC = 5; // Encode of CR rename pool size
//parameter GPR_POOL_ENC = 6;
//parameter THREADS_POOL_ENC = 1;
//parameter UCODE_ENTRIES_ENC = 3;
//parameter REAL_IFAR_WIDTH = 42; // 42 bit real address
//parameter DC_SIZE = 15; // 2^15 = 32768 Bytes L1 D$
//parameter AXU_SPARE_ENC = 3;
//parameter GPR_WIDTH_ENC = 6; // 5 = 32bit mode, 6 = 64bit mode
//parameter `CR_WIDTH = 4;
parameter PARBITS = 4; // Number of Parity Bits
// IU Dispatch
input [0:`THREADS-1] rv_lq_rv1_i0_vld;
input rv_lq_rv1_i0_ucode_preissue;
input rv_lq_rv1_i0_2ucode;
input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt;
input [0:`THREADS-1] rv_lq_rv1_i1_vld;
input rv_lq_rv1_i1_ucode_preissue;
input rv_lq_rv1_i1_2ucode;
input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt;
// Execution Pipe Inputs
input dec_dcc_ex0_act; // ACT
input dec_dcc_ex1_cmd_act; // ACT
input dec_dcc_ex1_ucode_val; // PreIssue of Ucode operation is valid
input [0:`UCODE_ENTRIES_ENC-1] dec_dcc_ex1_ucode_cnt;
input dec_dcc_ex1_ucode_op;
input dec_dcc_ex1_sfx_val; // Simple FXU operation is valid
input dec_dcc_ex1_axu_op_val; // Operation is from the AXU
input dec_dcc_ex1_axu_falign; // AXU force alignment indicator
input dec_dcc_ex1_axu_fexcpt; // AXU force alignment exception on misaligned access
input [0:2] dec_dcc_ex1_axu_instr_type;
input dec_dcc_ex1_cache_acc; // Cache Access is Valid, Op that touches directory
input [0:`THREADS-1] dec_dcc_ex1_thrd_id;
input [0:31] dec_dcc_ex1_instr;
input dec_dcc_ex1_optype1; // 1 Byte Load/Store
input dec_dcc_ex1_optype2; // 2 Byte Load/Store
input dec_dcc_ex1_optype4; // 4 Byte Load/Store
input dec_dcc_ex1_optype8; // 8 Byte Load/Store
input dec_dcc_ex1_optype16; // 16 Byte Load/Store
input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] dec_dcc_ex1_target_gpr; // Target GPR, needed for reloads
input dec_dcc_ex1_mtspr_trace; // Operation is a mtspr trace instruction
input dec_dcc_ex1_load_instr; // Operation is a Load instruction
input dec_dcc_ex1_store_instr; // Operation is a Store instruction
input dec_dcc_ex1_dcbf_instr; // Operation is a DCBF instruction
input dec_dcc_ex1_sync_instr; // Operation is a SYNC instruction
input [0:1] dec_dcc_ex1_l_fld; // DCBF/SYNC L Field
input dec_dcc_ex1_dcbi_instr; // Operation is a DCBI instruction
input dec_dcc_ex1_dcbz_instr; // Operation is a DCBZ instruction
input dec_dcc_ex1_dcbt_instr; // Operation is a DCBT instruction
input dec_dcc_ex1_pfetch_val; // Operation is a prefetch
input dec_dcc_ex1_dcbtst_instr; // Operation is a DCBTST instruction
input [0:4] dec_dcc_ex1_th_fld; // TH/CT Field for Cache Management instructions
input dec_dcc_ex1_dcbtls_instr;
input dec_dcc_ex1_dcbtstls_instr;
input dec_dcc_ex1_dcblc_instr;
input dec_dcc_ex1_dcbst_instr;
input dec_dcc_ex1_icbi_instr;
input dec_dcc_ex1_icblc_instr;
input dec_dcc_ex1_icbt_instr;
input dec_dcc_ex1_icbtls_instr;
input dec_dcc_ex1_icswx_instr;
input dec_dcc_ex1_icswxdot_instr;
input dec_dcc_ex1_icswx_epid;
input dec_dcc_ex1_tlbsync_instr;
input dec_dcc_ex1_ldawx_instr;
input dec_dcc_ex1_wclr_instr;
input dec_dcc_ex1_wchk_instr;
input dec_dcc_ex1_resv_instr; // Operation is a resv instruction
input dec_dcc_ex1_mutex_hint; // Mutex Hint For larx instructions
input dec_dcc_ex1_mbar_instr; // Operation is an MBAR instruction
input dec_dcc_ex1_makeitso_instr;
input dec_dcc_ex1_is_msgsnd;
input dec_dcc_ex1_dci_instr;
input dec_dcc_ex1_ici_instr;
input dec_dcc_ex1_mword_instr; // load/store multiple word instruction
input dec_dcc_ex1_algebraic; // Operation is an Algebraic Load instruction
input dec_dcc_ex1_strg_index; // String Indexed Form
input dec_dcc_ex1_src_gpr; // Source is the GPR's for mfloat and mDCR ops
input dec_dcc_ex1_src_axu; // Source is the AXU's for mfloat and mDCR ops
input dec_dcc_ex1_src_dp; // Source is the BOX's for mfloat and mDCR ops
input dec_dcc_ex1_targ_gpr; // Target is the GPR's for mfloat and mDCR ops
input dec_dcc_ex1_targ_axu; // Target is the AXU's for mfloat and mDCR ops
input dec_dcc_ex1_targ_dp; // Target is the BOX's for mfloat and mDCR ops
input dec_dcc_ex1_upd_form;
input [0:`ITAG_SIZE_ENC-1] dec_dcc_ex1_itag;
input [0:`CR_POOL_ENC-1] dec_dcc_ex1_cr_fld;
input dec_dcc_ex1_expt_det;
input dec_dcc_ex1_priv_prog;
input dec_dcc_ex1_hypv_prog;
input dec_dcc_ex1_illeg_prog;
input dec_dcc_ex1_dlock_excp;
input dec_dcc_ex1_ilock_excp;
input dec_dcc_ex1_ehpriv_excp;
input dec_dcc_ex2_is_any_load_dac;
input dec_dcc_ex5_req_abort_rpt;
input dec_dcc_ex5_axu_abort_rpt;
input [64-(2**`GPR_WIDTH_ENC):63] dir_dcc_ex2_eff_addr;
// Directory Back-Invalidate
input lsq_ctl_rv0_back_inv; // L2 Back-Invalidate is Valid
// Derat Snoop-Invalidate
input derat_rv1_snoop_val;
// Directory Read Operation
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_a;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_b;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_c;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_d;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_e;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_f;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_g;
input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_h;
input [0:PARBITS-1] dir_dcc_ex4_way_par_a;
input [0:PARBITS-1] dir_dcc_ex4_way_par_b;
input [0:PARBITS-1] dir_dcc_ex4_way_par_c;
input [0:PARBITS-1] dir_dcc_ex4_way_par_d;
input [0:PARBITS-1] dir_dcc_ex4_way_par_e;
input [0:PARBITS-1] dir_dcc_ex4_way_par_f;
input [0:PARBITS-1] dir_dcc_ex4_way_par_g;
input [0:PARBITS-1] dir_dcc_ex4_way_par_h;
input [0:1+`THREADS] dir_dcc_ex5_way_a_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_b_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_c_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_d_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_e_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_f_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_g_dir;
input [0:1+`THREADS] dir_dcc_ex5_way_h_dir;
input [0:6] dir_dcc_ex5_dir_lru;
input derat_dcc_ex3_wimge_e;
input derat_dcc_ex3_itagHit;
input [0:4] derat_dcc_ex4_wimge; // Memory Attribute I Bit from ERAT
input [0:3] derat_dcc_ex4_usr_bits; // User Defined Bits from ERAT
input [0:1] derat_dcc_ex4_wlc; // ClassID
input [64-`REAL_IFAR_WIDTH:51] derat_dcc_ex4_p_addr;
input derat_dcc_ex4_noop_touch;
input derat_dcc_ex4_miss;
input derat_dcc_ex4_tlb_err;
input derat_dcc_ex4_dsi;
input derat_dcc_ex4_vf;
input derat_dcc_ex4_multihit_err_det;
input derat_dcc_ex4_par_err_det;
input derat_dcc_ex4_multihit_err_flush;
input derat_dcc_ex4_par_err_flush;
input derat_dcc_ex4_tlb_inelig;
input derat_dcc_ex4_pt_fault;
input derat_dcc_ex4_lrat_miss;
input derat_dcc_ex4_tlb_multihit;
input derat_dcc_ex4_tlb_par_err;
input derat_dcc_ex4_lru_par_err;
input derat_dcc_ex4_restart;
input derat_fir_par_err;
input derat_fir_multihit;
// SetHold and ClrHold for itag
input derat_dcc_ex4_setHold;
input [0:`THREADS-1] derat_dcc_clr_hold;
// EMQ Idle indicator
input [0:`THREADS-1] derat_dcc_emq_idle;
// DEBUG Address Compare Exception
input spr_dcc_ex4_dvc1_en;
input spr_dcc_ex4_dvc2_en;
input spr_dcc_ex4_dacrw1_cmpr;
input spr_dcc_ex4_dacrw2_cmpr;
input spr_dcc_ex4_dacrw3_cmpr;
input spr_dcc_ex4_dacrw4_cmpr;
input [0:47] spr_dcc_spr_lesr;
input dir_dcc_ex4_hit; // ex4 Load/Store Hit
input dir_dcc_ex4_miss; // ex4 Load/Store Miss
input dir_dcc_ex4_set_rel_coll; // Resource Conflict, should cause a reject
input dir_dcc_ex4_byp_restart; // Directory Bypassed stage that was restarted
input dir_dcc_ex5_dir_perr_det; // Data Directory Parity Error Detected
input dir_dcc_ex5_dc_perr_det; // Data Cache Parity Error Detected
input dir_dcc_ex5_dir_perr_flush; // Data Directory Parity Error Flush
input dir_dcc_ex5_dc_perr_flush; // Data Cache Parity Error Flush
input dir_dcc_ex5_multihit_det; // Directory Multihit Detected
input dir_dcc_ex5_multihit_flush; // Directory Multihit Flush
input dir_dcc_stq4_dir_perr_det; // Data Cache Parity Error Detected on the STQ Commit Pipeline
input dir_dcc_stq4_multihit_det; // Directory Multihit Detected on the STQ Commit Pipeline
input dir_dcc_ex5_stp_flush; // Directory Error detected on the STQ Commit Pipeline with EX5 LDP valid
// Completion Inputs
input [0:`THREADS-1] iu_lq_cp_flush; // Completion Flush Report
input [0:`THREADS-1] iu_lq_recirc_val; // Next Itag Completion Report
input [0:`THREADS*`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag; // Next Itag Completion Itag
// XER[SO] Read for CP_NEXT instructions (stcx./icswx./ldawx.)
input [0:`THREADS-1] xu_lq_xer_cp_rd;
// Stage Flush
output fgen_ex1_stg_flush; // ex1 Stage Flush
output fgen_ex2_stg_flush; // ex2 Stage Flush
output fgen_ex3_stg_flush; // ex3 Stage Flush
output fgen_ex4_cp_flush; // ex4 CP Flush
output fgen_ex4_stg_flush; // ex4 Stage Flush
output fgen_ex5_stg_flush; // ex5 Stage Flush
input dir_dcc_rel3_dcarr_upd; // Reload Data Array Update Valid
// Data Cache Config
input xu_lq_spr_ccr2_en_trace; // MTSPR Trace is Enabled
input xu_lq_spr_ccr2_dfrat; // Force Real Address Translation
input xu_lq_spr_ccr2_ap; // AP Available
input xu_lq_spr_ccr2_ucode_dis; // Ucode Disabled
input xu_lq_spr_ccr2_notlb; // MMU is disabled
input xu_lq_spr_xucr0_clkg_ctl; // Clock Gating Override
input xu_lq_spr_xucr0_wlk; // Data Cache Way Locking Enable
input xu_lq_spr_xucr0_mbar_ack; // L2 ACK of membar and lwsync
input xu_lq_spr_xucr0_tlbsync; // L2 ACK of tlbsync
input xu_lq_spr_xucr0_dcdis; // Data Cache Disable
input xu_lq_spr_xucr0_aflsta; // AXU Force Load/Store Alignment interrupt
input xu_lq_spr_xucr0_flsta; // FX Force Load/Store Alignment interrupt
input [0:`THREADS-1] xu_lq_spr_xucr0_trace_um; // TRACE SPR is Enabled in user mode
input xu_lq_spr_xucr0_mddp; // Machine Check on Data Cache Directory Parity Error
input xu_lq_spr_xucr0_mdcp; // Machine Check on Data Cache Parity Error
input xu_lq_spr_xucr4_mmu_mchk; // Machine Check on a Data ERAT Parity or Multihit Error
input xu_lq_spr_xucr4_mddmh; // Machine Check on Data Cache Directory Multihit Error
input [0:`THREADS-1] xu_lq_spr_msr_cm; // 64bit mode enable
input [0:`THREADS-1] xu_lq_spr_msr_fp; // FP Available
input [0:`THREADS-1] xu_lq_spr_msr_spv; // VEC Available
input [0:`THREADS-1] xu_lq_spr_msr_de; // Debug Interrupt Enable
input [0:`THREADS-1] xu_lq_spr_dbcr0_idm; // Internal Debug Mode Enable
input [0:`THREADS-1] xu_lq_spr_epcr_duvd; // Disable Hypervisor Debug
// MSR[GS,PR] bits, indicates which state we are running in
input [0:`THREADS-1] xu_lq_spr_msr_gs; // (MSR.GS)
input [0:`THREADS-1] xu_lq_spr_msr_pr; // Problem State (MSR.PR)
input [0:`THREADS-1] xu_lq_spr_msr_ds; // Data Address Space (MSR.DS)
input [0:7] mm_lq_lsu_lpidr; // the LPIDR register
input [0:14*`THREADS-1] mm_lq_pid;
// RESTART indicator
input lsq_ctl_ex5_ldq_restart; // Loadmiss Queue Report
input lsq_ctl_ex5_stq_restart; // Store Queue Report
input lsq_ctl_ex5_stq_restart_miss;
// Store Data Forward
input lsq_ctl_ex5_fwd_val;
input lsq_ctl_sync_in_stq;
// Hold RV Indicator
input lsq_ctl_rv_hold_all;
// Reservation station set barrier indicator
input lsq_ctl_rv_set_hold;
input [0:`THREADS-1] lsq_ctl_rv_clr_hold;
// Reload/Commit Pipe
input lsq_ctl_stq1_stg_act;
input lsq_ctl_stq1_val;
input [0:`THREADS-1] lsq_ctl_stq1_thrd_id;
input lsq_ctl_stq1_store_val; // Store Commit instruction
input lsq_ctl_stq1_watch_clr; // Recirc Watch Clear instruction
input [0:1] lsq_ctl_stq1_l_fld; // Recirc Watch Clear L-Field
input lsq_ctl_stq1_resv;
input lsq_ctl_stq1_ci;
input lsq_ctl_stq1_axu_val; // Reload is for a Vector Register
input lsq_ctl_stq1_epid_val;
input lsq_ctl_stq1_mftgpr_val; // MFTGPR instruction Valid
input lsq_ctl_stq1_mfdpf_val; // MFDP to the Fixed Point Unit instruction Valid
input lsq_ctl_stq1_mfdpa_val; // MFDP to the Auxilary Unit instruction Valid
input lsq_ctl_stq2_blk_req; // Block Store due to RV issue
input lsq_ctl_stq4_xucr0_cul;
input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq5_itag;
input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_stq5_tgpr;
input lsq_ctl_rel1_gpr_val;
input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_rel1_ta_gpr;
input lsq_ctl_rel1_upd_gpr; // Reload data should be written to GPR (DCB ops don't write to GPRs)
// Store Queue Completion Report
input lsq_ctl_stq_cpl_ready;
input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_cpl_ready_itag;
input [0:`THREADS-1] lsq_ctl_stq_cpl_ready_tid;
input lsq_ctl_stq_n_flush;
input lsq_ctl_stq_np1_flush;
input lsq_ctl_stq_exception_val;
input [0:5] lsq_ctl_stq_exception;
input [0:3] lsq_ctl_stq_dacrw;
output ctl_lsq_stq_cpl_blk;
// Illegal LSWX has been determined
input lsq_ctl_ex3_strg_val; // STQ has checked XER valid
input lsq_ctl_ex3_strg_noop; // STQ detected a noop of LSWX/STSWX
input lsq_ctl_ex3_illeg_lswx; // STQ detected illegal form of LSWX
input lsq_ctl_ex3_ct_val; // ICSWX Data is valid
input [0:5] lsq_ctl_ex3_be_ct; // Big Endian Coprocessor Type Select
input [0:5] lsq_ctl_ex3_le_ct; // Little Endian Coprocessor Type Select
// Directory Results Input
input dir_dcc_stq3_hit;
input dir_dcc_ex5_cr_rslt;
// EX2 Execution Pipe Outputs
output dcc_dir_ex2_frc_align2;
output dcc_dir_ex2_frc_align4;
output dcc_dir_ex2_frc_align8;
output dcc_dir_ex2_frc_align16;
output dcc_dir_ex2_64bit_agen;
output [0:`THREADS-1] dcc_dir_ex2_thrd_id;
output dcc_derat_ex3_strg_noop;
output dcc_derat_ex5_blk_tlb_req; // Higher Priority Interrupt detected, block ERAT miss request from going to MMU
output [0:`THREADS-1] dcc_derat_ex6_cplt; // Completion report was sent for EMQ detected interrupts, EMQ entry can be freed
output [0:`ITAG_SIZE_ENC-1] dcc_derat_ex6_cplt_itag; // Completion report ITAG for EMQ detected interrupt
// EX3 Execution Pipe Outputs
output dcc_dir_ex3_lru_upd;
output dcc_dir_ex3_cache_acc; // Cache Access is Valid
output dcc_dir_ex3_pfetch_val;
output dcc_dir_ex3_lock_set; // DCBT[ST]LS Operation is valid
output dcc_dir_ex3_th_c; // DCBT[ST]LS Operation is targeting the L1 Data Cache
output dcc_dir_ex3_watch_set; // LDAWX Operation is valid
output dcc_dir_ex3_larx_val; // LARX Operation is valid, the directory should be invalidated if hit
output dcc_dir_ex3_watch_chk; // WCHK Operation is valid
output dcc_dir_ex3_ddir_acc;
output dcc_dir_ex4_load_val;
output dcc_spr_ex3_data_val;
output [64-(2**`GPR_WIDTH_ENC):63] dcc_spr_ex3_eff_addr;
output [0:4] ctl_dat_ex3_opsize;
output ctl_dat_ex3_le_mode;
output [0:3] ctl_dat_ex3_le_ld_rotsel;
output [0:3] ctl_dat_ex3_be_ld_rotsel;
output ctl_dat_ex3_algebraic;
output [0:3] ctl_dat_ex3_le_alg_rotsel;
// EX4 Execution Pipe Outputs
output dcc_byp_rel2_stg_act;
output dcc_byp_rel3_stg_act;
output dcc_byp_ram_act;
input byp_dcc_ex2_req_aborted;
output dcc_byp_ex4_moveOp_val;
output dcc_byp_stq6_moveOp_val;
output [64-(2**`GPR_WIDTH_ENC):63] dcc_byp_ex4_move_data;
output dcc_byp_ex5_lq_req_abort;
output [0:((2**`GPR_WIDTH_ENC)/8)-1] dcc_byp_ex5_byte_mask;
output [0:`THREADS-1] dcc_byp_ex6_thrd_id;
output dcc_byp_ex6_dvc1_en;
output dcc_byp_ex6_dvc2_en;
output [0:3] dcc_byp_ex6_dacr_cmpr;
output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dcc_dir_ex4_p_addr;
output dcc_dir_stq6_store_val;
// Execution Pipe Outputs
output [0:`THREADS-1] ctl_lsq_ex2_streq_val;
output [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag;
output [0:`THREADS-1] ctl_lsq_ex2_thrd_id;
output [0:`THREADS-1] ctl_lsq_ex3_ldreq_val;
output [0:`THREADS-1] ctl_lsq_ex3_wchkall_val;
output ctl_lsq_ex3_pfetch_val;
output [0:15] ctl_lsq_ex3_byte_en;
output [58:63] ctl_lsq_ex3_p_addr;
output [0:`THREADS-1] ctl_lsq_ex3_thrd_id;
output ctl_lsq_ex3_algebraic;
output [0:2] ctl_lsq_ex3_opsize;
output ctl_lsq_ex4_ldreq_val;
output ctl_lsq_ex4_binvreq_val;
output ctl_lsq_ex4_streq_val;
output ctl_lsq_ex4_othreq_val;
output [64-`REAL_IFAR_WIDTH:57] ctl_lsq_ex4_p_addr;
output ctl_lsq_ex4_dReq_val;
output ctl_lsq_ex4_gath_load;
output ctl_lsq_ex4_send_l2;
output ctl_lsq_ex4_has_data;
output ctl_lsq_ex4_cline_chk;
output [0:4] ctl_lsq_ex4_wimge;
output ctl_lsq_ex4_byte_swap;
output ctl_lsq_ex4_is_sync;
output ctl_lsq_ex4_all_thrd_chk;
output ctl_lsq_ex4_is_store;
output ctl_lsq_ex4_is_resv;
output ctl_lsq_ex4_is_mfgpr;
output ctl_lsq_ex4_is_icswxr;
output ctl_lsq_ex4_is_icbi;
output ctl_lsq_ex4_watch_clr;
output ctl_lsq_ex4_watch_clr_all;
output ctl_lsq_ex4_mtspr_trace;
output ctl_lsq_ex4_is_inval_op;
output ctl_lsq_ex4_is_cinval;
output ctl_lsq_ex5_lock_clr;
output ctl_lsq_ex5_lock_set;
output ctl_lsq_ex5_watch_set;
output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr;
output ctl_lsq_ex5_axu_val; // XU,AXU type operation
output ctl_lsq_ex5_is_epid;
output [0:3] ctl_lsq_ex5_usr_def;
output ctl_lsq_ex5_drop_rel; // L2 only instructions
output ctl_lsq_ex5_flush_req; // Flush request from LDQ/STQ
output ctl_lsq_ex5_flush_pfetch; // Flush Prefetch in EX5
output [0:10] ctl_lsq_ex5_cmmt_events;
output ctl_lsq_ex5_perf_val0;
output [0:3] ctl_lsq_ex5_perf_sel0;
output ctl_lsq_ex5_perf_val1;
output [0:3] ctl_lsq_ex5_perf_sel1;
output ctl_lsq_ex5_perf_val2;
output [0:3] ctl_lsq_ex5_perf_sel2;
output ctl_lsq_ex5_perf_val3;
output [0:3] ctl_lsq_ex5_perf_sel3;
output ctl_lsq_ex5_not_touch;
output [0:1] ctl_lsq_ex5_class_id;
output [0:1] ctl_lsq_ex5_dvc;
output [0:3] ctl_lsq_ex5_dacrw;
output [0:5] ctl_lsq_ex5_ttype;
output [0:1] ctl_lsq_ex5_l_fld;
output ctl_lsq_ex5_load_hit;
input [0:3] lsq_ctl_ex6_ldq_events; // LDQ Pipeline Performance Events
input [0:1] lsq_ctl_ex6_stq_events; // LDQ Pipeline Performance Events
output [0:26] ctl_lsq_stq3_icswx_data;
output [0:`THREADS-1] ctl_lsq_dbg_int_en;
output [0:`THREADS-1] ctl_lsq_ldp_idle;
// SPR Directory Read Valid
output ctl_lsq_rv1_dir_rd_val;
// Directory Read interface
output dcc_dec_arr_rd_rv1_val;
output [0:5] dcc_dec_arr_rd_congr_cl;
// MFTGPR instruction
output dcc_dec_stq3_mftgpr_val;
output dcc_dec_stq5_mftgpr_val;
// SPR status
output lq_xu_spr_xucr0_cul; // Cache Lock unable to lock
output [0:31] dcc_dir_spr_xucr2_rmt;
input spr_dcc_spr_xudbg0_exec; // Execute Directory Read
input [0:`THREADS-1] spr_dcc_spr_xudbg0_tid; // Directory Read Initiated by Thread
input [0:2] spr_dcc_spr_xudbg0_way; // Directory Read Way
input [0:5] spr_dcc_spr_xudbg0_row; // Directory Read Congruence Class
output dcc_spr_spr_xudbg0_done; // Directory Read Done
output dcc_spr_spr_xudbg1_valid; // Directory Valid State
output [0:3] dcc_spr_spr_xudbg1_watch; // Directory Watch State
output [0:3] dcc_spr_spr_xudbg1_parity; // Directory Parity
output [0:6] dcc_spr_spr_xudbg1_lru; // Directory LRU
output dcc_spr_spr_xudbg1_lock; // Directory Lock State
output [33:63] dcc_spr_spr_xudbg2_tag; // Directory Tag
input [32:63] spr_dcc_spr_xucr2_rmt; // RMT Table
input spr_dcc_spr_lsucr0_clchk; // Cacheline Check Enabled
input [0:(32*`THREADS)-1] spr_dcc_spr_acop_ct; // ACOP register for icswx
input [0:(32*`THREADS)-1] spr_dcc_spr_hacop_ct; // HACOP register for icswx
input [0:`THREADS-1] spr_dcc_epsc_epr;
input [0:`THREADS-1] spr_dcc_epsc_eas;
input [0:`THREADS-1] spr_dcc_epsc_egs;
input [0:(8*`THREADS)-1] spr_dcc_epsc_elpid;
input [0:(14*`THREADS)-1] spr_dcc_epsc_epid;
// Back-invalidate
output dcc_dir_ex2_binv_val;
// Update Data Array Valid
output stq4_dcarr_wren;
output dcc_byp_ram_sel;
output dcc_dec_ex5_wren;
output lq_xu_ex5_abort;
output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex5_wa;
output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_ex6_wa;
output lq_xu_axu_rel_we;
output lq_xu_gpr_rel_we;
output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa;
output lq_rv_gpr_rel_we;
output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_rel_wa;
output lq_xu_cr_ex5_we;
output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_ex5_wa;
output [0:`CR_WIDTH-1] lq_xu_ex5_cr;
// Interface with AXU PassThru with XU
output [59:63] lq_xu_axu_ex4_addr;
output lq_xu_axu_ex5_we;
output lq_xu_axu_ex5_le;
// Outputs to Reservation Station
output [0:`THREADS-1] lq_rv_itag1_vld;
output [0:`ITAG_SIZE_ENC-1] lq_rv_itag1;
output lq_rv_itag1_restart;
output lq_rv_itag1_abort;
output lq_rv_itag1_hold;
output lq_rv_itag1_cord;
output [0:`THREADS-1] lq_rv_clr_hold;
output dcc_dec_hold_all;
// Completion Report
output [0:`THREADS-1] lq0_iu_execute_vld;
output [0:`THREADS-1] lq0_iu_recirc_val;
output [0:`ITAG_SIZE_ENC-1] lq0_iu_itag;
output lq0_iu_flush2ucode;
output lq0_iu_flush2ucode_type;
output lq0_iu_exception_val;
output [0:5] lq0_iu_exception;
output [0:`THREADS-1] lq0_iu_dear_val;
output lq0_iu_n_flush;
output lq0_iu_np1_flush;
output lq0_iu_dacr_type;
output [0:3] lq0_iu_dacrw;
output [0:31] lq0_iu_instr;
output [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr;
// outputs to prefetch
output [64-(2**`GPR_WIDTH_ENC):59] dcc_pf_ex5_eff_addr;
output dcc_pf_ex5_req_val_4pf;
output dcc_pf_ex5_act;
output [0:`THREADS-1] dcc_pf_ex5_thrd_id;
output dcc_pf_ex5_loadmiss;
output [0:`ITAG_SIZE_ENC-1] dcc_pf_ex5_itag;
// Error Reporting
output lq_pc_err_derat_parity;
output lq_pc_err_dir_ldp_parity;
output lq_pc_err_dir_stp_parity;
output lq_pc_err_dcache_parity;
output lq_pc_err_derat_multihit;
output lq_pc_err_dir_ldp_multihit;
output lq_pc_err_dir_stp_multihit;
// Ram Mode Control
input [0:`THREADS-1] pc_lq_ram_active;
output lq_pc_ram_data_val;
// LQ Pervasive
output [0:18+`THREADS-1] ctl_perv_ex6_perf_events;
output [0:6+`THREADS-1] ctl_perv_stq4_perf_events;
// ACT's
output dcc_dir_ex2_stg_act;
output dcc_dir_ex3_stg_act;
output dcc_dir_ex4_stg_act;
output dcc_dir_ex5_stg_act;
output dcc_dir_stq1_stg_act;
output dcc_dir_stq2_stg_act;
output dcc_dir_stq3_stg_act;
output dcc_dir_stq4_stg_act;
output dcc_dir_stq5_stg_act;
output dcc_dir_binv2_ex2_stg_act;
output dcc_dir_binv3_ex3_stg_act;
output dcc_dir_binv4_ex4_stg_act;
output dcc_dir_binv5_ex5_stg_act;
output dcc_dir_binv6_ex6_stg_act;
// Pervasive
inout vdd;
inout gnd;
input clk;
input rst;
input sg_0;
input func_sl_thold_0_b;
input func_sl_force;
input func_nsl_thold_0_b;
input func_nsl_force;
input func_slp_sl_thold_0_b;
input func_slp_sl_force;
input func_slp_nsl_thold_0_b;
input func_slp_nsl_force;
input d_mode_dc;
input delay_lclkr_dc;
input mpw1_dc_b;
input mpw2_dc_b;
(* pin_data="PIN_FUNCTION=/SCAN_IN/" *)
input scan_in;
(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *)
output scan_out;
//--------------------------
// constants
//--------------------------
parameter TAGSIZE = ((63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH))+1;
parameter AXU_TARGET_ENC = `AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC;
//--------------------------
// components
//--------------------------
parameter [0:4] rot_max_size = 5'b10000;
//--------------------------
// signals
//--------------------------
wire [0:`THREADS-1] iu_lq_recirc_val_d;
wire [0:`THREADS-1] iu_lq_recirc_val_q;
wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_q[0:`THREADS-1];
wire [0:`THREADS-1] iu_lq_cp_flush_d;
wire [0:`THREADS-1] iu_lq_cp_flush_q;
wire [0:`THREADS-1] ex0_i0_vld_d;
wire [0:`THREADS-1] ex0_i0_vld_q;
wire ex0_i0_ucode_preissue_d;
wire ex0_i0_ucode_preissue_q;
wire ex0_i0_2ucode_d;
wire ex0_i0_2ucode_q;
wire [0:`UCODE_ENTRIES_ENC-1] ex0_i0_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] ex0_i0_ucode_cnt_q;
wire [0:`THREADS-1] ex0_i1_vld_d;
wire [0:`THREADS-1] ex0_i1_vld_q;
wire ex0_i1_ucode_preissue_d;
wire ex0_i1_ucode_preissue_q;
wire ex0_i1_2ucode_d;
wire ex0_i1_2ucode_q;
wire [0:`UCODE_ENTRIES_ENC-1] ex0_i1_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] ex0_i1_ucode_cnt_q;
wire [0:`THREADS-1] xer_lq_cp_rd_so_d;
wire [0:`THREADS-1] xer_lq_cp_rd_so_q;
wire ex2_optype1_d;
wire ex2_optype1_q;
wire ex3_optype1_d;
wire ex3_optype1_q;
wire ex2_optype2_d;
wire ex2_optype2_q;
wire ex3_optype2_d;
wire ex3_optype2_q;
wire ex2_optype4_d;
wire ex2_optype4_q;
wire ex3_optype4_d;
wire ex3_optype4_q;
wire ex2_optype8_d;
wire ex2_optype8_q;
wire ex3_optype8_d;
wire ex3_optype8_q;
wire ex2_optype16_d;
wire ex2_optype16_q;
wire ex3_optype16_d;
wire ex3_optype16_q;
wire ex3_dacr_type_d;
wire ex3_dacr_type_q;
wire ex4_dacr_type_d;
wire ex4_dacr_type_q;
wire ex5_dacr_type_d;
wire ex5_dacr_type_q;
wire ex2_cache_acc_d;
wire ex2_cache_acc_q;
wire ex3_cache_acc_d;
wire ex3_cache_acc_q;
wire ex4_cache_acc_d;
wire ex4_cache_acc_q;
wire ex5_cache_acc_d;
wire ex5_cache_acc_q;
wire ex6_cache_acc_d;
wire ex6_cache_acc_q;
wire [0:`THREADS-1] ex2_thrd_id_d;
wire [0:`THREADS-1] ex2_thrd_id_q;
wire [0:`THREADS-1] ex3_thrd_id_d;
wire [0:`THREADS-1] ex3_thrd_id_q;
wire [0:`THREADS-1] ex4_thrd_id_d;
wire [0:`THREADS-1] ex4_thrd_id_q;
wire [0:`THREADS-1] ex5_thrd_id_d;
wire [0:`THREADS-1] ex5_thrd_id_q;
wire [0:`THREADS-1] ex6_thrd_id_d;
wire [0:`THREADS-1] ex6_thrd_id_q;
wire [0:31] ex2_instr_d;
wire [0:31] ex2_instr_q;
wire [0:31] ex3_instr_d;
wire [0:31] ex3_instr_q;
wire [0:31] ex4_instr_d;
wire [0:31] ex4_instr_q;
wire [0:31] ex5_instr_d;
wire [0:31] ex5_instr_q;
wire [0:AXU_TARGET_ENC-1] ex2_target_gpr_d;
wire [0:AXU_TARGET_ENC-1] ex2_target_gpr_q;
wire [0:AXU_TARGET_ENC-1] ex3_target_gpr_d;
wire [0:AXU_TARGET_ENC-1] ex3_target_gpr_q;
wire [0:AXU_TARGET_ENC-1] ex4_target_gpr_d;
wire [0:AXU_TARGET_ENC-1] ex4_target_gpr_q;
wire [0:AXU_TARGET_ENC-1] ex5_target_gpr_d;
wire [0:AXU_TARGET_ENC-1] ex5_target_gpr_q;
wire ex2_dcbt_instr_d;
wire ex2_dcbt_instr_q;
wire ex3_dcbt_instr_d;
wire ex3_dcbt_instr_q;
wire ex4_dcbt_instr_d;
wire ex4_dcbt_instr_q;
wire ex2_pfetch_val_d;
wire ex2_pfetch_val_q;
wire ex3_pfetch_val_d;
wire ex3_pfetch_val_q;
wire ex4_pfetch_val_d;
wire ex4_pfetch_val_q;
wire ex5_pfetch_val_d;
wire ex5_pfetch_val_q;
wire ex6_pfetch_val_d;
wire ex6_pfetch_val_q;
wire [0:`THREADS-1] ldp_pfetch_inPipe;
wire ex2_dcbtst_instr_d;
wire ex2_dcbtst_instr_q;
wire ex3_dcbtst_instr_d;
wire ex3_dcbtst_instr_q;
wire ex4_dcbtst_instr_d;
wire ex4_dcbtst_instr_q;
wire ex2_store_instr_d;
wire ex2_store_instr_q;
wire ex2_wchk_instr_d;
wire ex2_wchk_instr_q;
wire ex3_wchk_instr_d;
wire ex3_wchk_instr_q;
wire ex4_wchk_instr_d;
wire ex4_wchk_instr_q;
wire ex2_dcbst_instr_d;
wire ex2_dcbst_instr_q;
wire ex3_dcbst_instr_d;
wire ex3_dcbst_instr_q;
wire ex4_dcbst_instr_d;
wire ex4_dcbst_instr_q;
wire ex2_dcbf_instr_d;
wire ex2_dcbf_instr_q;
wire ex3_dcbf_instr_d;
wire ex3_dcbf_instr_q;
wire ex4_dcbf_instr_d;
wire ex4_dcbf_instr_q;
wire ex2_mtspr_trace_d;
wire ex2_mtspr_trace_q;
wire ex3_mtspr_trace_d;
wire ex3_mtspr_trace_q;
wire ex4_mtspr_trace_d;
wire ex4_mtspr_trace_q;
wire ex2_sync_instr_d;
wire ex2_sync_instr_q;
wire ex3_sync_instr_d;
wire ex3_sync_instr_q;
wire ex4_sync_instr_d;
wire ex4_sync_instr_q;
wire [0:1] ex2_l_fld_d;
wire [0:1] ex2_l_fld_q;
wire [0:1] ex3_l_fld_d;
wire [0:1] ex3_l_fld_q;
wire [0:1] ex4_l_fld_d;
wire [0:1] ex4_l_fld_q;
wire [0:1] ex5_l_fld_d;
wire [0:1] ex5_l_fld_q;
wire [0:3] ex3_l_fld_sel;
wire [0:1] ex3_l_fld_mbar;
wire [0:1] ex3_l_fld_sync;
wire [0:1] ex3_l_fld_tlbsync;
wire [0:1] ex3_l_fld_makeitso;
wire [0:1] ex3_l_fld;
wire ex2_dcbi_instr_d;
wire ex2_dcbi_instr_q;
wire ex3_dcbi_instr_d;
wire ex3_dcbi_instr_q;
wire ex4_dcbi_instr_d;
wire ex4_dcbi_instr_q;
wire ex2_dcbz_instr_d;
wire ex2_dcbz_instr_q;
wire ex3_dcbz_instr_d;
wire ex3_dcbz_instr_q;
wire ex4_dcbz_instr_d;
wire ex4_dcbz_instr_q;
wire ex2_icbi_instr_d;
wire ex2_icbi_instr_q;
wire ex3_icbi_instr_d;
wire ex3_icbi_instr_q;
wire ex4_icbi_instr_d;
wire ex4_icbi_instr_q;
wire ex2_mbar_instr_d;
wire ex2_mbar_instr_q;
wire ex3_mbar_instr_d;
wire ex3_mbar_instr_q;
wire ex4_mbar_instr_d;
wire ex4_mbar_instr_q;
wire ex2_makeitso_instr_d;
wire ex2_makeitso_instr_q;
wire ex3_makeitso_instr_d;
wire ex3_makeitso_instr_q;
wire ex4_makeitso_instr_d;
wire ex4_makeitso_instr_q;
wire ex2_dci_instr_d;
wire ex2_dci_instr_q;
wire ex3_dci_instr_d;
wire ex3_dci_instr_q;
wire ex4_dci_instr_d;
wire ex4_dci_instr_q;
wire ex4_dci_l2_val;
wire ex4_is_cinval;
wire ex4_is_cinval_drop;
wire ex2_ici_instr_d;
wire ex2_ici_instr_q;
wire ex3_ici_instr_d;
wire ex3_ici_instr_q;
wire ex4_ici_instr_d;
wire ex4_ici_instr_q;
wire ex4_ici_l2_val;
wire ex2_resv_instr_d;
wire ex2_resv_instr_q;
wire ex3_resv_instr_d;
wire ex3_resv_instr_q;
wire ex4_resv_instr_d;
wire ex4_resv_instr_q;
wire ex2_load_instr_d;
wire ex2_load_instr_q;
wire ex3_load_instr_d;
wire ex3_load_instr_q;
wire ex4_load_instr_d;
wire ex4_load_instr_q;
wire ex3_load_type;
wire ex4_load_type_d;
wire ex4_load_type_q;
wire ex4_gath_load_d;
wire ex4_gath_load_q;
wire ex3_store_instr_d;
wire ex3_store_instr_q;
wire ex4_store_instr_d;
wire ex4_store_instr_q;
wire ex3_le_mode;
wire ex4_le_mode_d;
wire ex4_le_mode_q;
wire ex5_wimge_i_bits_d;
wire ex5_wimge_i_bits_q;
wire [0:3] ex5_usr_bits_d;
wire [0:3] ex5_usr_bits_q;
wire [0:1] ex5_classid_d;
wire [0:1] ex5_classid_q;
wire ex5_derat_setHold_d;
wire ex5_derat_setHold_q;
wire ex3_icswx_type;
wire ex4_icswx_type;
wire ex4_stx_instr;
wire ex4_larx_instr;
wire is_mem_bar_op;
wire is_inval_op;
wire ex3_l1_lock_set;
wire is_lock_clr;
wire ex3_lru_upd;
wire stq6_tgpr_val;
wire [0:AXU_TARGET_ENC-1] reg_upd_ta_gpr;
wire lq_wren;
wire ex5_lq_wren;
wire ex5_lq_wren_d;
wire ex5_lq_wren_q;
wire ex6_lq_wren_d;
wire ex6_lq_wren_q;
wire axu_wren;
wire rel2_axu_wren_d;
wire rel2_axu_wren_q;
wire stq2_axu_val_d;
wire stq2_axu_val_q;
wire stq3_axu_val_d;
wire stq3_axu_val_q;
wire stq4_axu_val_d;
wire stq4_axu_val_q;
wire stq3_store_hit;
wire stq3_store_miss;
wire stq4_store_hit_d;
wire stq4_store_hit_q;
wire stq5_store_hit_d;
wire stq5_store_hit_q;
wire stq6_store_hit_d;
wire stq6_store_hit_q;
wire ex4_load_hit;
wire ex4_load_miss;
wire ex5_load_miss_d;
wire ex5_load_miss_q;
wire ex5_load_hit_d;
wire ex5_load_hit_q;
wire ex6_load_hit_d;
wire ex6_load_hit_q;
wire ex2_axu_op_val_d;
wire ex2_axu_op_val_q;
wire ex3_axu_op_val_d;
wire ex3_axu_op_val_q;
wire ex4_axu_op_val_d;
wire ex4_axu_op_val_q;
wire ex5_axu_op_val_d;
wire ex5_axu_op_val_q;
wire ex2_upd_form_d;
wire ex2_upd_form_q;
wire ex3_upd_form_d;
wire ex3_upd_form_q;
wire [0:2] ex2_axu_instr_type_d;
wire [0:2] ex2_axu_instr_type_q;
wire [0:2] ex3_axu_instr_type_d;
wire [0:2] ex3_axu_instr_type_q;
wire ex5_axu_wren_d;
wire ex5_axu_wren_q;
wire ex6_axu_wren_d;
wire ex6_axu_wren_q;
wire [0:AXU_TARGET_ENC-1] ex5_lq_ta_gpr_d;
wire [0:AXU_TARGET_ENC-1] ex5_lq_ta_gpr_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ex6_lq_ta_gpr_d;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ex6_lq_ta_gpr_q;
wire ex5_load_le_d;
wire ex5_load_le_q;
wire ex2_algebraic_d;
wire ex2_algebraic_q;
wire ex3_algebraic_d;
wire ex3_algebraic_q;
wire ex2_strg_index_d;
wire ex2_strg_index_q;
wire ex3_strg_index_d;
wire ex3_strg_index_q;
wire ex4_strg_index_d;
wire ex4_strg_index_q;
wire ex4_nogpr_upd;
wire ex1_th_b0;
wire ex2_th_fld_c_d;
wire ex2_th_fld_c_q;
wire ex3_th_fld_c_d;
wire ex3_th_fld_c_q;
wire ex4_th_fld_c_d;
wire ex4_th_fld_c_q;
wire ex2_th_fld_l2_d;
wire ex2_th_fld_l2_q;
wire ex3_th_fld_l2_d;
wire ex3_th_fld_l2_q;
wire ex4_th_fld_l2_d;
wire ex4_th_fld_l2_q;
wire ex2_undef_touch;
wire ex3_undef_touch_d;
wire ex3_undef_touch_q;
wire ex4_undef_touch_d;
wire ex4_undef_touch_q;
wire ex2_dcbtls_instr_d;
wire ex2_dcbtls_instr_q;
wire ex3_dcbtls_instr_d;
wire ex3_dcbtls_instr_q;
wire ex4_dcbtls_instr_d;
wire ex4_dcbtls_instr_q;
wire ex2_dcbtstls_instr_d;
wire ex2_dcbtstls_instr_q;
wire ex3_dcbtstls_instr_d;
wire ex3_dcbtstls_instr_q;
wire ex4_dcbtstls_instr_d;
wire ex4_dcbtstls_instr_q;
wire ex2_dcblc_instr_d;
wire ex2_dcblc_instr_q;
wire ex3_dcblc_instr_d;
wire ex3_dcblc_instr_q;
wire ex4_dcblc_instr_d;
wire ex4_dcblc_instr_q;
wire ex2_icblc_l2_instr_d;
wire ex2_icblc_l2_instr_q;
wire ex3_icblc_l2_instr_d;
wire ex3_icblc_l2_instr_q;
wire ex4_icblc_l2_instr_d;
wire ex4_icblc_l2_instr_q;
wire ex2_icbt_l2_instr_d;
wire ex2_icbt_l2_instr_q;
wire ex3_icbt_l2_instr_d;
wire ex3_icbt_l2_instr_q;
wire ex4_icbt_l2_instr_d;
wire ex4_icbt_l2_instr_q;
wire ex2_icbtls_l2_instr_d;
wire ex2_icbtls_l2_instr_q;
wire ex3_icbtls_l2_instr_d;
wire ex3_icbtls_l2_instr_q;
wire ex4_icbtls_l2_instr_d;
wire ex4_icbtls_l2_instr_q;
wire ex2_tlbsync_instr_d;
wire ex2_tlbsync_instr_q;
wire ex3_tlbsync_instr_d;
wire ex3_tlbsync_instr_q;
wire ex4_tlbsync_instr_d;
wire ex4_tlbsync_instr_q;
wire ex2_ldst_falign_d;
wire ex2_ldst_falign_q;
wire ex2_ldst_fexcpt_d;
wire ex2_ldst_fexcpt_q;
wire ex3_ldst_fexcpt_d;
wire ex3_ldst_fexcpt_q;
wire [0:8+`THREADS] xudbg1_dir_reg_d;
wire [0:8+`THREADS] xudbg1_dir_reg_q;
wire [0:PARBITS-1] xudbg1_parity_reg_d;
wire [0:PARBITS-1] xudbg1_parity_reg_q;
wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] xudbg2_tag_d;
wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] xudbg2_tag_q;
wire [0:24] epsc_t_reg[0:`THREADS-1];
wire [0:23] lesr_t_reg[0:`THREADS-1];
wire [0:31] way_lck_rmt;
wire spr_ccr2_ap_d;
wire spr_ccr2_ap_q;
wire spr_ccr2_en_trace_d;
wire spr_ccr2_en_trace_q;
wire spr_ccr2_ucode_dis_d;
wire spr_ccr2_ucode_dis_q;
wire spr_ccr2_notlb_d;
wire spr_ccr2_notlb_q;
wire clkg_ctl_override_d;
wire clkg_ctl_override_q;
wire spr_xucr0_wlk_d;
wire spr_xucr0_wlk_q;
wire spr_xucr0_mbar_ack_d;
wire spr_xucr0_mbar_ack_q;
wire spr_xucr0_tlbsync_d;
wire spr_xucr0_tlbsync_q;
wire spr_xucr0_dcdis_d;
wire spr_xucr0_dcdis_q;
wire spr_xucr0_aflsta_d;
wire spr_xucr0_aflsta_q;
wire spr_xucr0_flsta_d;
wire spr_xucr0_flsta_q;
wire spr_xucr0_mddp_d;
wire spr_xucr0_mddp_q;
wire spr_xucr0_mdcp_d;
wire spr_xucr0_mdcp_q;
wire spr_xucr4_mmu_mchk_d;
wire spr_xucr4_mmu_mchk_q;
wire spr_xucr4_mddmh_d;
wire spr_xucr4_mddmh_q;
wire [0:`THREADS-1] spr_xucr0_en_trace_um_d;
wire [0:`THREADS-1] spr_xucr0_en_trace_um_q;
wire ex4_mtspr_trace_tid_en;
wire ex4_mtspr_trace_en;
wire ex4_mtspr_trace_dis;
wire ex1_lsu_64bit_mode;
wire [0:`THREADS-1] ex1_lsu_64bit_mode_d;
wire [0:`THREADS-1] ex1_lsu_64bit_mode_q;
wire ex2_lsu_64bit_agen_d;
wire ex2_lsu_64bit_agen_q;
wire ex3_lsu_64bit_agen_d;
wire ex3_lsu_64bit_agen_q;
wire ex4_lsu_64bit_agen_d;
wire ex4_lsu_64bit_agen_q;
wire stq4_dcarr_wren_d;
wire stq4_dcarr_wren_q;
wire ex2_sgpr_instr_d;
wire ex2_sgpr_instr_q;
wire ex2_saxu_instr_d;
wire ex2_saxu_instr_q;
wire ex2_sdp_instr_d;
wire ex2_sdp_instr_q;
wire ex2_tgpr_instr_d;
wire ex2_tgpr_instr_q;
wire ex2_taxu_instr_d;
wire ex2_taxu_instr_q;
wire ex2_tdp_instr_d;
wire ex2_tdp_instr_q;
wire ex3_sgpr_instr_d;
wire ex3_sgpr_instr_q;
wire ex3_saxu_instr_d;
wire ex3_saxu_instr_q;
wire ex3_sdp_instr_d;
wire ex3_sdp_instr_q;
wire ex3_tgpr_instr_d;
wire ex3_tgpr_instr_q;
wire ex3_taxu_instr_d;
wire ex3_taxu_instr_q;
wire ex3_tdp_instr_d;
wire ex3_tdp_instr_q;
wire ex4_sgpr_instr_d;
wire ex4_sgpr_instr_q;
wire ex4_saxu_instr_d;
wire ex4_saxu_instr_q;
wire ex4_sdp_instr_d;
wire ex4_sdp_instr_q;
wire ex4_tgpr_instr_d;
wire ex4_tgpr_instr_q;
wire ex4_taxu_instr_d;
wire ex4_taxu_instr_q;
wire ex4_tdp_instr_d;
wire ex4_tdp_instr_q;
wire ex4_mfdpa_val;
wire ex4_mfdpf_val;
wire ex4_ditc_val;
wire ex3_mffgpr_val;
wire ex4_mffgpr_val;
wire ex4_mftgpr_val;
wire ex5_mftgpr_val_d;
wire ex5_mftgpr_val_q;
wire ex2_mftgpr_val;
wire ex3_mftgpr_val;
wire ex3_mfgpr_val;
wire ex4_moveOp_val_d;
wire ex4_moveOp_val_q;
wire stq6_moveOp_val_d;
wire stq6_moveOp_val_q;
wire data_touch_op;
wire inst_touch_op;
wire all_touch_op;
wire ddir_acc_instr;
wire ex4_c_dcbtls;
wire ex4_c_dcbtstls;
wire ex4_c_icbtls;
wire ex4_l2_dcbtls;
wire ex4_l2_dcbtstls;
wire ex4_l2_icbtls;
wire ex4_l2_icblc;
wire ex4_l2_dcblc;
wire ex4_blkable_touch_d;
wire ex4_blkable_touch_q;
wire ex5_blk_touch_d;
wire ex5_blk_touch_q;
wire ex6_blk_touch_d;
wire ex6_blk_touch_q;
wire ex4_excp_touch;
wire ex4_cinh_touch;
wire ex4_blk_touch;
wire ex4_blk_touch_instr;
wire ex3_local_dcbf;
wire ex2_mutex_hint_d;
wire ex2_mutex_hint_q;
wire ex3_mutex_hint_d;
wire ex3_mutex_hint_q;
wire ex4_mutex_hint_d;
wire ex4_mutex_hint_q;
wire [64-`REAL_IFAR_WIDTH:63] ex4_p_addr;
wire [64-(2**`GPR_WIDTH_ENC):63] ex3_eff_addr_d;
wire [64-(2**`GPR_WIDTH_ENC):63] ex3_eff_addr_q;
wire [64-(2**`GPR_WIDTH_ENC):63] ex4_eff_addr_d;
wire [64-(2**`GPR_WIDTH_ENC):63] ex4_eff_addr_q;
wire [64-(2**`GPR_WIDTH_ENC):63] ex5_eff_addr_d;
wire [64-(2**`GPR_WIDTH_ENC):63] ex5_eff_addr_q;
wire ex2_lockset_instr;
wire ex3_undef_lockset_d;
wire ex3_undef_lockset_q;
wire ex4_undef_lockset_d;
wire ex4_undef_lockset_q;
wire ex4_cinh_lockset;
wire ex4_l1dc_dis_lockset;
wire ex4_l1dc_dis_lockclr;
wire ex4_noop_lockset;
wire ex5_unable_2lock_d;
wire ex5_unable_2lock_q;
wire ex6_stq5_unable_2lock_d;
wire ex6_stq5_unable_2lock_q;
wire ex2_stq_val_cacc;
wire ex2_stq_nval_cacc;
wire ex2_stq_val_req;
wire ex3_stq_val_req_d;
wire ex3_stq_val_req_q;
wire ex4_stq_val_req_d;
wire ex4_stq_val_req_q;
wire ex5_load_instr_d;
wire ex5_load_instr_q;
wire ex2_mword_instr_d;
wire ex2_mword_instr_q;
wire ex3_mword_instr_d;
wire ex3_mword_instr_q;
wire stq4_store_miss_d;
wire stq4_store_miss_q;
wire ex5_perf_dcbt_d;
wire ex5_perf_dcbt_q;
reg [0:23] ex5_spr_lesr;
wire perf_stq_stores;
wire perf_stq_store_miss;
wire perf_stq_stcx_exec;
wire perf_stq_axu_store;
wire perf_stq_wclr;
wire perf_stq_wclr_set;
wire perf_com_loadmiss;
wire perf_com_cinh_loads;
wire perf_com_loads;
wire perf_com_dcbt_sent;
wire perf_com_dcbt_hit;
wire perf_com_axu_load;
wire perf_com_load_fwd;
wire perf_ex6_pfetch_iss;
wire perf_ex6_pfetch_hit;
wire perf_ex6_pfetch_emiss;
wire perf_ex6_align_flush;
wire perf_ex6_dir_restart;
wire perf_ex6_dec_restart;
wire perf_ex6_wNComp_restart;
wire perf_ex6_pfetch_ldq_full;
wire perf_ex6_pfetch_ldq_hit;
wire perf_ex6_pfetch_stq;
wire perf_ex6_ldq_full;
wire perf_ex6_ldq_hit;
wire perf_ex6_lgq_full;
wire perf_ex6_lgq_hit;
wire perf_ex6_stq_sametid;
wire perf_ex6_stq_difftid;
wire perf_ex6_derat_attmpts;
wire [0:10] ex5_cmmt_events;
wire [0:6+`THREADS-1] stq_perf_events;
wire [0:18+`THREADS-1] ex6_dcc_perf_events;
wire perf_com_watch_set;
wire perf_com_watch_dup;
wire perf_com_wchkall;
wire perf_com_wchkall_succ;
wire ex3_watch_clr_entry;
wire ex3_watch_clr_all;
wire ex4_local_dcbf_d;
wire ex4_local_dcbf_q;
wire ex2_msgsnd_instr_d;
wire ex2_msgsnd_instr_q;
wire ex3_msgsnd_instr_d;
wire ex3_msgsnd_instr_q;
wire ex4_msgsnd_instr_d;
wire ex4_msgsnd_instr_q;
wire ex4_l2load_type_d;
wire ex4_l2load_type_q;
wire ex2_ldawx_instr_d;
wire ex2_ldawx_instr_q;
wire ex3_ldawx_instr_d;
wire ex3_ldawx_instr_q;
wire ex4_ldawx_instr_d;
wire ex4_ldawx_instr_q;
wire ex5_ldawx_instr_d;
wire ex5_ldawx_instr_q;
wire ex2_wclr_instr_d;
wire ex2_wclr_instr_q;
wire ex3_wclr_instr_d;
wire ex3_wclr_instr_q;
wire ex4_wclr_instr_d;
wire ex4_wclr_instr_q;
wire ex4_wclr_all_val;
wire [0:4] ex3_opsize;
wire [0:2] ex3_opsize_enc;
wire [0:2] ex4_opsize_enc_d;
wire [0:2] ex4_opsize_enc_q;
wire [0:2] ex5_opsize_enc_d;
wire [0:2] ex5_opsize_enc_q;
wire [1:4] ex5_opsize;
wire [0:7] ex5_byte_mask;
wire [0:4] ex3_rot_size;
wire [0:4] ex3_rot_sel_non_le;
wire [0:4] ex3_alg_bit_le_sel;
wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q;
wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q;
wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q;
wire [0:`ITAG_SIZE_ENC-1] ex5_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex5_itag_q;
wire [0:`ITAG_SIZE_ENC-1] ex6_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex6_itag_q;
wire ex5_drop_rel_d;
wire ex5_drop_rel_q;
wire ex2_icswx_instr_d;
wire ex2_icswx_instr_q;
wire ex3_icswx_instr_d;
wire ex3_icswx_instr_q;
wire ex4_icswx_instr_d;
wire ex4_icswx_instr_q;
wire ex2_icswxdot_instr_d;
wire ex2_icswxdot_instr_q;
wire ex3_icswxdot_instr_d;
wire ex3_icswxdot_instr_q;
wire ex4_icswxdot_instr_d;
wire ex4_icswxdot_instr_q;
wire ex2_icswx_epid_d;
wire ex2_icswx_epid_q;
wire ex3_icswx_epid_d;
wire ex3_icswx_epid_q;
wire ex4_icswx_epid_d;
wire ex4_icswx_epid_q;
wire ex5_icswx_epid_d;
wire ex5_icswx_epid_q;
wire ex4_c_inh_drop_op_d;
wire ex4_c_inh_drop_op_q;
wire ex4_cache_enabled;
wire ex4_cache_inhibited;
wire [0:8] ex4_mem_attr;
wire [0:AXU_TARGET_ENC-1] rel2_ta_gpr_d;
wire [0:AXU_TARGET_ENC-1] rel2_ta_gpr_q;
wire rv1_binv_val_d;
wire rv1_binv_val_q;
wire ex0_binv_val_d;
wire ex0_binv_val_q;
wire ex1_binv_val_d;
wire ex1_binv_val_q;
wire ex2_binv_val_d;
wire ex2_binv_val_q;
wire ex3_binv_val_d;
wire ex3_binv_val_q;
wire ex4_binv_val_d;
wire ex4_binv_val_q;
wire ex0_derat_snoop_val_d;
wire ex0_derat_snoop_val_q;
wire ex1_derat_snoop_val_d;
wire ex1_derat_snoop_val_q;
wire spr_msr_fp;
wire [0:`THREADS-1] spr_msr_fp_d;
wire [0:`THREADS-1] spr_msr_fp_q;
wire spr_msr_spv;
wire [0:`THREADS-1] spr_msr_spv_d;
wire [0:`THREADS-1] spr_msr_spv_q;
wire [0:`THREADS-1] spr_msr_gs_d;
wire [0:`THREADS-1] spr_msr_gs_q;
wire [0:`THREADS-1] spr_msr_pr_d;
wire [0:`THREADS-1] spr_msr_pr_q;
wire [0:`THREADS-1] spr_msr_ds_d;
wire [0:`THREADS-1] spr_msr_ds_q;
wire [0:`THREADS-1] spr_msr_de_d;
wire [0:`THREADS-1] spr_msr_de_q;
wire [0:`THREADS-1] spr_dbcr0_idm_d;
wire [0:`THREADS-1] spr_dbcr0_idm_q;
wire [0:`THREADS-1] spr_epcr_duvd_d;
wire [0:`THREADS-1] spr_epcr_duvd_q;
wire [0:7] spr_lpidr_d;
wire [0:7] spr_lpidr_q;
wire [0:13] spr_pid_d[0:`THREADS-1];
wire [0:13] spr_pid_q[0:`THREADS-1];
wire [0:31] spr_acop_ct[0:`THREADS-1];
wire [0:31] spr_hacop_ct[0:`THREADS-1];
wire ex2_epsc_egs;
wire ex2_epsc_epr;
wire ex2_msr_gs;
wire ex2_msr_pr;
wire ex3_icswx_gs_d;
wire ex3_icswx_gs_q;
wire ex3_icswx_pr_d;
wire ex3_icswx_pr_q;
wire ex4_icswx_ct_val_d;
wire ex4_icswx_ct_val_q;
reg [32:63] ex3_acop_ct;
reg [32:63] ex3_hacop_ct;
wire [32:63] ex3_acop_ct_npr;
wire [32:63] ex3_cop_ct;
wire [0:1] ex3_icswx_ct;
wire [0:1] ex4_icswx_ct_d;
wire [0:1] ex4_icswx_ct_q;
wire ex4_icswx_ct;
wire ex4_icswx_dsi;
wire [0:`THREADS-1] dbg_int_en_d;
wire [0:`THREADS-1] dbg_int_en_q;
reg [0:13] stq2_pid;
reg [0:24] stq2_epsc;
wire [0:24] stq2_icswx_epid;
wire [0:24] stq2_icswx_nepid;
wire [0:24] stq3_icswx_data_d;
wire [0:24] stq3_icswx_data_q;
wire ex4_spr_msr_pr;
wire [0:`THREADS-1] hypervisor_state;
wire ex4_load_val;
wire [0:5] ex5_ttype_d;
wire [0:5] ex5_ttype_q;
wire ex4_store_val;
wire ex4_othreq_val;
wire ex3_illeg_lswx;
wire ex3_strg_index_noop;
wire ex4_strg_gate_d;
wire ex4_strg_gate_q;
wire ex3_wNComp;
wire [0:`THREADS-1] ex3_wNComp_tid;
wire ex3_wNComp_rcvd;
wire ex4_wNComp_rcvd_d;
wire ex4_wNComp_rcvd_q;
wire ex4_wNComp_d;
wire ex4_wNComp_q;
wire ex5_wNComp_d;
wire ex5_wNComp_q;
wire ex5_wNComp_cr_upd_d;
wire ex5_wNComp_cr_upd_q;
wire ex4_wNComp_excp_restart;
wire ex4_2younger_restart;
wire ex5_flush_req;
wire ex5_blk_tlb_req;
wire ex5_flush_pfetch;
wire [0:1] ex5_dvc_en_d;
wire [0:1] ex5_dvc_en_q;
wire [0:1] ex6_dvc_en_d;
wire [0:1] ex6_dvc_en_q;
wire ex4_is_inval_op_d;
wire ex4_is_inval_op_q;
wire [0:15] op_sel;
wire [0:15] beC840_en;
wire [0:15] be3210_en;
wire [0:15] byte_en;
wire [0:15] ex3_byte_en;
wire ex2_sfx_val_d;
wire ex2_sfx_val_q;
wire ex3_sfx_val_d;
wire ex3_sfx_val_q;
wire ex4_sfx_val_d;
wire ex4_sfx_val_q;
wire ex2_ucode_val_d;
wire ex2_ucode_val_q;
wire ex3_ucode_val_d;
wire ex3_ucode_val_q;
wire ex4_ucode_val_d;
wire ex4_ucode_val_q;
wire ex6_lq_comp_rpt_d;
wire ex6_lq_comp_rpt_q;
wire [0:`THREADS-1] lq0_iu_execute_vld_d;
wire [0:`THREADS-1] lq0_iu_execute_vld_q;
wire [0:`ITAG_SIZE_ENC-1] lq0_iu_itag_d;
wire [0:`ITAG_SIZE_ENC-1] lq0_iu_itag_q;
wire lq0_iu_flush2ucode_type_d;
wire lq0_iu_flush2ucode_type_q;
wire [0:`THREADS-1] lq0_iu_recirc_val_d;
wire [0:`THREADS-1] lq0_iu_recirc_val_q;
wire lq0_iu_flush2ucode_d;
wire lq0_iu_flush2ucode_q;
wire [0:`THREADS-1] lq0_iu_dear_val_d;
wire [0:`THREADS-1] lq0_iu_dear_val_q;
wire [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr_d;
wire [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr_q;
wire lq0_iu_n_flush_d;
wire lq0_iu_n_flush_q;
wire lq0_iu_np1_flush_d;
wire lq0_iu_np1_flush_q;
wire lq0_iu_exception_val_d;
wire lq0_iu_exception_val_q;
wire [0:5] lq0_iu_exception_d;
wire [0:5] lq0_iu_exception_q;
wire lq0_iu_dacr_type_d;
wire lq0_iu_dacr_type_q;
wire [0:3] lq0_iu_dacrw_d;
wire [0:3] lq0_iu_dacrw_q;
wire [0:31] lq0_iu_instr_d;
wire [0:31] lq0_iu_instr_q;
wire ex4_spec_load_miss;
wire ex5_spec_load_miss_d;
wire ex5_spec_load_miss_q;
wire ex5_spec_itag_vld_d;
wire ex5_spec_itag_vld_q;
wire [0:`ITAG_SIZE_ENC-1] ex4_spec_itag;
wire [0:`THREADS-1] ex4_spec_thrd_id;
wire [0:`ITAG_SIZE_ENC-1] ex5_spec_itag_d;
wire [0:`ITAG_SIZE_ENC-1] ex5_spec_itag_q;
wire [0:`THREADS-1] ex5_spec_tid_d;
wire [0:`THREADS-1] ex5_spec_tid_q;
wire ex4_guarded_load;
wire ex5_blk_pf_load_d;
wire ex5_blk_pf_load_q;
wire ex4_lq_wNComp_req;
wire ex4_wNcomp_oth;
wire ex4_wNComp_req;
wire ex5_lq_wNComp_val_d;
wire ex5_lq_wNComp_val_q;
wire ex6_lq_wNComp_val_d;
wire ex6_lq_wNComp_val_q;
wire ex5_wNComp_ord_d;
wire ex5_wNComp_ord_q;
wire ex3_lswx_restart;
wire ex4_lswx_restart_d;
wire ex4_lswx_restart_q;
wire ex3_icswx_restart;
wire ex4_icswx_restart_d;
wire ex4_icswx_restart_q;
wire ex4_restart_val;
wire ex5_restart_val_d;
wire ex5_restart_val_q;
wire ex5_derat_restart_d;
wire ex5_derat_restart_q;
wire ex6_derat_restart_d;
wire ex6_derat_restart_q;
wire ex5_dir_restart_d;
wire ex5_dir_restart_q;
wire ex6_dir_restart_d;
wire ex6_dir_restart_q;
wire ex5_dec_restart_d;
wire ex5_dec_restart_q;
wire ex6_dec_restart_d;
wire ex6_dec_restart_q;
wire ex4_derat_itagHit_d;
wire ex4_derat_itagHit_q;
wire ex6_stq_restart_val_d;
wire ex6_stq_restart_val_q;
wire ex6_restart_val_d;
wire ex6_restart_val_q;
wire ex5_execute_vld;
wire ex5_execute_vld_d;
wire ex5_execute_vld_q;
wire ex5_flush2ucode_type_d;
wire ex5_flush2ucode_type_q;
wire ex5_recirc_val;
wire ex5_recirc_val_d;
wire ex5_recirc_val_q;
wire [0:`THREADS-1] lq0_rpt_thrd_id;
wire ex5_wchkall_cplt;
wire ex5_wchkall_cplt_d;
wire ex5_wchkall_cplt_q;
wire ex6_misalign_flush_d;
wire ex6_misalign_flush_q;
wire [0:`THREADS-1] ldq_idle_d;
wire [0:`THREADS-1] ldq_idle_q;
wire ex5_lq_comp_rpt_val;
wire ex5_restart_val;
wire ex5_lq_req_abort;
wire ex5_ldq_restart_val;
wire ex5_stq_restart_miss;
wire ex5_stq_restart_val;
wire ex4_is_sync_d;
wire ex4_is_sync_q;
wire ex4_l1_lock_set_d;
wire ex4_l1_lock_set_q;
wire ex5_l1_lock_set_d;
wire ex5_l1_lock_set_q;
wire ex4_lock_clr_d;
wire ex4_lock_clr_q;
wire ex5_lock_clr_d;
wire ex5_lock_clr_q;
wire rel2_xu_wren_d;
wire rel2_xu_wren_q;
wire stq2_store_val_d;
wire stq2_store_val_q;
wire stq3_store_val_d;
wire stq3_store_val_q;
wire stq4_store_val_d;
wire stq4_store_val_q;
wire stq2_ci_d;
wire stq2_ci_q;
wire stq3_ci_d;
wire stq3_ci_q;
wire stq2_resv_d;
wire stq2_resv_q;
wire stq3_resv_d;
wire stq3_resv_q;
wire stq2_wclr_val_d;
wire stq2_wclr_val_q;
wire stq3_wclr_val_d;
wire stq3_wclr_val_q;
wire stq4_wclr_val_d;
wire stq4_wclr_val_q;
wire stq2_wclr_all_set_d;
wire stq2_wclr_all_set_q;
wire stq3_wclr_all_set_d;
wire stq3_wclr_all_set_q;
wire stq4_wclr_all_set_d;
wire stq4_wclr_all_set_q;
wire stq4_rec_stcx_d;
wire stq4_rec_stcx_q;
wire [0:`ITAG_SIZE_ENC-1] stq6_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stq6_itag_q;
wire [0:AXU_TARGET_ENC-1] stq6_tgpr_d;
wire [0:AXU_TARGET_ENC-1] stq6_tgpr_q;
wire [0:`THREADS-1] stq2_thrd_id_d;
wire [0:`THREADS-1] stq2_thrd_id_q;
wire [0:`THREADS-1] stq3_thrd_id_d;
wire [0:`THREADS-1] stq3_thrd_id_q;
wire [0:`THREADS-1] stq4_thrd_id_d;
wire [0:`THREADS-1] stq4_thrd_id_q;
wire [0:`THREADS-1] stq5_thrd_id_d;
wire [0:`THREADS-1] stq5_thrd_id_q;
wire [0:`THREADS-1] stq6_thrd_id_d;
wire [0:`THREADS-1] stq6_thrd_id_q;
wire [0:`THREADS-1] stq7_thrd_id_d;
wire [0:`THREADS-1] stq7_thrd_id_q;
wire [0:`THREADS-1] stq8_thrd_id_d;
wire [0:`THREADS-1] stq8_thrd_id_q;
wire stq2_epid_val_d;
wire stq2_epid_val_q;
wire stq2_mftgpr_val_d;
wire stq2_mftgpr_val_q;
wire stq3_mftgpr_val_d;
wire stq3_mftgpr_val_q;
wire stq4_mftgpr_val_d;
wire stq4_mftgpr_val_q;
wire stq5_mftgpr_val_d;
wire stq5_mftgpr_val_q;
wire stq6_mftgpr_val_d;
wire stq6_mftgpr_val_q;
wire stq7_mftgpr_val_d;
wire stq7_mftgpr_val_q;
wire stq8_mftgpr_val_d;
wire stq8_mftgpr_val_q;
wire stq2_mfdpf_val_d;
wire stq2_mfdpf_val_q;
wire stq3_mfdpf_val_d;
wire stq3_mfdpf_val_q;
wire stq4_mfdpf_val_d;
wire stq4_mfdpf_val_q;
wire stq5_mfdpf_val_d;
wire stq5_mfdpf_val_q;
wire stq2_mfdpa_val_d;
wire stq2_mfdpa_val_q;
wire stq3_mfdpa_val_d;
wire stq3_mfdpa_val_q;
wire stq4_mfdpa_val_d;
wire stq4_mfdpa_val_q;
wire stq5_mfdpa_val_d;
wire stq5_mfdpa_val_q;
wire stq6_mfdpa_val_d;
wire stq6_mfdpa_val_q;
wire [0:`CR_POOL_ENC-1] ex2_cr_fld_d;
wire [0:`CR_POOL_ENC-1] ex2_cr_fld_q;
wire [0:`CR_POOL_ENC-1] ex3_cr_fld_d;
wire [0:`CR_POOL_ENC-1] ex3_cr_fld_q;
wire [0:`CR_POOL_ENC-1] ex4_cr_fld_d;
wire [0:`CR_POOL_ENC-1] ex4_cr_fld_q;
wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] ex5_cr_fld_d;
wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] ex5_cr_fld_q;
wire ex4_cr_sel;
wire [0:AXU_TARGET_ENC-1] ex4_cr_fld;
wire [0:`CR_WIDTH-1] ex5_cr_wd;
wire [0:`UCODE_ENTRIES_ENC-1] ex2_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] ex2_ucode_cnt_q;
wire [0:`UCODE_ENTRIES_ENC-1] ex3_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] ex3_ucode_cnt_q;
wire ex2_ucode_op_d;
wire ex2_ucode_op_q;
wire ex3_ucode_op_d;
wire ex3_ucode_op_q;
wire ex4_ucode_op_d;
wire ex4_ucode_op_q;
wire ex4_cline_chk;
wire ex4_send_l2;
wire ex4_has_data;
wire ex4_dReq_val;
wire ex4_excp_rpt_val;
wire ex4_ucode_rpt;
wire ex4_ucode_rpt_val;
wire ex4_mffgpr_rpt_val;
wire ex4_ucode_restart;
wire ex4_sfx_excpt_det;
wire ex4_excp_det;
wire ex4_wNComp_excp;
wire dir_arr_rd_rv1_done;
wire [0:1] dir_arr_rd_cntrl;
wire dir_arr_rd_val_d;
wire dir_arr_rd_val_q;
wire [0:`THREADS-1] dir_arr_rd_tid_d;
wire [0:`THREADS-1] dir_arr_rd_tid_q;
wire dir_arr_rd_rv1_val_d;
wire dir_arr_rd_rv1_val_q;
wire dir_arr_rd_ex0_done_d;
wire dir_arr_rd_ex0_done_q;
wire dir_arr_rd_ex1_done_d;
wire dir_arr_rd_ex1_done_q;
wire dir_arr_rd_ex2_done_d;
wire dir_arr_rd_ex2_done_q;
wire dir_arr_rd_ex3_done_d;
wire dir_arr_rd_ex3_done_q;
wire dir_arr_rd_ex4_done_d;
wire dir_arr_rd_ex4_done_q;
wire dir_arr_rd_ex5_done_d;
wire dir_arr_rd_ex5_done_q;
wire dir_arr_rd_ex6_done_d;
wire dir_arr_rd_ex6_done_q;
wire dir_arr_rd_busy;
wire [0:`THREADS-1] dir_arr_rd_tid_busy;
wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_arr_rd_tag;
wire [0:1+`THREADS] dir_arr_rd_directory;
wire [0:PARBITS-1] dir_arr_rd_parity;
wire [0:6] dir_arr_rd_lru;
wire ex4_dacrw1_cmpr;
wire ex4_dacrw2_cmpr;
wire ex4_dacrw3_cmpr;
wire ex4_dacrw4_cmpr;
wire ex5_dacrw_rpt_val;
wire [0:3] ex5_dacrw_cmpr;
wire [0:3] ex5_dacrw_cmpr_d;
wire [0:3] ex5_dacrw_cmpr_q;
wire [0:3] ex6_dacrw_cmpr_d;
wire [0:3] ex6_dacrw_cmpr_q;
wire ex4_dac_int_det;
wire ex4_dbg_int_en;
wire ex5_flush2ucode;
wire ex5_n_flush;
wire ex5_np1_flush;
wire ex5_exception_val;
wire [0:5] ex5_exception;
wire [0:`THREADS-1] ex5_dear_val;
wire ex5_misalign_flush;
wire [0:`THREADS-1] lq_ram_data_val;
wire [0:`THREADS-1] ex6_ram_thrd;
wire [0:`THREADS-1] ex6_ram_active_thrd;
wire [0:`THREADS-1] stq8_ram_thrd;
wire [0:`THREADS-1] stq8_ram_active_thrd;
wire [0:`THREADS-1] rel2_ram_thrd;
wire [0:`THREADS-1] rel2_ram_active_thrd;
wire [0:`THREADS-1] pc_lq_ram_active_d;
wire [0:`THREADS-1] pc_lq_ram_active_q;
wire lq_pc_ram_data_val_d;
wire lq_pc_ram_data_val_q;
wire ex1_instr_act;
wire ex1_stg_act;
wire ex1_stg_act_d;
wire ex1_stg_act_q;
wire ex2_stg_act_d;
wire ex2_stg_act_q;
wire ex3_stg_act_d;
wire ex3_stg_act_q;
wire ex4_stg_act_d;
wire ex4_stg_act_q;
wire ex5_stg_act_d;
wire ex5_stg_act_q;
wire ex6_stg_act_d;
wire ex6_stg_act_q;
wire binv1_stg_act;
wire binv2_stg_act_d;
wire binv2_stg_act_q;
wire binv3_stg_act_d;
wire binv3_stg_act_q;
wire binv4_stg_act_d;
wire binv4_stg_act_q;
wire binv5_stg_act_d;
wire binv5_stg_act_q;
wire binv6_stg_act_d;
wire binv6_stg_act_q;
wire ex2_binv2_stg_act;
wire ex3_binv3_stg_act;
wire ex4_binv4_stg_act;
wire ex5_binv5_stg_act;
wire ex6_binv6_stg_act;
wire ex4_darr_rd_act;
wire ex5_darr_rd_act;
wire lq0_iu_act;
wire stq1_stg_act;
wire stq2_stg_act_d;
wire stq2_stg_act_q;
wire stq3_stg_act_d;
wire stq3_stg_act_q;
wire stq4_stg_act_d;
wire stq4_stg_act_q;
wire stq5_stg_act_d;
wire stq5_stg_act_q;
wire fgen_ex1_stg_flush_int;
wire fgen_ex2_stg_flush_int;
wire fgen_ex3_stg_flush_int;
wire fgen_ex4_stg_flush_int;
wire fgen_ex5_stg_flush_int;
wire fgen_ex4_cp_flush_int;
wire fgen_ex5_cp_flush;
wire fgen_scan_in;
wire fgen_scan_out;
wire perf_ex6_derat_restarts;
//--------------------------
// register constants
//--------------------------
parameter iu_lq_recirc_val_offset = 0;
parameter iu_lq_cp_next_itag_offset = iu_lq_recirc_val_offset + `THREADS;
parameter iu_lq_cp_flush_offset = iu_lq_cp_next_itag_offset + (`THREADS*`ITAG_SIZE_ENC);
parameter xer_lq_cp_rd_so_offset = iu_lq_cp_flush_offset + `THREADS;
parameter ex0_i0_vld_offset = xer_lq_cp_rd_so_offset + `THREADS;
parameter ex0_i0_ucode_preissue_offset = ex0_i0_vld_offset + `THREADS;
parameter ex0_i0_2ucode_offset = ex0_i0_ucode_preissue_offset + 1;
parameter ex0_i0_ucode_cnt_offset = ex0_i0_2ucode_offset + 1;
parameter ex0_i1_vld_offset = ex0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter ex0_i1_ucode_preissue_offset = ex0_i1_vld_offset + `THREADS;
parameter ex0_i1_2ucode_offset = ex0_i1_ucode_preissue_offset + 1;
parameter ex0_i1_ucode_cnt_offset = ex0_i1_2ucode_offset + 1;
parameter ex2_optype1_offset = ex0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter ex2_optype2_offset = ex2_optype1_offset + 1;
parameter ex2_optype4_offset = ex2_optype2_offset + 1;
parameter ex2_optype8_offset = ex2_optype4_offset + 1;
parameter ex2_optype16_offset = ex2_optype8_offset + 1;
parameter ex3_optype1_offset = ex2_optype16_offset + 1;
parameter ex3_optype2_offset = ex3_optype1_offset + 1;
parameter ex3_optype4_offset = ex3_optype2_offset + 1;
parameter ex3_optype8_offset = ex3_optype4_offset + 1;
parameter ex3_optype16_offset = ex3_optype8_offset + 1;
parameter ex3_dacr_type_offset = ex3_optype16_offset + 1;
parameter ex4_dacr_type_offset = ex3_dacr_type_offset + 1;
parameter ex5_dacr_type_offset = ex4_dacr_type_offset + 1;
parameter ex2_cache_acc_offset = ex5_dacr_type_offset + 1;
parameter ex3_cache_acc_offset = ex2_cache_acc_offset + 1;
parameter ex4_cache_acc_offset = ex3_cache_acc_offset + 1;
parameter ex5_cache_acc_offset = ex4_cache_acc_offset + 1;
parameter ex6_cache_acc_offset = ex5_cache_acc_offset + 1;
parameter ex2_thrd_id_offset = ex6_cache_acc_offset + 1;
parameter ex3_thrd_id_offset = ex2_thrd_id_offset + `THREADS;
parameter ex4_thrd_id_offset = ex3_thrd_id_offset + `THREADS;
parameter ex5_thrd_id_offset = ex4_thrd_id_offset + `THREADS;
parameter ex6_thrd_id_offset = ex5_thrd_id_offset + `THREADS;
parameter ex2_instr_offset = ex6_thrd_id_offset + `THREADS;
parameter ex3_instr_offset = ex2_instr_offset + 32;
parameter ex4_instr_offset = ex3_instr_offset + 32;
parameter ex5_instr_offset = ex4_instr_offset + 32;
parameter ex2_target_gpr_offset = ex5_instr_offset + 32;
parameter ex3_target_gpr_offset = ex2_target_gpr_offset + AXU_TARGET_ENC;
parameter ex4_target_gpr_offset = ex3_target_gpr_offset + AXU_TARGET_ENC;
parameter ex5_target_gpr_offset = ex4_target_gpr_offset + AXU_TARGET_ENC;
parameter ex2_dcbt_instr_offset = ex5_target_gpr_offset + AXU_TARGET_ENC;
parameter ex3_dcbt_instr_offset = ex2_dcbt_instr_offset + 1;
parameter ex4_dcbt_instr_offset = ex3_dcbt_instr_offset + 1;
parameter ex2_pfetch_val_offset = ex4_dcbt_instr_offset + 1;
parameter ex3_pfetch_val_offset = ex2_pfetch_val_offset + 1;
parameter ex4_pfetch_val_offset = ex3_pfetch_val_offset + 1;
parameter ex5_pfetch_val_offset = ex4_pfetch_val_offset + 1;
parameter ex6_pfetch_val_offset = ex5_pfetch_val_offset + 1;
parameter ex2_dcbtst_instr_offset = ex6_pfetch_val_offset + 1;
parameter ex3_dcbtst_instr_offset = ex2_dcbtst_instr_offset + 1;
parameter ex4_dcbtst_instr_offset = ex3_dcbtst_instr_offset + 1;
parameter ex2_wchk_instr_offset = ex4_dcbtst_instr_offset + 1;
parameter ex3_wchk_instr_offset = ex2_wchk_instr_offset + 1;
parameter ex4_wchk_instr_offset = ex3_wchk_instr_offset + 1;
parameter ex2_dcbst_instr_offset = ex4_wchk_instr_offset + 1;
parameter ex3_dcbst_instr_offset = ex2_dcbst_instr_offset + 1;
parameter ex4_dcbst_instr_offset = ex3_dcbst_instr_offset + 1;
parameter ex2_dcbf_instr_offset = ex4_dcbst_instr_offset + 1;
parameter ex3_dcbf_instr_offset = ex2_dcbf_instr_offset + 1;
parameter ex4_dcbf_instr_offset = ex3_dcbf_instr_offset + 1;
parameter ex2_mtspr_trace_offset = ex4_dcbf_instr_offset + 1;
parameter ex3_mtspr_trace_offset = ex2_mtspr_trace_offset + 1;
parameter ex4_mtspr_trace_offset = ex3_mtspr_trace_offset + 1;
parameter ex2_sync_instr_offset = ex4_mtspr_trace_offset + 1;
parameter ex3_sync_instr_offset = ex2_sync_instr_offset + 1;
parameter ex4_sync_instr_offset = ex3_sync_instr_offset + 1;
parameter ex2_l_fld_offset = ex4_sync_instr_offset + 1;
parameter ex3_l_fld_offset = ex2_l_fld_offset + 2;
parameter ex4_l_fld_offset = ex3_l_fld_offset + 2;
parameter ex5_l_fld_offset = ex4_l_fld_offset + 2;
parameter ex2_dcbi_instr_offset = ex5_l_fld_offset + 2;
parameter ex3_dcbi_instr_offset = ex2_dcbi_instr_offset + 1;
parameter ex4_dcbi_instr_offset = ex3_dcbi_instr_offset + 1;
parameter ex2_dcbz_instr_offset = ex4_dcbi_instr_offset + 1;
parameter ex3_dcbz_instr_offset = ex2_dcbz_instr_offset + 1;
parameter ex4_dcbz_instr_offset = ex3_dcbz_instr_offset + 1;
parameter ex2_icbi_instr_offset = ex4_dcbz_instr_offset + 1;
parameter ex3_icbi_instr_offset = ex2_icbi_instr_offset + 1;
parameter ex4_icbi_instr_offset = ex3_icbi_instr_offset + 1;
parameter ex2_mbar_instr_offset = ex4_icbi_instr_offset + 1;
parameter ex3_mbar_instr_offset = ex2_mbar_instr_offset + 1;
parameter ex4_mbar_instr_offset = ex3_mbar_instr_offset + 1;
parameter ex2_makeitso_instr_offset = ex4_mbar_instr_offset + 1;
parameter ex3_makeitso_instr_offset = ex2_makeitso_instr_offset + 1;
parameter ex4_makeitso_instr_offset = ex3_makeitso_instr_offset + 1;
parameter ex2_dci_instr_offset = ex4_makeitso_instr_offset + 1;
parameter ex3_dci_instr_offset = ex2_dci_instr_offset + 1;
parameter ex4_dci_instr_offset = ex3_dci_instr_offset + 1;
parameter ex2_ici_instr_offset = ex4_dci_instr_offset + 1;
parameter ex3_ici_instr_offset = ex2_ici_instr_offset + 1;
parameter ex4_ici_instr_offset = ex3_ici_instr_offset + 1;
parameter ex2_algebraic_offset = ex4_ici_instr_offset + 1;
parameter ex3_algebraic_offset = ex2_algebraic_offset + 1;
parameter ex2_strg_index_offset = ex3_algebraic_offset + 1;
parameter ex3_strg_index_offset = ex2_strg_index_offset + 1;
parameter ex4_strg_index_offset = ex3_strg_index_offset + 1;
parameter ex2_resv_instr_offset = ex4_strg_index_offset + 1;
parameter ex3_resv_instr_offset = ex2_resv_instr_offset + 1;
parameter ex4_resv_instr_offset = ex3_resv_instr_offset + 1;
parameter ex2_mutex_hint_offset = ex4_resv_instr_offset + 1;
parameter ex3_mutex_hint_offset = ex2_mutex_hint_offset + 1;
parameter ex4_mutex_hint_offset = ex3_mutex_hint_offset + 1;
parameter ex2_load_instr_offset = ex4_mutex_hint_offset + 1;
parameter ex3_load_instr_offset = ex2_load_instr_offset + 1;
parameter ex4_load_instr_offset = ex3_load_instr_offset + 1;
parameter ex2_store_instr_offset = ex4_load_instr_offset + 1;
parameter ex3_store_instr_offset = ex2_store_instr_offset + 1;
parameter ex4_store_instr_offset = ex3_store_instr_offset + 1;
parameter ex4_le_mode_offset = ex4_store_instr_offset + 1;
parameter ex5_wimge_i_bits_offset = ex4_le_mode_offset + 1;
parameter ex2_axu_op_val_offset = ex5_wimge_i_bits_offset + 1;
parameter ex3_axu_op_val_offset = ex2_axu_op_val_offset + 1;
parameter ex4_axu_op_val_offset = ex3_axu_op_val_offset + 1;
parameter ex5_axu_op_val_offset = ex4_axu_op_val_offset + 1;
parameter ex2_upd_form_offset = ex5_axu_op_val_offset + 1;
parameter ex3_upd_form_offset = ex2_upd_form_offset + 1;
parameter ex2_axu_instr_type_offset = ex3_upd_form_offset + 1;
parameter ex3_axu_instr_type_offset = ex2_axu_instr_type_offset + 3;
parameter ex5_load_hit_offset = ex3_axu_instr_type_offset + 3;
parameter ex6_load_hit_offset = ex5_load_hit_offset + 1;
parameter ex5_usr_bits_offset = ex6_load_hit_offset + 1;
parameter ex5_classid_offset = ex5_usr_bits_offset + 4;
parameter ex5_derat_setHold_offset = ex5_classid_offset + 2;
parameter ex5_axu_wren_offset = ex5_derat_setHold_offset + 1;
parameter ex6_axu_wren_offset = ex5_axu_wren_offset + 1;
parameter ex5_lq_ta_gpr_offset = ex6_axu_wren_offset + 1;
parameter ex6_lq_ta_gpr_offset = ex5_lq_ta_gpr_offset + AXU_TARGET_ENC;
parameter ex5_load_le_offset = ex6_lq_ta_gpr_offset + (`GPR_POOL_ENC+`THREADS_POOL_ENC);
parameter ex2_th_fld_c_offset = ex5_load_le_offset + 1;
parameter ex3_th_fld_c_offset = ex2_th_fld_c_offset + 1;
parameter ex4_th_fld_c_offset = ex3_th_fld_c_offset + 1;
parameter ex2_th_fld_l2_offset = ex4_th_fld_c_offset + 1;
parameter ex3_th_fld_l2_offset = ex2_th_fld_l2_offset + 1;
parameter ex4_th_fld_l2_offset = ex3_th_fld_l2_offset + 1;
parameter ex2_dcbtls_instr_offset = ex4_th_fld_l2_offset + 1;
parameter ex3_dcbtls_instr_offset = ex2_dcbtls_instr_offset + 1;
parameter ex4_dcbtls_instr_offset = ex3_dcbtls_instr_offset + 1;
parameter ex2_dcbtstls_instr_offset = ex4_dcbtls_instr_offset + 1;
parameter ex3_dcbtstls_instr_offset = ex2_dcbtstls_instr_offset + 1;
parameter ex4_dcbtstls_instr_offset = ex3_dcbtstls_instr_offset + 1;
parameter ex2_dcblc_instr_offset = ex4_dcbtstls_instr_offset + 1;
parameter ex3_dcblc_instr_offset = ex2_dcblc_instr_offset + 1;
parameter ex4_dcblc_instr_offset = ex3_dcblc_instr_offset + 1;
parameter ex2_icblc_l2_instr_offset = ex4_dcblc_instr_offset + 1;
parameter ex3_icblc_l2_instr_offset = ex2_icblc_l2_instr_offset + 1;
parameter ex4_icblc_l2_instr_offset = ex3_icblc_l2_instr_offset + 1;
parameter ex2_icbt_l2_instr_offset = ex4_icblc_l2_instr_offset + 1;
parameter ex3_icbt_l2_instr_offset = ex2_icbt_l2_instr_offset + 1;
parameter ex4_icbt_l2_instr_offset = ex3_icbt_l2_instr_offset + 1;
parameter ex2_icbtls_l2_instr_offset = ex4_icbt_l2_instr_offset + 1;
parameter ex3_icbtls_l2_instr_offset = ex2_icbtls_l2_instr_offset + 1;
parameter ex4_icbtls_l2_instr_offset = ex3_icbtls_l2_instr_offset + 1;
parameter ex2_tlbsync_instr_offset = ex4_icbtls_l2_instr_offset + 1;
parameter ex3_tlbsync_instr_offset = ex2_tlbsync_instr_offset + 1;
parameter ex4_tlbsync_instr_offset = ex3_tlbsync_instr_offset + 1;
parameter ex2_ldst_falign_offset = ex4_tlbsync_instr_offset + 1;
parameter ex2_ldst_fexcpt_offset = ex2_ldst_falign_offset + 1;
parameter ex3_ldst_fexcpt_offset = ex2_ldst_fexcpt_offset + 1;
parameter ex5_load_miss_offset = ex3_ldst_fexcpt_offset + 1;
parameter xudbg1_dir_reg_offset = ex5_load_miss_offset + 1;
parameter xudbg1_parity_reg_offset = xudbg1_dir_reg_offset + (9+`THREADS);
parameter xudbg2_tag_offset = xudbg1_parity_reg_offset + PARBITS;
parameter stq4_dcarr_wren_offset = xudbg2_tag_offset + TAGSIZE;
parameter ex2_sgpr_instr_offset = stq4_dcarr_wren_offset + 1;
parameter ex2_saxu_instr_offset = ex2_sgpr_instr_offset + 1;
parameter ex2_sdp_instr_offset = ex2_saxu_instr_offset + 1;
parameter ex2_tgpr_instr_offset = ex2_sdp_instr_offset + 1;
parameter ex2_taxu_instr_offset = ex2_tgpr_instr_offset + 1;
parameter ex2_tdp_instr_offset = ex2_taxu_instr_offset + 1;
parameter ex3_sgpr_instr_offset = ex2_tdp_instr_offset + 1;
parameter ex3_saxu_instr_offset = ex3_sgpr_instr_offset + 1;
parameter ex3_sdp_instr_offset = ex3_saxu_instr_offset + 1;
parameter ex3_tgpr_instr_offset = ex3_sdp_instr_offset + 1;
parameter ex3_taxu_instr_offset = ex3_tgpr_instr_offset + 1;
parameter ex3_tdp_instr_offset = ex3_taxu_instr_offset + 1;
parameter ex4_sgpr_instr_offset = ex3_tdp_instr_offset + 1;
parameter ex4_saxu_instr_offset = ex4_sgpr_instr_offset + 1;
parameter ex4_sdp_instr_offset = ex4_saxu_instr_offset + 1;
parameter ex4_tgpr_instr_offset = ex4_sdp_instr_offset + 1;
parameter ex4_taxu_instr_offset = ex4_tgpr_instr_offset + 1;
parameter ex4_tdp_instr_offset = ex4_taxu_instr_offset + 1;
parameter ex5_mftgpr_val_offset = ex4_tdp_instr_offset + 1;
parameter ex4_moveOp_val_offset = ex5_mftgpr_val_offset + 1;
parameter stq6_moveOp_val_offset = ex4_moveOp_val_offset + 1;
parameter ex3_undef_touch_offset = stq6_moveOp_val_offset + 1;
parameter ex4_undef_touch_offset = ex3_undef_touch_offset + 1;
parameter ex4_blkable_touch_offset = ex4_undef_touch_offset + 1;
parameter ex5_blk_touch_offset = ex4_blkable_touch_offset + 1;
parameter ex6_blk_touch_offset = ex5_blk_touch_offset + 1;
parameter ex3_eff_addr_offset = ex6_blk_touch_offset + 1;
parameter ex4_eff_addr_offset = ex3_eff_addr_offset + (2**`GPR_WIDTH_ENC);
parameter ex5_eff_addr_offset = ex4_eff_addr_offset + (2**`GPR_WIDTH_ENC);
parameter ex3_undef_lockset_offset = ex5_eff_addr_offset + (2**`GPR_WIDTH_ENC);
parameter ex4_undef_lockset_offset = ex3_undef_lockset_offset + 1;
parameter ex5_unable_2lock_offset = ex4_undef_lockset_offset + 1;
parameter ex6_stq5_unable_2lock_offset = ex5_unable_2lock_offset + 1;
parameter ex5_dacrw_cmpr_offset = ex6_stq5_unable_2lock_offset + 1;
parameter ex6_dacrw_cmpr_offset = ex5_dacrw_cmpr_offset + 4;
parameter ex3_stq_val_req_offset = ex6_dacrw_cmpr_offset + 4;
parameter ex4_stq_val_req_offset = ex3_stq_val_req_offset + 1;
parameter ex5_load_instr_offset = ex4_stq_val_req_offset + 1;
parameter ex2_mword_instr_offset = ex5_load_instr_offset + 1;
parameter ex3_mword_instr_offset = ex2_mword_instr_offset + 1;
parameter stq4_store_miss_offset = ex3_mword_instr_offset + 1;
parameter ex5_perf_dcbt_offset = stq4_store_miss_offset + 1;
parameter spr_ccr2_ap_offset = ex5_perf_dcbt_offset + 1;
parameter spr_ccr2_en_trace_offset = spr_ccr2_ap_offset + 1;
parameter spr_ccr2_ucode_dis_offset = spr_ccr2_en_trace_offset + 1;
parameter spr_ccr2_notlb_offset = spr_ccr2_ucode_dis_offset + 1;
parameter clkg_ctl_override_offset = spr_ccr2_notlb_offset + 1;
parameter spr_xucr0_wlk_offset = clkg_ctl_override_offset + 1;
parameter spr_xucr0_mbar_ack_offset = spr_xucr0_wlk_offset + 1;
parameter spr_xucr0_tlbsync_offset = spr_xucr0_mbar_ack_offset + 1;
parameter spr_xucr0_dcdis_offset = spr_xucr0_tlbsync_offset + 1;
parameter spr_xucr0_aflsta_offset = spr_xucr0_dcdis_offset + 1;
parameter spr_xucr0_flsta_offset = spr_xucr0_aflsta_offset + 1;
parameter spr_xucr0_mddp_offset = spr_xucr0_flsta_offset + 1;
parameter spr_xucr0_mdcp_offset = spr_xucr0_mddp_offset + 1;
parameter spr_xucr4_mmu_mchk_offset = spr_xucr0_mdcp_offset + 1;
parameter spr_xucr4_mddmh_offset = spr_xucr4_mmu_mchk_offset + 1;
parameter spr_xucr0_en_trace_um_offset = spr_xucr4_mddmh_offset + 1;
parameter ex1_lsu_64bit_mode_offset = spr_xucr0_en_trace_um_offset + `THREADS;
parameter ex2_lsu_64bit_agen_offset = ex1_lsu_64bit_mode_offset + `THREADS;
parameter ex3_lsu_64bit_agen_offset = ex2_lsu_64bit_agen_offset + 1;
parameter ex4_lsu_64bit_agen_offset = ex3_lsu_64bit_agen_offset + 1;
parameter ex4_local_dcbf_offset = ex4_lsu_64bit_agen_offset + 1;
parameter ex2_msgsnd_instr_offset = ex4_local_dcbf_offset + 1;
parameter ex3_msgsnd_instr_offset = ex2_msgsnd_instr_offset + 1;
parameter ex4_msgsnd_instr_offset = ex3_msgsnd_instr_offset + 1;
parameter ex4_load_type_offset = ex4_msgsnd_instr_offset + 1;
parameter ex4_gath_load_offset = ex4_load_type_offset + 1;
parameter ex4_l2load_type_offset = ex4_gath_load_offset + 1;
parameter ex5_lq_wren_offset = ex4_l2load_type_offset + 1;
parameter ex6_lq_wren_offset = ex5_lq_wren_offset + 1;
parameter ex2_ldawx_instr_offset = ex6_lq_wren_offset + 1;
parameter ex3_ldawx_instr_offset = ex2_ldawx_instr_offset + 1;
parameter ex4_ldawx_instr_offset = ex3_ldawx_instr_offset + 1;
parameter ex5_ldawx_instr_offset = ex4_ldawx_instr_offset + 1;
parameter ex2_wclr_instr_offset = ex5_ldawx_instr_offset + 1;
parameter ex3_wclr_instr_offset = ex2_wclr_instr_offset + 1;
parameter ex4_wclr_instr_offset = ex3_wclr_instr_offset + 1;
parameter ex4_opsize_enc_offset = ex4_wclr_instr_offset + 1;
parameter ex5_opsize_enc_offset = ex4_opsize_enc_offset + 3;
parameter ex2_itag_offset = ex5_opsize_enc_offset + 3;
parameter ex3_itag_offset = ex2_itag_offset + `ITAG_SIZE_ENC;
parameter ex4_itag_offset = ex3_itag_offset + `ITAG_SIZE_ENC;
parameter ex5_itag_offset = ex4_itag_offset + `ITAG_SIZE_ENC;
parameter ex6_itag_offset = ex5_itag_offset + `ITAG_SIZE_ENC;
parameter ex5_drop_rel_offset = ex6_itag_offset + `ITAG_SIZE_ENC;
parameter ex2_icswx_instr_offset = ex5_drop_rel_offset + 1;
parameter ex3_icswx_instr_offset = ex2_icswx_instr_offset + 1;
parameter ex4_icswx_instr_offset = ex3_icswx_instr_offset + 1;
parameter ex2_icswxdot_instr_offset = ex4_icswx_instr_offset + 1;
parameter ex3_icswxdot_instr_offset = ex2_icswxdot_instr_offset + 1;
parameter ex4_icswxdot_instr_offset = ex3_icswxdot_instr_offset + 1;
parameter ex2_icswx_epid_offset = ex4_icswxdot_instr_offset + 1;
parameter ex3_icswx_epid_offset = ex2_icswx_epid_offset + 1;
parameter ex4_icswx_epid_offset = ex3_icswx_epid_offset + 1;
parameter ex5_icswx_epid_offset = ex4_icswx_epid_offset + 1;
parameter ex4_c_inh_drop_op_offset = ex5_icswx_epid_offset + 1;
parameter rel2_axu_wren_offset = ex4_c_inh_drop_op_offset + 1;
parameter stq2_axu_val_offset = rel2_axu_wren_offset + 1;
parameter stq3_axu_val_offset = stq2_axu_val_offset + 1;
parameter stq4_axu_val_offset = stq3_axu_val_offset + 1;
parameter stq4_store_hit_offset = stq4_axu_val_offset + 1;
parameter stq5_store_hit_offset = stq4_store_hit_offset + 1;
parameter stq6_store_hit_offset = stq5_store_hit_offset + 1;
parameter rel2_ta_gpr_offset = stq6_store_hit_offset + 1;
parameter rv1_binv_val_offset = rel2_ta_gpr_offset + AXU_TARGET_ENC;
parameter ex0_binv_val_offset = rv1_binv_val_offset + 1;
parameter ex1_binv_val_offset = ex0_binv_val_offset + 1;
parameter ex2_binv_val_offset = ex1_binv_val_offset + 1;
parameter ex3_binv_val_offset = ex2_binv_val_offset + 1;
parameter ex4_binv_val_offset = ex3_binv_val_offset + 1;
parameter ex0_derat_snoop_val_offset = ex4_binv_val_offset + 1;
parameter ex1_derat_snoop_val_offset = ex0_derat_snoop_val_offset + 1;
parameter spr_msr_fp_offset = ex1_derat_snoop_val_offset + 1;
parameter spr_msr_spv_offset = spr_msr_fp_offset + `THREADS;
parameter spr_msr_gs_offset = spr_msr_spv_offset + `THREADS;
parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS;
parameter spr_msr_ds_offset = spr_msr_pr_offset + `THREADS;
parameter spr_msr_de_offset = spr_msr_ds_offset + `THREADS;
parameter spr_dbcr0_idm_offset = spr_msr_de_offset + `THREADS;
parameter spr_epcr_duvd_offset = spr_dbcr0_idm_offset + `THREADS;
parameter spr_lpidr_offset = spr_epcr_duvd_offset + `THREADS;
parameter spr_pid_offset = spr_lpidr_offset + 8;
parameter ex3_icswx_gs_offset = spr_pid_offset + (`THREADS*14);
parameter ex3_icswx_pr_offset = ex3_icswx_gs_offset + 1;
parameter ex4_icswx_ct_offset = ex3_icswx_pr_offset + 1;
parameter ex4_icswx_ct_val_offset = ex4_icswx_ct_offset + 2;
parameter dbg_int_en_offset = ex4_icswx_ct_val_offset + 1;
parameter ex5_ttype_offset = dbg_int_en_offset + `THREADS;
parameter ex4_wNComp_rcvd_offset = ex5_ttype_offset + 6;
parameter ex4_wNComp_offset = ex4_wNComp_rcvd_offset + 1;
parameter ex5_wNComp_offset = ex4_wNComp_offset + 1;
parameter ex5_wNComp_cr_upd_offset = ex5_wNComp_offset + 1;
parameter ex5_dvc_en_offset = ex5_wNComp_cr_upd_offset + 1;
parameter ex6_dvc_en_offset = ex5_dvc_en_offset + 2;
parameter ex4_is_inval_op_offset = ex6_dvc_en_offset + 2;
parameter ex4_l1_lock_set_offset = ex4_is_inval_op_offset + 1;
parameter ex5_l1_lock_set_offset = ex4_l1_lock_set_offset + 1;
parameter ex4_lock_clr_offset = ex5_l1_lock_set_offset + 1;
parameter ex5_lock_clr_offset = ex4_lock_clr_offset + 1;
parameter ex2_sfx_val_offset = ex5_lock_clr_offset + 1;
parameter ex3_sfx_val_offset = ex2_sfx_val_offset + 1;
parameter ex4_sfx_val_offset = ex3_sfx_val_offset + 1;
parameter ex2_ucode_val_offset = ex4_sfx_val_offset + 1;
parameter ex3_ucode_val_offset = ex2_ucode_val_offset + 1;
parameter ex4_ucode_val_offset = ex3_ucode_val_offset + 1;
parameter ex2_ucode_cnt_offset = ex4_ucode_val_offset + 1;
parameter ex3_ucode_cnt_offset = ex2_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter ex2_ucode_op_offset = ex3_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter ex3_ucode_op_offset = ex2_ucode_op_offset + 1;
parameter ex4_ucode_op_offset = ex3_ucode_op_offset + 1;
parameter ex6_lq_comp_rpt_offset = ex4_ucode_op_offset + 1;
parameter lq0_iu_execute_vld_offset = ex6_lq_comp_rpt_offset + 1;
parameter lq0_iu_itag_offset = lq0_iu_execute_vld_offset + `THREADS;
parameter lq0_iu_flush2ucode_type_offset = lq0_iu_itag_offset + `ITAG_SIZE_ENC;
parameter lq0_iu_recirc_val_offset = lq0_iu_flush2ucode_type_offset + 1;
parameter lq0_iu_flush2ucode_offset = lq0_iu_recirc_val_offset + `THREADS;
parameter lq0_iu_dear_val_offset = lq0_iu_flush2ucode_offset + 1;
parameter lq0_iu_eff_addr_offset = lq0_iu_dear_val_offset + `THREADS;
parameter lq0_iu_n_flush_offset = lq0_iu_eff_addr_offset + (2**`GPR_WIDTH_ENC);
parameter lq0_iu_np1_flush_offset = lq0_iu_n_flush_offset + 1;
parameter lq0_iu_exception_val_offset = lq0_iu_np1_flush_offset + 1;
parameter lq0_iu_exception_offset = lq0_iu_exception_val_offset + 1;
parameter lq0_iu_dacr_type_offset = lq0_iu_exception_offset + 6;
parameter lq0_iu_dacrw_offset = lq0_iu_dacr_type_offset + 1;
parameter lq0_iu_instr_offset = lq0_iu_dacrw_offset + 4;
parameter ex5_spec_load_miss_offset = lq0_iu_instr_offset + 32;
parameter ex5_spec_itag_vld_offset = ex5_spec_load_miss_offset + 1;
parameter ex5_spec_itag_offset = ex5_spec_itag_vld_offset + 1;
parameter ex5_spec_tid_offset = ex5_spec_itag_offset + `ITAG_SIZE_ENC;
parameter ex5_blk_pf_load_offset = ex5_spec_tid_offset + `THREADS;
parameter ex5_lq_wNComp_val_offset = ex5_blk_pf_load_offset + 1;
parameter ex6_lq_wNComp_val_offset = ex5_lq_wNComp_val_offset + 1;
parameter ex5_wNComp_ord_offset = ex6_lq_wNComp_val_offset + 1;
parameter ex5_restart_val_offset = ex5_wNComp_ord_offset + 1;
parameter ex5_derat_restart_offset = ex5_restart_val_offset + 1;
parameter ex6_derat_restart_offset = ex5_derat_restart_offset + 1;
parameter ex5_dir_restart_offset = ex6_derat_restart_offset + 1;
parameter ex6_dir_restart_offset = ex5_dir_restart_offset + 1;
parameter ex5_dec_restart_offset = ex6_dir_restart_offset + 1;
parameter ex6_dec_restart_offset = ex5_dec_restart_offset + 1;
parameter ex4_derat_itagHit_offset = ex6_dec_restart_offset + 1;