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380 KiB
Verilog

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
`timescale 1 ns / 1 ns
//********************************************************************
//*
//* TITLE:
//*
//* NAME: iuq_rn.vhdl
//*
//*********************************************************************
`include "tri_a2o.vh"
module iuq_rn(
inout vdd,
inout gnd,
input clk,
input rst,
input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types
input pc_iu_sg_2,
input clkoff_b,
input act_dis,
input tc_ac_ccflush_dc,
input d_mode,
input delay_lclkr,
input mpw1_b,
input mpw2_b,
input func_scan_in,
output func_scan_out,
//-----------------------------
// SPR connections
//-----------------------------
input spr_high_pri_mask,
input spr_cpcr_we,
input [0:6] spr_cpcr3_cp_cnt,
input [0:6] spr_cpcr5_cp_cnt,
input spr_single_issue,
//-------------------------------
// Performance interface with I$
//-------------------------------
input pc_iu_event_bus_enable,
output perf_iu5_stall,
output perf_iu5_cpl_credit_stall,
output perf_iu5_gpr_credit_stall,
output perf_iu5_cr_credit_stall,
output perf_iu5_lr_credit_stall,
output perf_iu5_ctr_credit_stall,
output perf_iu5_xer_credit_stall,
output perf_iu5_br_hold_stall,
output perf_iu5_axu_hold_stall,
//-----------------------------
// Inputs to rename from decode
//-----------------------------
input fdec_frn_iu5_i0_vld,
input [0:2] fdec_frn_iu5_i0_ucode,
input fdec_frn_iu5_i0_2ucode,
input fdec_frn_iu5_i0_fuse_nop,
input fdec_frn_iu5_i0_rte_lq,
input fdec_frn_iu5_i0_rte_sq,
input fdec_frn_iu5_i0_rte_fx0,
input fdec_frn_iu5_i0_rte_fx1,
input fdec_frn_iu5_i0_rte_axu0,
input fdec_frn_iu5_i0_rte_axu1,
input fdec_frn_iu5_i0_valop,
input fdec_frn_iu5_i0_ord,
input fdec_frn_iu5_i0_cord,
input [0:2] fdec_frn_iu5_i0_error,
input fdec_frn_iu5_i0_btb_entry,
input [0:1] fdec_frn_iu5_i0_btb_hist,
input fdec_frn_iu5_i0_bta_val,
input [0:19] fdec_frn_iu5_i0_fusion,
input fdec_frn_iu5_i0_spec,
input fdec_frn_iu5_i0_type_fp,
input fdec_frn_iu5_i0_type_ap,
input fdec_frn_iu5_i0_type_spv,
input fdec_frn_iu5_i0_type_st,
input fdec_frn_iu5_i0_async_block,
input fdec_frn_iu5_i0_np1_flush,
input fdec_frn_iu5_i0_core_block,
input fdec_frn_iu5_i0_isram,
input fdec_frn_iu5_i0_isload,
input fdec_frn_iu5_i0_isstore,
input [0:31] fdec_frn_iu5_i0_instr,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta,
input fdec_frn_iu5_i0_br_pred,
input fdec_frn_iu5_i0_bh_update,
input [0:1] fdec_frn_iu5_i0_bh0_hist,
input [0:1] fdec_frn_iu5_i0_bh1_hist,
input [0:1] fdec_frn_iu5_i0_bh2_hist,
input [0:17] fdec_frn_iu5_i0_gshare,
input [0:2] fdec_frn_iu5_i0_ls_ptr,
input fdec_frn_iu5_i0_match,
input [0:3] fdec_frn_iu5_i0_ilat,
input fdec_frn_iu5_i0_t1_v,
input [0:2] fdec_frn_iu5_i0_t1_t,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a,
input fdec_frn_iu5_i0_t2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a,
input [0:2] fdec_frn_iu5_i0_t2_t,
input fdec_frn_iu5_i0_t3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a,
input [0:2] fdec_frn_iu5_i0_t3_t,
input fdec_frn_iu5_i0_s1_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a,
input [0:2] fdec_frn_iu5_i0_s1_t,
input fdec_frn_iu5_i0_s2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a,
input [0:2] fdec_frn_iu5_i0_s2_t,
input fdec_frn_iu5_i0_s3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a,
input [0:2] fdec_frn_iu5_i0_s3_t,
input fdec_frn_iu5_i1_vld,
input [0:2] fdec_frn_iu5_i1_ucode,
input fdec_frn_iu5_i1_fuse_nop,
input fdec_frn_iu5_i1_rte_lq,
input fdec_frn_iu5_i1_rte_sq,
input fdec_frn_iu5_i1_rte_fx0,
input fdec_frn_iu5_i1_rte_fx1,
input fdec_frn_iu5_i1_rte_axu0,
input fdec_frn_iu5_i1_rte_axu1,
input fdec_frn_iu5_i1_valop,
input fdec_frn_iu5_i1_ord,
input fdec_frn_iu5_i1_cord,
input [0:2] fdec_frn_iu5_i1_error,
input fdec_frn_iu5_i1_btb_entry,
input [0:1] fdec_frn_iu5_i1_btb_hist,
input fdec_frn_iu5_i1_bta_val,
input [0:19] fdec_frn_iu5_i1_fusion,
input fdec_frn_iu5_i1_spec,
input fdec_frn_iu5_i1_type_fp,
input fdec_frn_iu5_i1_type_ap,
input fdec_frn_iu5_i1_type_spv,
input fdec_frn_iu5_i1_type_st,
input fdec_frn_iu5_i1_async_block,
input fdec_frn_iu5_i1_np1_flush,
input fdec_frn_iu5_i1_core_block,
input fdec_frn_iu5_i1_isram,
input fdec_frn_iu5_i1_isload,
input fdec_frn_iu5_i1_isstore,
input [0:31] fdec_frn_iu5_i1_instr,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar,
input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta,
input fdec_frn_iu5_i1_br_pred,
input fdec_frn_iu5_i1_bh_update,
input [0:1] fdec_frn_iu5_i1_bh0_hist,
input [0:1] fdec_frn_iu5_i1_bh1_hist,
input [0:1] fdec_frn_iu5_i1_bh2_hist,
input [0:17] fdec_frn_iu5_i1_gshare,
input [0:2] fdec_frn_iu5_i1_ls_ptr,
input fdec_frn_iu5_i1_match,
input [0:3] fdec_frn_iu5_i1_ilat,
input fdec_frn_iu5_i1_t1_v,
input [0:2] fdec_frn_iu5_i1_t1_t,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a,
input fdec_frn_iu5_i1_t2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a,
input [0:2] fdec_frn_iu5_i1_t2_t,
input fdec_frn_iu5_i1_t3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a,
input [0:2] fdec_frn_iu5_i1_t3_t,
input fdec_frn_iu5_i1_s1_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a,
input [0:2] fdec_frn_iu5_i1_s1_t,
input fdec_frn_iu5_i1_s2_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a,
input [0:2] fdec_frn_iu5_i1_s2_t,
input fdec_frn_iu5_i1_s3_v,
input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a,
input [0:2] fdec_frn_iu5_i1_s3_t,
//-----------------------------
// Stall to decode
//-----------------------------
output frn_fdec_iu5_stall,
input au_iu_iu5_stall, //AXU Rename stall
//-----------------------------
// Stall from dispatch
//-----------------------------
input fdis_frn_iu6_stall,
//----------------------------
// Completion Interface
//----------------------------
input cp_rn_empty,
input cp_rn_i0_v,
input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag,
input cp_rn_i0_t1_v,
input [0:2] cp_rn_i0_t1_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a,
input cp_rn_i0_t2_v,
input [0:2] cp_rn_i0_t2_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a,
input cp_rn_i0_t3_v,
input [0:2] cp_rn_i0_t3_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a,
input cp_rn_i1_v,
input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag,
input cp_rn_i1_t1_v,
input [0:2] cp_rn_i1_t1_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a,
input cp_rn_i1_t2_v,
input [0:2] cp_rn_i1_t2_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a,
input cp_rn_i1_t3_v,
input [0:2] cp_rn_i1_t3_t,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p,
input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a,
input cp_flush,
input cp_flush_into_uc,
input br_iu_redirect,
input cp_rn_uc_credit_free,
//----------------------------------------------------------------
// AXU Interface
//----------------------------------------------------------------
output iu_au_iu5_send_ok,
output [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0,
output [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1,
input au_iu_iu5_axu0_send_ok,
input au_iu_iu5_axu1_send_ok,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p,
input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag,
input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag,
input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p,
input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p,
input au_iu_iu5_i1_s1_dep_hit,
input au_iu_iu5_i1_s2_dep_hit,
input au_iu_iu5_i1_s3_dep_hit,
input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag,
input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag,
input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag,
//----------------------------------------------------------------
// Interface to reservation station - Completion is snooping also
//----------------------------------------------------------------
output frn_fdis_iu6_i0_vld,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag,
output [0:2] frn_fdis_iu6_i0_ucode,
output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt,
output frn_fdis_iu6_i0_2ucode,
output frn_fdis_iu6_i0_fuse_nop,
output frn_fdis_iu6_i0_rte_lq,
output frn_fdis_iu6_i0_rte_sq,
output frn_fdis_iu6_i0_rte_fx0,
output frn_fdis_iu6_i0_rte_fx1,
output frn_fdis_iu6_i0_rte_axu0,
output frn_fdis_iu6_i0_rte_axu1,
output frn_fdis_iu6_i0_valop,
output frn_fdis_iu6_i0_ord,
output frn_fdis_iu6_i0_cord,
output [0:2] frn_fdis_iu6_i0_error,
output frn_fdis_iu6_i0_btb_entry,
output [0:1] frn_fdis_iu6_i0_btb_hist,
output frn_fdis_iu6_i0_bta_val,
output [0:19] frn_fdis_iu6_i0_fusion,
output frn_fdis_iu6_i0_spec,
output frn_fdis_iu6_i0_type_fp,
output frn_fdis_iu6_i0_type_ap,
output frn_fdis_iu6_i0_type_spv,
output frn_fdis_iu6_i0_type_st,
output frn_fdis_iu6_i0_async_block,
output frn_fdis_iu6_i0_np1_flush,
output frn_fdis_iu6_i0_core_block,
output frn_fdis_iu6_i0_isram,
output frn_fdis_iu6_i0_isload,
output frn_fdis_iu6_i0_isstore,
output [0:31] frn_fdis_iu6_i0_instr,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta,
output frn_fdis_iu6_i0_br_pred,
output frn_fdis_iu6_i0_bh_update,
output [0:1] frn_fdis_iu6_i0_bh0_hist,
output [0:1] frn_fdis_iu6_i0_bh1_hist,
output [0:1] frn_fdis_iu6_i0_bh2_hist,
output [0:17] frn_fdis_iu6_i0_gshare,
output [0:2] frn_fdis_iu6_i0_ls_ptr,
output frn_fdis_iu6_i0_match,
output [0:3] frn_fdis_iu6_i0_ilat,
output frn_fdis_iu6_i0_t1_v,
output [0:2] frn_fdis_iu6_i0_t1_t,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p,
output frn_fdis_iu6_i0_t2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p,
output [0:2] frn_fdis_iu6_i0_t2_t,
output frn_fdis_iu6_i0_t3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p,
output [0:2] frn_fdis_iu6_i0_t3_t,
output frn_fdis_iu6_i0_s1_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag,
output [0:2] frn_fdis_iu6_i0_s1_t,
output frn_fdis_iu6_i0_s2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag,
output [0:2] frn_fdis_iu6_i0_s2_t,
output frn_fdis_iu6_i0_s3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag,
output [0:2] frn_fdis_iu6_i0_s3_t,
output frn_fdis_iu6_i1_vld,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag,
output [0:2] frn_fdis_iu6_i1_ucode,
output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt,
output frn_fdis_iu6_i1_fuse_nop,
output frn_fdis_iu6_i1_rte_lq,
output frn_fdis_iu6_i1_rte_sq,
output frn_fdis_iu6_i1_rte_fx0,
output frn_fdis_iu6_i1_rte_fx1,
output frn_fdis_iu6_i1_rte_axu0,
output frn_fdis_iu6_i1_rte_axu1,
output frn_fdis_iu6_i1_valop,
output frn_fdis_iu6_i1_ord,
output frn_fdis_iu6_i1_cord,
output [0:2] frn_fdis_iu6_i1_error,
output frn_fdis_iu6_i1_btb_entry,
output [0:1] frn_fdis_iu6_i1_btb_hist,
output frn_fdis_iu6_i1_bta_val,
output [0:19] frn_fdis_iu6_i1_fusion,
output frn_fdis_iu6_i1_spec,
output frn_fdis_iu6_i1_type_fp,
output frn_fdis_iu6_i1_type_ap,
output frn_fdis_iu6_i1_type_spv,
output frn_fdis_iu6_i1_type_st,
output frn_fdis_iu6_i1_async_block,
output frn_fdis_iu6_i1_np1_flush,
output frn_fdis_iu6_i1_core_block,
output frn_fdis_iu6_i1_isram,
output frn_fdis_iu6_i1_isload,
output frn_fdis_iu6_i1_isstore,
output [0:31] frn_fdis_iu6_i1_instr,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar,
output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta,
output frn_fdis_iu6_i1_br_pred,
output frn_fdis_iu6_i1_bh_update,
output [0:1] frn_fdis_iu6_i1_bh0_hist,
output [0:1] frn_fdis_iu6_i1_bh1_hist,
output [0:1] frn_fdis_iu6_i1_bh2_hist,
output [0:17] frn_fdis_iu6_i1_gshare,
output [0:2] frn_fdis_iu6_i1_ls_ptr,
output frn_fdis_iu6_i1_match,
output [0:3] frn_fdis_iu6_i1_ilat,
output frn_fdis_iu6_i1_t1_v,
output [0:2] frn_fdis_iu6_i1_t1_t,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p,
output frn_fdis_iu6_i1_t2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p,
output [0:2] frn_fdis_iu6_i1_t2_t,
output frn_fdis_iu6_i1_t3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p,
output [0:2] frn_fdis_iu6_i1_t3_t,
output frn_fdis_iu6_i1_s1_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag,
output [0:2] frn_fdis_iu6_i1_s1_t,
output frn_fdis_iu6_i1_s1_dep_hit,
output frn_fdis_iu6_i1_s2_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag,
output [0:2] frn_fdis_iu6_i1_s2_t,
output frn_fdis_iu6_i1_s2_dep_hit,
output frn_fdis_iu6_i1_s3_v,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a,
output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p,
output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag,
output [0:2] frn_fdis_iu6_i1_s3_t,
output frn_fdis_iu6_i1_s3_dep_hit
);
localparam [0:31] value_1 = 32'h00000001;
localparam [0:31] value_2 = 32'h00000002;
parameter next_itag_0_offset = 0;
parameter next_itag_1_offset = next_itag_0_offset + `ITAG_SIZE_ENC;
parameter cp_high_credit_cnt_offset = next_itag_1_offset + `ITAG_SIZE_ENC;
parameter cp_med_credit_cnt_offset = cp_high_credit_cnt_offset + `CPL_Q_DEPTH_ENC + 1;
parameter ucode_cnt_offset = cp_med_credit_cnt_offset + `CPL_Q_DEPTH_ENC + 1;
parameter ucode_cnt_save_offset = ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter cp_flush_offset = ucode_cnt_save_offset + `UCODE_ENTRIES_ENC;
parameter cp_flush_into_uc_offset = cp_flush_offset + 1;
parameter br_iu_hold_offset = cp_flush_into_uc_offset + 1;
parameter cp_rn_empty_offset = br_iu_hold_offset + 1;
parameter hold_instructions_offset = cp_rn_empty_offset + 1;
parameter high_pri_mask_offset = hold_instructions_offset + 1;
parameter fdis_frn_iu6_stall_offset = high_pri_mask_offset + 1;
parameter frn_fdis_iu6_i0_vld_offset = fdis_frn_iu6_stall_offset + 19;
parameter frn_fdis_iu6_i0_itag_offset = frn_fdis_iu6_i0_vld_offset + 1;
parameter frn_fdis_iu6_i0_ucode_offset = frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i0_ucode_cnt_offset = frn_fdis_iu6_i0_ucode_offset + 3;
parameter frn_fdis_iu6_i0_2ucode_offset = frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter frn_fdis_iu6_i0_fuse_nop_offset = frn_fdis_iu6_i0_2ucode_offset + 1;
parameter frn_fdis_iu6_i0_rte_lq_offset = frn_fdis_iu6_i0_fuse_nop_offset + 1;
parameter frn_fdis_iu6_i0_rte_sq_offset = frn_fdis_iu6_i0_rte_lq_offset + 1;
parameter frn_fdis_iu6_i0_rte_fx0_offset = frn_fdis_iu6_i0_rte_sq_offset + 1;
parameter frn_fdis_iu6_i0_rte_fx1_offset = frn_fdis_iu6_i0_rte_fx0_offset + 1;
parameter frn_fdis_iu6_i0_rte_axu0_offset = frn_fdis_iu6_i0_rte_fx1_offset + 1;
parameter frn_fdis_iu6_i0_rte_axu1_offset = frn_fdis_iu6_i0_rte_axu0_offset + 1;
parameter frn_fdis_iu6_i0_valop_offset = frn_fdis_iu6_i0_rte_axu1_offset + 1;
parameter frn_fdis_iu6_i0_ord_offset = frn_fdis_iu6_i0_valop_offset + 1;
parameter frn_fdis_iu6_i0_cord_offset = frn_fdis_iu6_i0_ord_offset + 1;
parameter frn_fdis_iu6_i0_error_offset = frn_fdis_iu6_i0_cord_offset + 1;
parameter frn_fdis_iu6_i0_btb_entry_offset = frn_fdis_iu6_i0_error_offset + 3;
parameter frn_fdis_iu6_i0_btb_hist_offset = frn_fdis_iu6_i0_btb_entry_offset + 1;
parameter frn_fdis_iu6_i0_bta_val_offset = frn_fdis_iu6_i0_btb_hist_offset + 2;
parameter frn_fdis_iu6_i0_fusion_offset = frn_fdis_iu6_i0_bta_val_offset + 1;
parameter frn_fdis_iu6_i0_spec_offset = frn_fdis_iu6_i0_fusion_offset + 20;
parameter frn_fdis_iu6_i0_type_fp_offset = frn_fdis_iu6_i0_spec_offset + 1;
parameter frn_fdis_iu6_i0_type_ap_offset = frn_fdis_iu6_i0_type_fp_offset + 1;
parameter frn_fdis_iu6_i0_type_spv_offset = frn_fdis_iu6_i0_type_ap_offset + 1;
parameter frn_fdis_iu6_i0_type_st_offset = frn_fdis_iu6_i0_type_spv_offset + 1;
parameter frn_fdis_iu6_i0_async_block_offset = frn_fdis_iu6_i0_type_st_offset + 1;
parameter frn_fdis_iu6_i0_np1_flush_offset = frn_fdis_iu6_i0_async_block_offset + 1;
parameter frn_fdis_iu6_i0_core_block_offset = frn_fdis_iu6_i0_np1_flush_offset + 1;
parameter frn_fdis_iu6_i0_isram_offset = frn_fdis_iu6_i0_core_block_offset + 1;
parameter frn_fdis_iu6_i0_isload_offset = frn_fdis_iu6_i0_isram_offset + 1;
parameter frn_fdis_iu6_i0_isstore_offset = frn_fdis_iu6_i0_isload_offset + 1;
parameter frn_fdis_iu6_i0_instr_offset = frn_fdis_iu6_i0_isstore_offset + 1;
parameter frn_fdis_iu6_i0_ifar_offset = frn_fdis_iu6_i0_instr_offset + 32;
parameter frn_fdis_iu6_i0_bta_offset = frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH);
parameter frn_fdis_iu6_i0_br_pred_offset = frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH);
parameter frn_fdis_iu6_i0_bh_update_offset = frn_fdis_iu6_i0_br_pred_offset + 1;
parameter frn_fdis_iu6_i0_bh0_hist_offset = frn_fdis_iu6_i0_bh_update_offset + 1;
parameter frn_fdis_iu6_i0_bh1_hist_offset = frn_fdis_iu6_i0_bh0_hist_offset + 2;
parameter frn_fdis_iu6_i0_bh2_hist_offset = frn_fdis_iu6_i0_bh1_hist_offset + 2;
parameter frn_fdis_iu6_i0_gshare_offset = frn_fdis_iu6_i0_bh2_hist_offset + 2;
parameter frn_fdis_iu6_i0_ls_ptr_offset = frn_fdis_iu6_i0_gshare_offset + 18;
parameter frn_fdis_iu6_i0_match_offset = frn_fdis_iu6_i0_ls_ptr_offset + 3;
parameter frn_fdis_iu6_i0_ilat_offset = frn_fdis_iu6_i0_match_offset + 1;
parameter frn_fdis_iu6_i0_t1_v_offset = frn_fdis_iu6_i0_ilat_offset + 4;
parameter frn_fdis_iu6_i0_t1_t_offset = frn_fdis_iu6_i0_t1_v_offset + 1;
parameter frn_fdis_iu6_i0_t1_a_offset = frn_fdis_iu6_i0_t1_t_offset + 3;
parameter frn_fdis_iu6_i0_t1_p_offset = frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_t2_v_offset = frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_t2_a_offset = frn_fdis_iu6_i0_t2_v_offset + 1;
parameter frn_fdis_iu6_i0_t2_p_offset = frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_t2_t_offset = frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_t3_v_offset = frn_fdis_iu6_i0_t2_t_offset + 3;
parameter frn_fdis_iu6_i0_t3_a_offset = frn_fdis_iu6_i0_t3_v_offset + 1;
parameter frn_fdis_iu6_i0_t3_p_offset = frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_t3_t_offset = frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s1_v_offset = frn_fdis_iu6_i0_t3_t_offset + 3;
parameter frn_fdis_iu6_i0_s1_a_offset = frn_fdis_iu6_i0_s1_v_offset + 1;
parameter frn_fdis_iu6_i0_s1_p_offset = frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s1_itag_offset = frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s1_t_offset = frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i0_s2_v_offset = frn_fdis_iu6_i0_s1_t_offset + 3;
parameter frn_fdis_iu6_i0_s2_a_offset = frn_fdis_iu6_i0_s2_v_offset + 1;
parameter frn_fdis_iu6_i0_s2_p_offset = frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s2_itag_offset = frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s2_t_offset = frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i0_s3_v_offset = frn_fdis_iu6_i0_s2_t_offset + 3;
parameter frn_fdis_iu6_i0_s3_a_offset = frn_fdis_iu6_i0_s3_v_offset + 1;
parameter frn_fdis_iu6_i0_s3_p_offset = frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s3_itag_offset = frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i0_s3_t_offset = frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i1_vld_offset = frn_fdis_iu6_i0_s3_t_offset + 3;
parameter frn_fdis_iu6_i1_itag_offset = frn_fdis_iu6_i1_vld_offset + 1;
parameter frn_fdis_iu6_i1_ucode_offset = frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i1_ucode_cnt_offset = frn_fdis_iu6_i1_ucode_offset + 3;
parameter frn_fdis_iu6_i1_fuse_nop_offset = frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter frn_fdis_iu6_i1_rte_lq_offset = frn_fdis_iu6_i1_fuse_nop_offset + 1;
parameter frn_fdis_iu6_i1_rte_sq_offset = frn_fdis_iu6_i1_rte_lq_offset + 1;
parameter frn_fdis_iu6_i1_rte_fx0_offset = frn_fdis_iu6_i1_rte_sq_offset + 1;
parameter frn_fdis_iu6_i1_rte_fx1_offset = frn_fdis_iu6_i1_rte_fx0_offset + 1;
parameter frn_fdis_iu6_i1_rte_axu0_offset = frn_fdis_iu6_i1_rte_fx1_offset + 1;
parameter frn_fdis_iu6_i1_rte_axu1_offset = frn_fdis_iu6_i1_rte_axu0_offset + 1;
parameter frn_fdis_iu6_i1_valop_offset = frn_fdis_iu6_i1_rte_axu1_offset + 1;
parameter frn_fdis_iu6_i1_ord_offset = frn_fdis_iu6_i1_valop_offset + 1;
parameter frn_fdis_iu6_i1_cord_offset = frn_fdis_iu6_i1_ord_offset + 1;
parameter frn_fdis_iu6_i1_error_offset = frn_fdis_iu6_i1_cord_offset + 1;
parameter frn_fdis_iu6_i1_btb_entry_offset = frn_fdis_iu6_i1_error_offset + 3;
parameter frn_fdis_iu6_i1_btb_hist_offset = frn_fdis_iu6_i1_btb_entry_offset + 1;
parameter frn_fdis_iu6_i1_bta_val_offset = frn_fdis_iu6_i1_btb_hist_offset + 2;
parameter frn_fdis_iu6_i1_fusion_offset = frn_fdis_iu6_i1_bta_val_offset + 1;
parameter frn_fdis_iu6_i1_spec_offset = frn_fdis_iu6_i1_fusion_offset + 20;
parameter frn_fdis_iu6_i1_type_fp_offset = frn_fdis_iu6_i1_spec_offset + 1;
parameter frn_fdis_iu6_i1_type_ap_offset = frn_fdis_iu6_i1_type_fp_offset + 1;
parameter frn_fdis_iu6_i1_type_spv_offset = frn_fdis_iu6_i1_type_ap_offset + 1;
parameter frn_fdis_iu6_i1_type_st_offset = frn_fdis_iu6_i1_type_spv_offset + 1;
parameter frn_fdis_iu6_i1_async_block_offset = frn_fdis_iu6_i1_type_st_offset + 1;
parameter frn_fdis_iu6_i1_np1_flush_offset = frn_fdis_iu6_i1_async_block_offset + 1;
parameter frn_fdis_iu6_i1_core_block_offset = frn_fdis_iu6_i1_np1_flush_offset + 1;
parameter frn_fdis_iu6_i1_isram_offset = frn_fdis_iu6_i1_core_block_offset + 1;
parameter frn_fdis_iu6_i1_isload_offset = frn_fdis_iu6_i1_isram_offset + 1;
parameter frn_fdis_iu6_i1_isstore_offset = frn_fdis_iu6_i1_isload_offset + 1;
parameter frn_fdis_iu6_i1_instr_offset = frn_fdis_iu6_i1_isstore_offset + 1;
parameter frn_fdis_iu6_i1_ifar_offset = frn_fdis_iu6_i1_instr_offset + 32;
parameter frn_fdis_iu6_i1_bta_offset = frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH);
parameter frn_fdis_iu6_i1_br_pred_offset = frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH);
parameter frn_fdis_iu6_i1_bh_update_offset = frn_fdis_iu6_i1_br_pred_offset + 1;
parameter frn_fdis_iu6_i1_bh0_hist_offset = frn_fdis_iu6_i1_bh_update_offset + 1;
parameter frn_fdis_iu6_i1_bh1_hist_offset = frn_fdis_iu6_i1_bh0_hist_offset + 2;
parameter frn_fdis_iu6_i1_bh2_hist_offset = frn_fdis_iu6_i1_bh1_hist_offset + 2;
parameter frn_fdis_iu6_i1_gshare_offset = frn_fdis_iu6_i1_bh2_hist_offset + 2;
parameter frn_fdis_iu6_i1_ls_ptr_offset = frn_fdis_iu6_i1_gshare_offset + 18;
parameter frn_fdis_iu6_i1_match_offset = frn_fdis_iu6_i1_ls_ptr_offset + 3;
parameter frn_fdis_iu6_i1_ilat_offset = frn_fdis_iu6_i1_match_offset + 1;
parameter frn_fdis_iu6_i1_t1_v_offset = frn_fdis_iu6_i1_ilat_offset + 4;
parameter frn_fdis_iu6_i1_t1_t_offset = frn_fdis_iu6_i1_t1_v_offset + 1;
parameter frn_fdis_iu6_i1_t1_a_offset = frn_fdis_iu6_i1_t1_t_offset + 3;
parameter frn_fdis_iu6_i1_t1_p_offset = frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_t2_v_offset = frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_t2_a_offset = frn_fdis_iu6_i1_t2_v_offset + 1;
parameter frn_fdis_iu6_i1_t2_p_offset = frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_t2_t_offset = frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_t3_v_offset = frn_fdis_iu6_i1_t2_t_offset + 3;
parameter frn_fdis_iu6_i1_t3_a_offset = frn_fdis_iu6_i1_t3_v_offset + 1;
parameter frn_fdis_iu6_i1_t3_p_offset = frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_t3_t_offset = frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s1_v_offset = frn_fdis_iu6_i1_t3_t_offset + 3;
parameter frn_fdis_iu6_i1_s1_a_offset = frn_fdis_iu6_i1_s1_v_offset + 1;
parameter frn_fdis_iu6_i1_s1_p_offset = frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s1_itag_offset = frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s1_t_offset = frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i1_s1_dep_hit_offset = frn_fdis_iu6_i1_s1_t_offset + 3;
parameter frn_fdis_iu6_i1_s2_v_offset = frn_fdis_iu6_i1_s1_dep_hit_offset + 1;
parameter frn_fdis_iu6_i1_s2_a_offset = frn_fdis_iu6_i1_s2_v_offset + 1;
parameter frn_fdis_iu6_i1_s2_p_offset = frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s2_itag_offset = frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s2_t_offset = frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i1_s2_dep_hit_offset = frn_fdis_iu6_i1_s2_t_offset + 3;
parameter frn_fdis_iu6_i1_s3_v_offset = frn_fdis_iu6_i1_s2_dep_hit_offset + 1;
parameter frn_fdis_iu6_i1_s3_a_offset = frn_fdis_iu6_i1_s3_v_offset + 1;
parameter frn_fdis_iu6_i1_s3_p_offset = frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s3_itag_offset = frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC;
parameter frn_fdis_iu6_i1_s3_t_offset = frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC;
parameter frn_fdis_iu6_i1_s3_dep_hit_offset = frn_fdis_iu6_i1_s3_t_offset + 3;
parameter stall_frn_fdis_iu6_i0_vld_offset = frn_fdis_iu6_i1_s3_dep_hit_offset + 1;
parameter stall_frn_fdis_iu6_i0_itag_offset = stall_frn_fdis_iu6_i0_vld_offset + 1;
parameter stall_frn_fdis_iu6_i0_ucode_offset = stall_frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i0_ucode_cnt_offset = stall_frn_fdis_iu6_i0_ucode_offset + 3;
parameter stall_frn_fdis_iu6_i0_fuse_nop_offset = stall_frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter stall_frn_fdis_iu6_i0_2ucode_offset = stall_frn_fdis_iu6_i0_fuse_nop_offset + 1;
parameter stall_frn_fdis_iu6_i0_rte_lq_offset = stall_frn_fdis_iu6_i0_2ucode_offset + 1;
parameter stall_frn_fdis_iu6_i0_rte_sq_offset = stall_frn_fdis_iu6_i0_rte_lq_offset + 1;
parameter stall_frn_fdis_iu6_i0_rte_fx0_offset = stall_frn_fdis_iu6_i0_rte_sq_offset + 1;
parameter stall_frn_fdis_iu6_i0_rte_fx1_offset = stall_frn_fdis_iu6_i0_rte_fx0_offset + 1;
parameter stall_frn_fdis_iu6_i0_rte_axu0_offset = stall_frn_fdis_iu6_i0_rte_fx1_offset + 1;
parameter stall_frn_fdis_iu6_i0_rte_axu1_offset = stall_frn_fdis_iu6_i0_rte_axu0_offset + 1;
parameter stall_frn_fdis_iu6_i0_valop_offset = stall_frn_fdis_iu6_i0_rte_axu1_offset + 1;
parameter stall_frn_fdis_iu6_i0_ord_offset = stall_frn_fdis_iu6_i0_valop_offset + 1;
parameter stall_frn_fdis_iu6_i0_cord_offset = stall_frn_fdis_iu6_i0_ord_offset + 1;
parameter stall_frn_fdis_iu6_i0_error_offset = stall_frn_fdis_iu6_i0_cord_offset + 1;
parameter stall_frn_fdis_iu6_i0_btb_entry_offset = stall_frn_fdis_iu6_i0_error_offset + 3;
parameter stall_frn_fdis_iu6_i0_btb_hist_offset = stall_frn_fdis_iu6_i0_btb_entry_offset + 1;
parameter stall_frn_fdis_iu6_i0_bta_val_offset = stall_frn_fdis_iu6_i0_btb_hist_offset + 2;
parameter stall_frn_fdis_iu6_i0_fusion_offset = stall_frn_fdis_iu6_i0_bta_val_offset + 1;
parameter stall_frn_fdis_iu6_i0_spec_offset = stall_frn_fdis_iu6_i0_fusion_offset + 20;
parameter stall_frn_fdis_iu6_i0_type_fp_offset = stall_frn_fdis_iu6_i0_spec_offset + 1;
parameter stall_frn_fdis_iu6_i0_type_ap_offset = stall_frn_fdis_iu6_i0_type_fp_offset + 1;
parameter stall_frn_fdis_iu6_i0_type_spv_offset = stall_frn_fdis_iu6_i0_type_ap_offset + 1;
parameter stall_frn_fdis_iu6_i0_type_st_offset = stall_frn_fdis_iu6_i0_type_spv_offset + 1;
parameter stall_frn_fdis_iu6_i0_async_block_offset = stall_frn_fdis_iu6_i0_type_st_offset + 1;
parameter stall_frn_fdis_iu6_i0_np1_flush_offset = stall_frn_fdis_iu6_i0_async_block_offset + 1;
parameter stall_frn_fdis_iu6_i0_core_block_offset = stall_frn_fdis_iu6_i0_np1_flush_offset + 1;
parameter stall_frn_fdis_iu6_i0_isram_offset = stall_frn_fdis_iu6_i0_core_block_offset + 1;
parameter stall_frn_fdis_iu6_i0_isload_offset = stall_frn_fdis_iu6_i0_isram_offset + 1;
parameter stall_frn_fdis_iu6_i0_isstore_offset = stall_frn_fdis_iu6_i0_isload_offset + 1;
parameter stall_frn_fdis_iu6_i0_instr_offset = stall_frn_fdis_iu6_i0_isstore_offset + 1;
parameter stall_frn_fdis_iu6_i0_ifar_offset = stall_frn_fdis_iu6_i0_instr_offset + 32;
parameter stall_frn_fdis_iu6_i0_bta_offset = stall_frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH);
parameter stall_frn_fdis_iu6_i0_br_pred_offset = stall_frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH);
parameter stall_frn_fdis_iu6_i0_bh_update_offset = stall_frn_fdis_iu6_i0_br_pred_offset + 1;
parameter stall_frn_fdis_iu6_i0_bh0_hist_offset = stall_frn_fdis_iu6_i0_bh_update_offset + 1;
parameter stall_frn_fdis_iu6_i0_bh1_hist_offset = stall_frn_fdis_iu6_i0_bh0_hist_offset + 2;
parameter stall_frn_fdis_iu6_i0_bh2_hist_offset = stall_frn_fdis_iu6_i0_bh1_hist_offset + 2;
parameter stall_frn_fdis_iu6_i0_gshare_offset = stall_frn_fdis_iu6_i0_bh2_hist_offset + 2;
parameter stall_frn_fdis_iu6_i0_ls_ptr_offset = stall_frn_fdis_iu6_i0_gshare_offset + 18;
parameter stall_frn_fdis_iu6_i0_match_offset = stall_frn_fdis_iu6_i0_ls_ptr_offset + 3;
parameter stall_frn_fdis_iu6_i0_ilat_offset = stall_frn_fdis_iu6_i0_match_offset + 1;
parameter stall_frn_fdis_iu6_i0_t1_v_offset = stall_frn_fdis_iu6_i0_ilat_offset + 4;
parameter stall_frn_fdis_iu6_i0_t1_t_offset = stall_frn_fdis_iu6_i0_t1_v_offset + 1;
parameter stall_frn_fdis_iu6_i0_t1_a_offset = stall_frn_fdis_iu6_i0_t1_t_offset + 3;
parameter stall_frn_fdis_iu6_i0_t1_p_offset = stall_frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_t2_v_offset = stall_frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_t2_a_offset = stall_frn_fdis_iu6_i0_t2_v_offset + 1;
parameter stall_frn_fdis_iu6_i0_t2_p_offset = stall_frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_t2_t_offset = stall_frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_t3_v_offset = stall_frn_fdis_iu6_i0_t2_t_offset + 3;
parameter stall_frn_fdis_iu6_i0_t3_a_offset = stall_frn_fdis_iu6_i0_t3_v_offset + 1;
parameter stall_frn_fdis_iu6_i0_t3_p_offset = stall_frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_t3_t_offset = stall_frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s1_v_offset = stall_frn_fdis_iu6_i0_t3_t_offset + 3;
parameter stall_frn_fdis_iu6_i0_s1_a_offset = stall_frn_fdis_iu6_i0_s1_v_offset + 1;
parameter stall_frn_fdis_iu6_i0_s1_p_offset = stall_frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s1_itag_offset = stall_frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s1_t_offset = stall_frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i0_s2_v_offset = stall_frn_fdis_iu6_i0_s1_t_offset + 3;
parameter stall_frn_fdis_iu6_i0_s2_a_offset = stall_frn_fdis_iu6_i0_s2_v_offset + 1;
parameter stall_frn_fdis_iu6_i0_s2_p_offset = stall_frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s2_itag_offset = stall_frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s2_t_offset = stall_frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i0_s3_v_offset = stall_frn_fdis_iu6_i0_s2_t_offset + 3;
parameter stall_frn_fdis_iu6_i0_s3_a_offset = stall_frn_fdis_iu6_i0_s3_v_offset + 1;
parameter stall_frn_fdis_iu6_i0_s3_p_offset = stall_frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s3_itag_offset = stall_frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i0_s3_t_offset = stall_frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i1_vld_offset = stall_frn_fdis_iu6_i0_s3_t_offset + 3;
parameter stall_frn_fdis_iu6_i1_itag_offset = stall_frn_fdis_iu6_i1_vld_offset + 1;
parameter stall_frn_fdis_iu6_i1_ucode_offset = stall_frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i1_ucode_cnt_offset = stall_frn_fdis_iu6_i1_ucode_offset + 3;
parameter stall_frn_fdis_iu6_i1_fuse_nop_offset = stall_frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC;
parameter stall_frn_fdis_iu6_i1_rte_lq_offset = stall_frn_fdis_iu6_i1_fuse_nop_offset + 1;
parameter stall_frn_fdis_iu6_i1_rte_sq_offset = stall_frn_fdis_iu6_i1_rte_lq_offset + 1;
parameter stall_frn_fdis_iu6_i1_rte_fx0_offset = stall_frn_fdis_iu6_i1_rte_sq_offset + 1;
parameter stall_frn_fdis_iu6_i1_rte_fx1_offset = stall_frn_fdis_iu6_i1_rte_fx0_offset + 1;
parameter stall_frn_fdis_iu6_i1_rte_axu0_offset = stall_frn_fdis_iu6_i1_rte_fx1_offset + 1;
parameter stall_frn_fdis_iu6_i1_rte_axu1_offset = stall_frn_fdis_iu6_i1_rte_axu0_offset + 1;
parameter stall_frn_fdis_iu6_i1_valop_offset = stall_frn_fdis_iu6_i1_rte_axu1_offset + 1;
parameter stall_frn_fdis_iu6_i1_ord_offset = stall_frn_fdis_iu6_i1_valop_offset + 1;
parameter stall_frn_fdis_iu6_i1_cord_offset = stall_frn_fdis_iu6_i1_ord_offset + 1;
parameter stall_frn_fdis_iu6_i1_error_offset = stall_frn_fdis_iu6_i1_cord_offset + 1;
parameter stall_frn_fdis_iu6_i1_btb_entry_offset = stall_frn_fdis_iu6_i1_error_offset + 3;
parameter stall_frn_fdis_iu6_i1_btb_hist_offset = stall_frn_fdis_iu6_i1_btb_entry_offset + 1;
parameter stall_frn_fdis_iu6_i1_bta_val_offset = stall_frn_fdis_iu6_i1_btb_hist_offset + 2;
parameter stall_frn_fdis_iu6_i1_fusion_offset = stall_frn_fdis_iu6_i1_bta_val_offset + 1;
parameter stall_frn_fdis_iu6_i1_spec_offset = stall_frn_fdis_iu6_i1_fusion_offset + 20;
parameter stall_frn_fdis_iu6_i1_type_fp_offset = stall_frn_fdis_iu6_i1_spec_offset + 1;
parameter stall_frn_fdis_iu6_i1_type_ap_offset = stall_frn_fdis_iu6_i1_type_fp_offset + 1;
parameter stall_frn_fdis_iu6_i1_type_spv_offset = stall_frn_fdis_iu6_i1_type_ap_offset + 1;
parameter stall_frn_fdis_iu6_i1_type_st_offset = stall_frn_fdis_iu6_i1_type_spv_offset + 1;
parameter stall_frn_fdis_iu6_i1_async_block_offset = stall_frn_fdis_iu6_i1_type_st_offset + 1;
parameter stall_frn_fdis_iu6_i1_np1_flush_offset = stall_frn_fdis_iu6_i1_async_block_offset + 1;
parameter stall_frn_fdis_iu6_i1_core_block_offset = stall_frn_fdis_iu6_i1_np1_flush_offset + 1;
parameter stall_frn_fdis_iu6_i1_isram_offset = stall_frn_fdis_iu6_i1_core_block_offset + 1;
parameter stall_frn_fdis_iu6_i1_isload_offset = stall_frn_fdis_iu6_i1_isram_offset + 1;
parameter stall_frn_fdis_iu6_i1_isstore_offset = stall_frn_fdis_iu6_i1_isload_offset + 1;
parameter stall_frn_fdis_iu6_i1_instr_offset = stall_frn_fdis_iu6_i1_isstore_offset + 1;
parameter stall_frn_fdis_iu6_i1_ifar_offset = stall_frn_fdis_iu6_i1_instr_offset + 32;
parameter stall_frn_fdis_iu6_i1_bta_offset = stall_frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH);
parameter stall_frn_fdis_iu6_i1_br_pred_offset = stall_frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH);
parameter stall_frn_fdis_iu6_i1_bh_update_offset = stall_frn_fdis_iu6_i1_br_pred_offset + 1;
parameter stall_frn_fdis_iu6_i1_bh0_hist_offset = stall_frn_fdis_iu6_i1_bh_update_offset + 1;
parameter stall_frn_fdis_iu6_i1_bh1_hist_offset = stall_frn_fdis_iu6_i1_bh0_hist_offset + 2;
parameter stall_frn_fdis_iu6_i1_bh2_hist_offset = stall_frn_fdis_iu6_i1_bh1_hist_offset + 2;
parameter stall_frn_fdis_iu6_i1_gshare_offset = stall_frn_fdis_iu6_i1_bh2_hist_offset + 2;
parameter stall_frn_fdis_iu6_i1_ls_ptr_offset = stall_frn_fdis_iu6_i1_gshare_offset + 18;
parameter stall_frn_fdis_iu6_i1_match_offset = stall_frn_fdis_iu6_i1_ls_ptr_offset + 3;
parameter stall_frn_fdis_iu6_i1_ilat_offset = stall_frn_fdis_iu6_i1_match_offset + 1;
parameter stall_frn_fdis_iu6_i1_t1_v_offset = stall_frn_fdis_iu6_i1_ilat_offset + 4;
parameter stall_frn_fdis_iu6_i1_t1_t_offset = stall_frn_fdis_iu6_i1_t1_v_offset + 1;
parameter stall_frn_fdis_iu6_i1_t1_a_offset = stall_frn_fdis_iu6_i1_t1_t_offset + 3;
parameter stall_frn_fdis_iu6_i1_t1_p_offset = stall_frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_t2_v_offset = stall_frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_t2_a_offset = stall_frn_fdis_iu6_i1_t2_v_offset + 1;
parameter stall_frn_fdis_iu6_i1_t2_p_offset = stall_frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_t2_t_offset = stall_frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_t3_v_offset = stall_frn_fdis_iu6_i1_t2_t_offset + 3;
parameter stall_frn_fdis_iu6_i1_t3_a_offset = stall_frn_fdis_iu6_i1_t3_v_offset + 1;
parameter stall_frn_fdis_iu6_i1_t3_p_offset = stall_frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_t3_t_offset = stall_frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s1_v_offset = stall_frn_fdis_iu6_i1_t3_t_offset + 3;
parameter stall_frn_fdis_iu6_i1_s1_a_offset = stall_frn_fdis_iu6_i1_s1_v_offset + 1;
parameter stall_frn_fdis_iu6_i1_s1_p_offset = stall_frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s1_itag_offset = stall_frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s1_t_offset = stall_frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i1_s1_dep_hit_offset = stall_frn_fdis_iu6_i1_s1_t_offset + 3;
parameter stall_frn_fdis_iu6_i1_s2_v_offset = stall_frn_fdis_iu6_i1_s1_dep_hit_offset + 1;
parameter stall_frn_fdis_iu6_i1_s2_a_offset = stall_frn_fdis_iu6_i1_s2_v_offset + 1;
parameter stall_frn_fdis_iu6_i1_s2_p_offset = stall_frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s2_itag_offset = stall_frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s2_t_offset = stall_frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i1_s2_dep_hit_offset = stall_frn_fdis_iu6_i1_s2_t_offset + 3;
parameter stall_frn_fdis_iu6_i1_s3_v_offset = stall_frn_fdis_iu6_i1_s2_dep_hit_offset + 1;
parameter stall_frn_fdis_iu6_i1_s3_a_offset = stall_frn_fdis_iu6_i1_s3_v_offset + 1;
parameter stall_frn_fdis_iu6_i1_s3_p_offset = stall_frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s3_itag_offset = stall_frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC;
parameter stall_frn_fdis_iu6_i1_s3_t_offset = stall_frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC;
parameter stall_frn_fdis_iu6_i1_s3_dep_hit_offset = stall_frn_fdis_iu6_i1_s3_t_offset + 3;
parameter perf_iu5_stall_offset = stall_frn_fdis_iu6_i1_s3_dep_hit_offset + 1;
parameter perf_iu5_cpl_credit_stall_offset = perf_iu5_stall_offset + 1;
parameter perf_iu5_gpr_credit_stall_offset = perf_iu5_cpl_credit_stall_offset + 1;
parameter perf_iu5_cr_credit_stall_offset = perf_iu5_gpr_credit_stall_offset + 1;
parameter perf_iu5_lr_credit_stall_offset = perf_iu5_cr_credit_stall_offset + 1;
parameter perf_iu5_ctr_credit_stall_offset = perf_iu5_lr_credit_stall_offset + 1;
parameter perf_iu5_xer_credit_stall_offset = perf_iu5_ctr_credit_stall_offset + 1;
parameter perf_iu5_br_hold_stall_offset = perf_iu5_xer_credit_stall_offset + 1;
parameter perf_iu5_axu_hold_stall_offset = perf_iu5_br_hold_stall_offset + 1;
parameter scan_right = perf_iu5_axu_hold_stall_offset + 1 - 1;
// scan
wire [0:scan_right] siv;
wire [0:scan_right] sov;
wire [0:4] map_siv;
wire [0:4] map_sov;
wire tidn;
wire tiup;
// iu6 latches
wire frn_fdis_iu6_i0_act;
wire frn_fdis_iu6_i0_vld_d;
wire frn_fdis_iu6_i0_vld_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag_l2;
wire [0:2] frn_fdis_iu6_i0_ucode_d;
wire [0:2] frn_fdis_iu6_i0_ucode_l2;
wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt_l2;
wire frn_fdis_iu6_i0_2ucode_d;
wire frn_fdis_iu6_i0_2ucode_l2;
wire frn_fdis_iu6_i0_fuse_nop_d;
wire frn_fdis_iu6_i0_fuse_nop_l2;
wire frn_fdis_iu6_i0_rte_lq_d;
wire frn_fdis_iu6_i0_rte_lq_l2;
wire frn_fdis_iu6_i0_rte_sq_d;
wire frn_fdis_iu6_i0_rte_sq_l2;
wire frn_fdis_iu6_i0_rte_fx0_d;
wire frn_fdis_iu6_i0_rte_fx0_l2;
wire frn_fdis_iu6_i0_rte_fx1_d;
wire frn_fdis_iu6_i0_rte_fx1_l2;
wire frn_fdis_iu6_i0_rte_axu0_d;
wire frn_fdis_iu6_i0_rte_axu0_l2;
wire frn_fdis_iu6_i0_rte_axu1_d;
wire frn_fdis_iu6_i0_rte_axu1_l2;
wire frn_fdis_iu6_i0_valop_d;
wire frn_fdis_iu6_i0_valop_l2;
wire frn_fdis_iu6_i0_ord_d;
wire frn_fdis_iu6_i0_ord_l2;
wire frn_fdis_iu6_i0_cord_d;
wire frn_fdis_iu6_i0_cord_l2;
wire [0:2] frn_fdis_iu6_i0_error_d;
wire [0:2] frn_fdis_iu6_i0_error_l2;
wire frn_fdis_iu6_i0_btb_entry_d;
wire frn_fdis_iu6_i0_btb_entry_l2;
wire [0:1] frn_fdis_iu6_i0_btb_hist_d;
wire [0:1] frn_fdis_iu6_i0_btb_hist_l2;
wire frn_fdis_iu6_i0_bta_val_d;
wire frn_fdis_iu6_i0_bta_val_l2;
wire [0:19] frn_fdis_iu6_i0_fusion_d;
wire [0:19] frn_fdis_iu6_i0_fusion_l2;
wire frn_fdis_iu6_i0_spec_d;
wire frn_fdis_iu6_i0_spec_l2;
wire frn_fdis_iu6_i0_type_fp_d;
wire frn_fdis_iu6_i0_type_fp_l2;
wire frn_fdis_iu6_i0_type_ap_d;
wire frn_fdis_iu6_i0_type_ap_l2;
wire frn_fdis_iu6_i0_type_spv_d;
wire frn_fdis_iu6_i0_type_spv_l2;
wire frn_fdis_iu6_i0_type_st_d;
wire frn_fdis_iu6_i0_type_st_l2;
wire frn_fdis_iu6_i0_async_block_d;
wire frn_fdis_iu6_i0_async_block_l2;
wire frn_fdis_iu6_i0_np1_flush_d;
wire frn_fdis_iu6_i0_np1_flush_l2;
wire frn_fdis_iu6_i0_core_block_d;
wire frn_fdis_iu6_i0_core_block_l2;
wire frn_fdis_iu6_i0_isram_d;
wire frn_fdis_iu6_i0_isram_l2;
wire frn_fdis_iu6_i0_isload_d;
wire frn_fdis_iu6_i0_isload_l2;
wire frn_fdis_iu6_i0_isstore_d;
wire frn_fdis_iu6_i0_isstore_l2;
wire [0:31] frn_fdis_iu6_i0_instr_d;
wire [0:31] frn_fdis_iu6_i0_instr_l2;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar_d;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar_l2;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta_d;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta_l2;
wire frn_fdis_iu6_i0_br_pred_d;
wire frn_fdis_iu6_i0_br_pred_l2;
wire frn_fdis_iu6_i0_bh_update_d;
wire frn_fdis_iu6_i0_bh_update_l2;
wire [0:1] frn_fdis_iu6_i0_bh0_hist_d;
wire [0:1] frn_fdis_iu6_i0_bh0_hist_l2;
wire [0:1] frn_fdis_iu6_i0_bh1_hist_d;
wire [0:1] frn_fdis_iu6_i0_bh1_hist_l2;
wire [0:1] frn_fdis_iu6_i0_bh2_hist_d;
wire [0:1] frn_fdis_iu6_i0_bh2_hist_l2;
wire [0:17] frn_fdis_iu6_i0_gshare_d;
wire [0:17] frn_fdis_iu6_i0_gshare_l2;
wire [0:2] frn_fdis_iu6_i0_ls_ptr_d;
wire [0:2] frn_fdis_iu6_i0_ls_ptr_l2;
wire frn_fdis_iu6_i0_match_d;
wire frn_fdis_iu6_i0_match_l2;
wire [0:3] frn_fdis_iu6_i0_ilat_d;
wire [0:3] frn_fdis_iu6_i0_ilat_l2;
wire frn_fdis_iu6_i0_t1_v_d;
wire frn_fdis_iu6_i0_t1_v_l2;
wire [0:2] frn_fdis_iu6_i0_t1_t_d;
wire [0:2] frn_fdis_iu6_i0_t1_t_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p_l2;
wire frn_fdis_iu6_i0_t2_v_d;
wire frn_fdis_iu6_i0_t2_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p_l2;
wire [0:2] frn_fdis_iu6_i0_t2_t_d;
wire [0:2] frn_fdis_iu6_i0_t2_t_l2;
wire frn_fdis_iu6_i0_t3_v_d;
wire frn_fdis_iu6_i0_t3_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p_l2;
wire [0:2] frn_fdis_iu6_i0_t3_t_d;
wire [0:2] frn_fdis_iu6_i0_t3_t_l2;
wire frn_fdis_iu6_i0_s1_v_d;
wire frn_fdis_iu6_i0_s1_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag_l2;
wire [0:2] frn_fdis_iu6_i0_s1_t_d;
wire [0:2] frn_fdis_iu6_i0_s1_t_l2;
wire frn_fdis_iu6_i0_s2_v_d;
wire frn_fdis_iu6_i0_s2_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag_l2;
wire [0:2] frn_fdis_iu6_i0_s2_t_d;
wire [0:2] frn_fdis_iu6_i0_s2_t_l2;
wire frn_fdis_iu6_i0_s3_v_d;
wire frn_fdis_iu6_i0_s3_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag_l2;
wire [0:2] frn_fdis_iu6_i0_s3_t_d;
wire [0:2] frn_fdis_iu6_i0_s3_t_l2;
wire frn_fdis_iu6_i1_act;
wire frn_fdis_iu6_i1_vld_d;
wire frn_fdis_iu6_i1_vld_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag_l2;
wire [0:2] frn_fdis_iu6_i1_ucode_d;
wire [0:2] frn_fdis_iu6_i1_ucode_l2;
wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt_l2;
wire frn_fdis_iu6_i1_fuse_nop_d;
wire frn_fdis_iu6_i1_fuse_nop_l2;
wire frn_fdis_iu6_i1_rte_lq_d;
wire frn_fdis_iu6_i1_rte_lq_l2;
wire frn_fdis_iu6_i1_rte_sq_d;
wire frn_fdis_iu6_i1_rte_sq_l2;
wire frn_fdis_iu6_i1_rte_fx0_d;
wire frn_fdis_iu6_i1_rte_fx0_l2;
wire frn_fdis_iu6_i1_rte_fx1_d;
wire frn_fdis_iu6_i1_rte_fx1_l2;
wire frn_fdis_iu6_i1_rte_axu0_d;
wire frn_fdis_iu6_i1_rte_axu0_l2;
wire frn_fdis_iu6_i1_rte_axu1_d;
wire frn_fdis_iu6_i1_rte_axu1_l2;
wire frn_fdis_iu6_i1_valop_d;
wire frn_fdis_iu6_i1_valop_l2;
wire frn_fdis_iu6_i1_ord_d;
wire frn_fdis_iu6_i1_ord_l2;
wire frn_fdis_iu6_i1_cord_d;
wire frn_fdis_iu6_i1_cord_l2;
wire [0:2] frn_fdis_iu6_i1_error_d;
wire [0:2] frn_fdis_iu6_i1_error_l2;
wire frn_fdis_iu6_i1_btb_entry_d;
wire frn_fdis_iu6_i1_btb_entry_l2;
wire [0:1] frn_fdis_iu6_i1_btb_hist_d;
wire [0:1] frn_fdis_iu6_i1_btb_hist_l2;
wire frn_fdis_iu6_i1_bta_val_d;
wire frn_fdis_iu6_i1_bta_val_l2;
wire [0:19] frn_fdis_iu6_i1_fusion_d;
wire [0:19] frn_fdis_iu6_i1_fusion_l2;
wire frn_fdis_iu6_i1_spec_d;
wire frn_fdis_iu6_i1_spec_l2;
wire frn_fdis_iu6_i1_type_fp_d;
wire frn_fdis_iu6_i1_type_fp_l2;
wire frn_fdis_iu6_i1_type_ap_d;
wire frn_fdis_iu6_i1_type_ap_l2;
wire frn_fdis_iu6_i1_type_spv_d;
wire frn_fdis_iu6_i1_type_spv_l2;
wire frn_fdis_iu6_i1_type_st_d;
wire frn_fdis_iu6_i1_type_st_l2;
wire frn_fdis_iu6_i1_async_block_d;
wire frn_fdis_iu6_i1_async_block_l2;
wire frn_fdis_iu6_i1_np1_flush_d;
wire frn_fdis_iu6_i1_np1_flush_l2;
wire frn_fdis_iu6_i1_core_block_d;
wire frn_fdis_iu6_i1_core_block_l2;
wire frn_fdis_iu6_i1_isram_d;
wire frn_fdis_iu6_i1_isram_l2;
wire frn_fdis_iu6_i1_isload_d;
wire frn_fdis_iu6_i1_isload_l2;
wire frn_fdis_iu6_i1_isstore_d;
wire frn_fdis_iu6_i1_isstore_l2;
wire [0:31] frn_fdis_iu6_i1_instr_d;
wire [0:31] frn_fdis_iu6_i1_instr_l2;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar_d;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar_l2;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta_d;
wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta_l2;
wire frn_fdis_iu6_i1_br_pred_d;
wire frn_fdis_iu6_i1_br_pred_l2;
wire frn_fdis_iu6_i1_bh_update_d;
wire frn_fdis_iu6_i1_bh_update_l2;
wire [0:1] frn_fdis_iu6_i1_bh0_hist_d;
wire [0:1] frn_fdis_iu6_i1_bh0_hist_l2;
wire [0:1] frn_fdis_iu6_i1_bh1_hist_d;
wire [0:1] frn_fdis_iu6_i1_bh1_hist_l2;
wire [0:1] frn_fdis_iu6_i1_bh2_hist_d;
wire [0:1] frn_fdis_iu6_i1_bh2_hist_l2;
wire [0:17] frn_fdis_iu6_i1_gshare_d;
wire [0:17] frn_fdis_iu6_i1_gshare_l2;
wire [0:2] frn_fdis_iu6_i1_ls_ptr_d;
wire [0:2] frn_fdis_iu6_i1_ls_ptr_l2;
wire frn_fdis_iu6_i1_match_d;
wire frn_fdis_iu6_i1_match_l2;
wire [0:3] frn_fdis_iu6_i1_ilat_d;
wire [0:3] frn_fdis_iu6_i1_ilat_l2;
wire frn_fdis_iu6_i1_t1_v_d;
wire frn_fdis_iu6_i1_t1_v_l2;
wire [0:2] frn_fdis_iu6_i1_t1_t_d;
wire [0:2] frn_fdis_iu6_i1_t1_t_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a_l2;
reg [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p_l2;
wire frn_fdis_iu6_i1_t2_v_d;
wire frn_fdis_iu6_i1_t2_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a_l2;
reg [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p_l2;
wire [0:2] frn_fdis_iu6_i1_t2_t_d;
wire [0:2] frn_fdis_iu6_i1_t2_t_l2;
wire frn_fdis_iu6_i1_t3_v_d;
wire frn_fdis_iu6_i1_t3_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a_l2;
reg [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p_l2;
wire [0:2] frn_fdis_iu6_i1_t3_t_d;
wire [0:2] frn_fdis_iu6_i1_t3_t_l2;
wire frn_fdis_iu6_i1_s1_v_d;
wire frn_fdis_iu6_i1_s1_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag_l2;
wire [0:2] frn_fdis_iu6_i1_s1_t_d;
wire [0:2] frn_fdis_iu6_i1_s1_t_l2;
wire frn_fdis_iu6_i1_s1_dep_hit_d;
wire frn_fdis_iu6_i1_s1_dep_hit_l2;
wire frn_fdis_iu6_i1_s2_v_d;
wire frn_fdis_iu6_i1_s2_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag_l2;
wire [0:2] frn_fdis_iu6_i1_s2_t_d;
wire [0:2] frn_fdis_iu6_i1_s2_t_l2;
wire frn_fdis_iu6_i1_s2_dep_hit_d;
wire frn_fdis_iu6_i1_s2_dep_hit_l2;
wire frn_fdis_iu6_i1_s3_v_d;
wire frn_fdis_iu6_i1_s3_v_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a_l2;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p_d;
wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p_l2;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag_d;
wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag_l2;
wire [0:2] frn_fdis_iu6_i1_s3_t_d;
wire [0:2] frn_fdis_iu6_i1_s3_t_l2;
wire frn_fdis_iu6_i1_s3_dep_hit_d;
wire frn_fdis_iu6_i1_s3_dep_hit_l2;
// iu6 stall latches
wire stall_frn_fdis_iu6_i0_act;
wire stall_frn_fdis_iu6_i0_vld_d;
wire stall_frn_fdis_iu6_i0_vld_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i0_ucode_d;
wire [0:2] stall_frn_fdis_iu6_i0_ucode_l2;
wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i0_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i0_ucode_cnt_l2;
wire stall_frn_fdis_iu6_i0_2ucode_d;
wire stall_frn_fdis_iu6_i0_2ucode_l2;
wire stall_frn_fdis_iu6_i0_fuse_nop_d;
wire stall_frn_fdis_iu6_i0_fuse_nop_l2;
wire stall_frn_fdis_iu6_i0_rte_lq_d;
wire stall_frn_fdis_iu6_i0_rte_lq_l2;
wire stall_frn_fdis_iu6_i0_rte_sq_d;
wire stall_frn_fdis_iu6_i0_rte_sq_l2;
wire stall_frn_fdis_iu6_i0_rte_fx0_d;
wire stall_frn_fdis_iu6_i0_rte_fx0_l2;
wire stall_frn_fdis_iu6_i0_rte_fx1_d;
wire stall_frn_fdis_iu6_i0_rte_fx1_l2;
wire stall_frn_fdis_iu6_i0_rte_axu0_d;
wire stall_frn_fdis_iu6_i0_rte_axu0_l2;
wire stall_frn_fdis_iu6_i0_rte_axu1_d;
wire stall_frn_fdis_iu6_i0_rte_axu1_l2;
wire stall_frn_fdis_iu6_i0_valop_d;
wire stall_frn_fdis_iu6_i0_valop_l2;
wire stall_frn_fdis_iu6_i0_ord_d;
wire stall_frn_fdis_iu6_i0_ord_l2;
wire stall_frn_fdis_iu6_i0_cord_d;
wire stall_frn_fdis_iu6_i0_cord_l2;
wire [0:2] stall_frn_fdis_iu6_i0_error_d;
wire [0:2] stall_frn_fdis_iu6_i0_error_l2;
wire stall_frn_fdis_iu6_i0_btb_entry_d;
wire stall_frn_fdis_iu6_i0_btb_entry_l2;
wire [0:1] stall_frn_fdis_iu6_i0_btb_hist_d;
wire [0:1] stall_frn_fdis_iu6_i0_btb_hist_l2;
wire stall_frn_fdis_iu6_i0_bta_val_d;
wire stall_frn_fdis_iu6_i0_bta_val_l2;
wire [0:19] stall_frn_fdis_iu6_i0_fusion_d;
wire [0:19] stall_frn_fdis_iu6_i0_fusion_l2;
wire stall_frn_fdis_iu6_i0_spec_d;
wire stall_frn_fdis_iu6_i0_spec_l2;
wire stall_frn_fdis_iu6_i0_type_fp_d;
wire stall_frn_fdis_iu6_i0_type_fp_l2;
wire stall_frn_fdis_iu6_i0_type_ap_d;
wire stall_frn_fdis_iu6_i0_type_ap_l2;
wire stall_frn_fdis_iu6_i0_type_spv_d;
wire stall_frn_fdis_iu6_i0_type_spv_l2;
wire stall_frn_fdis_iu6_i0_type_st_d;
wire stall_frn_fdis_iu6_i0_type_st_l2;
wire stall_frn_fdis_iu6_i0_async_block_d;
wire stall_frn_fdis_iu6_i0_async_block_l2;
wire stall_frn_fdis_iu6_i0_np1_flush_d;
wire stall_frn_fdis_iu6_i0_np1_flush_l2;
wire stall_frn_fdis_iu6_i0_core_block_d;
wire stall_frn_fdis_iu6_i0_core_block_l2;
wire stall_frn_fdis_iu6_i0_isram_d;
wire stall_frn_fdis_iu6_i0_isram_l2;
wire stall_frn_fdis_iu6_i0_isload_d;
wire stall_frn_fdis_iu6_i0_isload_l2;
wire stall_frn_fdis_iu6_i0_isstore_d;
wire stall_frn_fdis_iu6_i0_isstore_l2;
wire [0:31] stall_frn_fdis_iu6_i0_instr_d;
wire [0:31] stall_frn_fdis_iu6_i0_instr_l2;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_ifar_d;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_ifar_l2;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_bta_d;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_bta_l2;
wire stall_frn_fdis_iu6_i0_br_pred_d;
wire stall_frn_fdis_iu6_i0_br_pred_l2;
wire stall_frn_fdis_iu6_i0_bh_update_d;
wire stall_frn_fdis_iu6_i0_bh_update_l2;
wire [0:1] stall_frn_fdis_iu6_i0_bh0_hist_d;
wire [0:1] stall_frn_fdis_iu6_i0_bh0_hist_l2;
wire [0:1] stall_frn_fdis_iu6_i0_bh1_hist_d;
wire [0:1] stall_frn_fdis_iu6_i0_bh1_hist_l2;
wire [0:1] stall_frn_fdis_iu6_i0_bh2_hist_d;
wire [0:1] stall_frn_fdis_iu6_i0_bh2_hist_l2;
wire [0:17] stall_frn_fdis_iu6_i0_gshare_d;
wire [0:17] stall_frn_fdis_iu6_i0_gshare_l2;
wire [0:2] stall_frn_fdis_iu6_i0_ls_ptr_d;
wire [0:2] stall_frn_fdis_iu6_i0_ls_ptr_l2;
wire stall_frn_fdis_iu6_i0_match_d;
wire stall_frn_fdis_iu6_i0_match_l2;
wire [0:3] stall_frn_fdis_iu6_i0_ilat_d;
wire [0:3] stall_frn_fdis_iu6_i0_ilat_l2;
wire stall_frn_fdis_iu6_i0_t1_v_d;
wire stall_frn_fdis_iu6_i0_t1_v_l2;
wire [0:2] stall_frn_fdis_iu6_i0_t1_t_d;
wire [0:2] stall_frn_fdis_iu6_i0_t1_t_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_p_l2;
wire stall_frn_fdis_iu6_i0_t2_v_d;
wire stall_frn_fdis_iu6_i0_t2_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_p_l2;
wire [0:2] stall_frn_fdis_iu6_i0_t2_t_d;
wire [0:2] stall_frn_fdis_iu6_i0_t2_t_l2;
wire stall_frn_fdis_iu6_i0_t3_v_d;
wire stall_frn_fdis_iu6_i0_t3_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_p_l2;
wire [0:2] stall_frn_fdis_iu6_i0_t3_t_d;
wire [0:2] stall_frn_fdis_iu6_i0_t3_t_l2;
wire stall_frn_fdis_iu6_i0_s1_v_d;
wire stall_frn_fdis_iu6_i0_s1_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_p_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s1_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s1_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i0_s1_t_d;
wire [0:2] stall_frn_fdis_iu6_i0_s1_t_l2;
wire stall_frn_fdis_iu6_i0_s2_v_d;
wire stall_frn_fdis_iu6_i0_s2_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_p_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s2_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s2_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i0_s2_t_d;
wire [0:2] stall_frn_fdis_iu6_i0_s2_t_l2;
wire stall_frn_fdis_iu6_i0_s3_v_d;
wire stall_frn_fdis_iu6_i0_s3_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_p_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s3_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s3_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i0_s3_t_d;
wire [0:2] stall_frn_fdis_iu6_i0_s3_t_l2;
wire stall_frn_fdis_iu6_i1_act;
wire stall_frn_fdis_iu6_i1_vld_d;
wire stall_frn_fdis_iu6_i1_vld_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i1_ucode_d;
wire [0:2] stall_frn_fdis_iu6_i1_ucode_l2;
wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i1_ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i1_ucode_cnt_l2;
wire stall_frn_fdis_iu6_i1_fuse_nop_d;
wire stall_frn_fdis_iu6_i1_fuse_nop_l2;
wire stall_frn_fdis_iu6_i1_rte_lq_d;
wire stall_frn_fdis_iu6_i1_rte_lq_l2;
wire stall_frn_fdis_iu6_i1_rte_sq_d;
wire stall_frn_fdis_iu6_i1_rte_sq_l2;
wire stall_frn_fdis_iu6_i1_rte_fx0_d;
wire stall_frn_fdis_iu6_i1_rte_fx0_l2;
wire stall_frn_fdis_iu6_i1_rte_fx1_d;
wire stall_frn_fdis_iu6_i1_rte_fx1_l2;
wire stall_frn_fdis_iu6_i1_rte_axu0_d;
wire stall_frn_fdis_iu6_i1_rte_axu0_l2;
wire stall_frn_fdis_iu6_i1_rte_axu1_d;
wire stall_frn_fdis_iu6_i1_rte_axu1_l2;
wire stall_frn_fdis_iu6_i1_valop_d;
wire stall_frn_fdis_iu6_i1_valop_l2;
wire stall_frn_fdis_iu6_i1_ord_d;
wire stall_frn_fdis_iu6_i1_ord_l2;
wire stall_frn_fdis_iu6_i1_cord_d;
wire stall_frn_fdis_iu6_i1_cord_l2;
wire [0:2] stall_frn_fdis_iu6_i1_error_d;
wire [0:2] stall_frn_fdis_iu6_i1_error_l2;
wire stall_frn_fdis_iu6_i1_btb_entry_d;
wire stall_frn_fdis_iu6_i1_btb_entry_l2;
wire [0:1] stall_frn_fdis_iu6_i1_btb_hist_d;
wire [0:1] stall_frn_fdis_iu6_i1_btb_hist_l2;
wire stall_frn_fdis_iu6_i1_bta_val_d;
wire stall_frn_fdis_iu6_i1_bta_val_l2;
wire [0:19] stall_frn_fdis_iu6_i1_fusion_d;
wire [0:19] stall_frn_fdis_iu6_i1_fusion_l2;
wire stall_frn_fdis_iu6_i1_spec_d;
wire stall_frn_fdis_iu6_i1_spec_l2;
wire stall_frn_fdis_iu6_i1_type_fp_d;
wire stall_frn_fdis_iu6_i1_type_fp_l2;
wire stall_frn_fdis_iu6_i1_type_ap_d;
wire stall_frn_fdis_iu6_i1_type_ap_l2;
wire stall_frn_fdis_iu6_i1_type_spv_d;
wire stall_frn_fdis_iu6_i1_type_spv_l2;
wire stall_frn_fdis_iu6_i1_type_st_d;
wire stall_frn_fdis_iu6_i1_type_st_l2;
wire stall_frn_fdis_iu6_i1_async_block_d;
wire stall_frn_fdis_iu6_i1_async_block_l2;
wire stall_frn_fdis_iu6_i1_np1_flush_d;
wire stall_frn_fdis_iu6_i1_np1_flush_l2;
wire stall_frn_fdis_iu6_i1_core_block_d;
wire stall_frn_fdis_iu6_i1_core_block_l2;
wire stall_frn_fdis_iu6_i1_isram_d;
wire stall_frn_fdis_iu6_i1_isram_l2;
wire stall_frn_fdis_iu6_i1_isload_d;
wire stall_frn_fdis_iu6_i1_isload_l2;
wire stall_frn_fdis_iu6_i1_isstore_d;
wire stall_frn_fdis_iu6_i1_isstore_l2;
wire [0:31] stall_frn_fdis_iu6_i1_instr_d;
wire [0:31] stall_frn_fdis_iu6_i1_instr_l2;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_ifar_d;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_ifar_l2;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_bta_d;
wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_bta_l2;
wire stall_frn_fdis_iu6_i1_br_pred_d;
wire stall_frn_fdis_iu6_i1_br_pred_l2;
wire stall_frn_fdis_iu6_i1_bh_update_d;
wire stall_frn_fdis_iu6_i1_bh_update_l2;
wire [0:1] stall_frn_fdis_iu6_i1_bh0_hist_d;
wire [0:1] stall_frn_fdis_iu6_i1_bh0_hist_l2;
wire [0:1] stall_frn_fdis_iu6_i1_bh1_hist_d;
wire [0:1] stall_frn_fdis_iu6_i1_bh1_hist_l2;
wire [0:1] stall_frn_fdis_iu6_i1_bh2_hist_d;
wire [0:1] stall_frn_fdis_iu6_i1_bh2_hist_l2;
wire [0:17] stall_frn_fdis_iu6_i1_gshare_d;
wire [0:17] stall_frn_fdis_iu6_i1_gshare_l2;
wire [0:2] stall_frn_fdis_iu6_i1_ls_ptr_d;
wire [0:2] stall_frn_fdis_iu6_i1_ls_ptr_l2;
wire stall_frn_fdis_iu6_i1_match_d;
wire stall_frn_fdis_iu6_i1_match_l2;
wire [0:3] stall_frn_fdis_iu6_i1_ilat_d;
wire [0:3] stall_frn_fdis_iu6_i1_ilat_l2;
wire stall_frn_fdis_iu6_i1_t1_v_d;
wire stall_frn_fdis_iu6_i1_t1_v_l2;
wire [0:2] stall_frn_fdis_iu6_i1_t1_t_d;
wire [0:2] stall_frn_fdis_iu6_i1_t1_t_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_p_l2;
wire stall_frn_fdis_iu6_i1_t2_v_d;
wire stall_frn_fdis_iu6_i1_t2_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_p_l2;
wire [0:2] stall_frn_fdis_iu6_i1_t2_t_d;
wire [0:2] stall_frn_fdis_iu6_i1_t2_t_l2;
wire stall_frn_fdis_iu6_i1_t3_v_d;
wire stall_frn_fdis_iu6_i1_t3_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_p_l2;
wire [0:2] stall_frn_fdis_iu6_i1_t3_t_d;
wire [0:2] stall_frn_fdis_iu6_i1_t3_t_l2;
wire stall_frn_fdis_iu6_i1_s1_v_d;
wire stall_frn_fdis_iu6_i1_s1_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_p_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s1_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s1_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i1_s1_t_d;
wire [0:2] stall_frn_fdis_iu6_i1_s1_t_l2;
wire stall_frn_fdis_iu6_i1_s1_dep_hit_d;
wire stall_frn_fdis_iu6_i1_s1_dep_hit_l2;
wire stall_frn_fdis_iu6_i1_s2_v_d;
wire stall_frn_fdis_iu6_i1_s2_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_p_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s2_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s2_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i1_s2_t_d;
wire [0:2] stall_frn_fdis_iu6_i1_s2_t_l2;
wire stall_frn_fdis_iu6_i1_s2_dep_hit_d;
wire stall_frn_fdis_iu6_i1_s2_dep_hit_l2;
wire stall_frn_fdis_iu6_i1_s3_v_d;
wire stall_frn_fdis_iu6_i1_s3_v_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_a_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_a_l2;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_p_d;
wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_p_l2;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s3_itag_d;
wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s3_itag_l2;
wire [0:2] stall_frn_fdis_iu6_i1_s3_t_d;
wire [0:2] stall_frn_fdis_iu6_i1_s3_t_l2;
wire stall_frn_fdis_iu6_i1_s3_dep_hit_d;
wire stall_frn_fdis_iu6_i1_s3_dep_hit_l2;
//stall
wire [0:18] fdis_frn_iu6_stall_d;
wire [0:18] fdis_frn_iu6_stall_l2;
wire fdis_frn_iu6_stall_dly;
// Next Itags
wire [0:`ITAG_SIZE_ENC-1] next_itag_0_d;
wire [0:`ITAG_SIZE_ENC-1] next_itag_0_l2;
wire [0:`ITAG_SIZE_ENC-1] next_itag_1_d;
wire [0:`ITAG_SIZE_ENC-1] next_itag_1_l2;
wire [0:`ITAG_SIZE_ENC-1] i0_itag_next;
wire [0:`ITAG_SIZE_ENC-1] i1_itag_next;
wire inc_0;
wire inc_1;
// Credit counters
reg [0:`CPL_Q_DEPTH_ENC] cp_high_credit_cnt_d;
wire [0:`CPL_Q_DEPTH_ENC] cp_high_credit_cnt_l2;
reg [0:`CPL_Q_DEPTH_ENC] cp_med_credit_cnt_d;
wire [0:`CPL_Q_DEPTH_ENC] cp_med_credit_cnt_l2;
wire [0:`CPL_Q_DEPTH_ENC] cp_credit_cnt_mux;
wire [0:`CPL_Q_DEPTH_ENC] high_cnt_plus2_temp, high_cnt_plus2;
wire [0:`CPL_Q_DEPTH_ENC] high_cnt_plus1_temp, high_cnt_plus1;
wire [0:`CPL_Q_DEPTH_ENC] high_cnt_minus1_temp, high_cnt_minus1;
wire [0:`CPL_Q_DEPTH_ENC] high_cnt_minus2_temp, high_cnt_minus2;
wire [0:`CPL_Q_DEPTH_ENC] med_cnt_plus2_temp, med_cnt_plus2;
wire [0:`CPL_Q_DEPTH_ENC] med_cnt_plus1_temp, med_cnt_plus1;
wire [0:`CPL_Q_DEPTH_ENC] med_cnt_minus1_temp, med_cnt_minus1;
wire [0:`CPL_Q_DEPTH_ENC] med_cnt_minus2_temp, med_cnt_minus2;
// Rolling count for ucode instructions
reg [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_d;
wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_l2;
// Save count to flush to for flushing to ucode
reg [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_save_d;
wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_save_l2;
// Latch to delay the flush signal
wire cp_flush_d;
wire cp_flush_l2;
wire cp_flush_into_uc_d;
wire cp_flush_into_uc_l2;
wire br_iu_hold_d;
wire br_iu_hold_l2;
wire hold_instructions_d;
wire hold_instructions_l2;
// completion queue is empty
wire cp_rn_empty_l2;
wire high_pri_mask_l2;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`GPR_POOL_ENC-1] gpr_iu5_i0_src1_p;
wire [0:`GPR_POOL_ENC-1] gpr_iu5_i0_src2_p;
wire [0:`GPR_POOL_ENC-1] gpr_iu5_i0_src3_p;
wire [0:`GPR_POOL_ENC-1] gpr_iu5_i1_src1_p;
wire [0:`GPR_POOL_ENC-1] gpr_iu5_i1_src2_p;
wire [0:`GPR_POOL_ENC-1] gpr_iu5_i1_src3_p;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i0_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i0_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i0_src3_itag;
wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i1_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i1_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i1_src3_itag;
// I1 dependency hit vs I0 for each source this is used by RV
wire gpr_s1_dep_hit;
wire gpr_s2_dep_hit;
wire gpr_s3_dep_hit;
// Free from completion to the gpr pool
wire gpr_cp_i0_wr_v;
wire [0:`GPR_POOL_ENC-1] gpr_cp_i0_wr_a;
wire [0:`GPR_POOL_ENC-1] gpr_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] gpr_cp_i0_wr_itag;
wire gpr_cp_i1_wr_v;
wire [0:`GPR_POOL_ENC-1] gpr_cp_i1_wr_a;
wire [0:`GPR_POOL_ENC-1] gpr_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] gpr_cp_i1_wr_itag;
wire gpr_spec_i0_wr_v;
wire gpr_spec_i0_wr_v_fast;
wire [0:`GPR_POOL_ENC-1] gpr_spec_i0_wr_a;
wire [0:`GPR_POOL_ENC-1] gpr_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] gpr_spec_i0_wr_itag;
wire gpr_spec_i1_wr_v;
wire gpr_spec_i1_wr_v_fast;
wire [0:`GPR_POOL_ENC-1] gpr_spec_i1_wr_a;
wire [0:`GPR_POOL_ENC-1] gpr_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] gpr_spec_i1_wr_itag;
wire next_gpr_0_v;
wire [0:`GPR_POOL_ENC-1] next_gpr_0;
wire next_gpr_1_v;
wire [0:`GPR_POOL_ENC-1] next_gpr_1;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`CR_POOL_ENC-1] cr_iu5_i0_src1_p;
wire [0:`CR_POOL_ENC-1] cr_iu5_i0_src2_p;
wire [0:`CR_POOL_ENC-1] cr_iu5_i0_src3_p;
wire [0:`CR_POOL_ENC-1] cr_iu5_i1_src1_p;
wire [0:`CR_POOL_ENC-1] cr_iu5_i1_src2_p;
wire [0:`CR_POOL_ENC-1] cr_iu5_i1_src3_p;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i0_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i0_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i0_src3_itag;
wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i1_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i1_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i1_src3_itag;
// I1 dependency hit vs I0 for each source this is used by RV
wire cr_s1_dep_hit;
wire cr_s2_dep_hit;
wire cr_s3_dep_hit;
// Free from completion to the cr pool
wire cr_cp_i0_wr_v;
wire [0:`CR_POOL_ENC-1] cr_cp_i0_wr_a;
wire [0:`CR_POOL_ENC-1] cr_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] cr_cp_i0_wr_itag;
wire cr_cp_i1_wr_v;
wire [0:`CR_POOL_ENC-1] cr_cp_i1_wr_a;
wire [0:`CR_POOL_ENC-1] cr_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] cr_cp_i1_wr_itag;
wire cr_spec_i0_wr_v;
wire cr_spec_i0_wr_v_fast;
wire [0:`CR_POOL_ENC-1] cr_spec_i0_wr_a;
wire [0:`CR_POOL_ENC-1] cr_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] cr_spec_i0_wr_itag;
wire cr_spec_i1_wr_v;
wire cr_spec_i1_wr_v_fast;
wire [0:`CR_POOL_ENC-1] cr_spec_i1_wr_a;
wire [0:`CR_POOL_ENC-1] cr_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] cr_spec_i1_wr_itag;
wire next_cr_0_v;
wire [0:`CR_POOL_ENC-1] next_cr_0;
wire next_cr_1_v;
wire [0:`CR_POOL_ENC-1] next_cr_1;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`LR_POOL_ENC-1] lr_iu5_i0_src1_p;
wire [0:`LR_POOL_ENC-1] lr_iu5_i0_src2_p;
wire [0:`LR_POOL_ENC-1] lr_iu5_i0_src3_p;
wire [0:`LR_POOL_ENC-1] lr_iu5_i1_src1_p;
wire [0:`LR_POOL_ENC-1] lr_iu5_i1_src2_p;
wire [0:`LR_POOL_ENC-1] lr_iu5_i1_src3_p;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i0_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i0_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i0_src3_itag;
wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i1_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i1_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i1_src3_itag;
// I1 dependency hit vs I0 for each source this is used by RV
wire lr_s1_dep_hit;
wire lr_s2_dep_hit;
wire lr_s3_dep_hit;
// Free from completion to the lr pool
wire lr_cp_i0_wr_v;
wire [0:`LR_POOL_ENC-1] lr_cp_i0_wr_a;
wire [0:`LR_POOL_ENC-1] lr_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] lr_cp_i0_wr_itag;
wire lr_cp_i1_wr_v;
wire [0:`LR_POOL_ENC-1] lr_cp_i1_wr_a;
wire [0:`LR_POOL_ENC-1] lr_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] lr_cp_i1_wr_itag;
wire lr_spec_i0_wr_v;
wire lr_spec_i0_wr_v_fast;
wire [0:`LR_POOL_ENC-1] lr_spec_i0_wr_a;
wire [0:`LR_POOL_ENC-1] lr_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] lr_spec_i0_wr_itag;
wire lr_spec_i1_wr_v;
wire lr_spec_i1_wr_v_fast;
wire [0:`LR_POOL_ENC-1] lr_spec_i1_wr_a;
wire [0:`LR_POOL_ENC-1] lr_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] lr_spec_i1_wr_itag;
wire next_lr_0_v;
wire [0:`LR_POOL_ENC-1] next_lr_0;
wire next_lr_1_v;
wire [0:`LR_POOL_ENC-1] next_lr_1;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`CTR_POOL_ENC-1] ctr_iu5_i0_src1_p;
wire [0:`CTR_POOL_ENC-1] ctr_iu5_i0_src2_p;
wire [0:`CTR_POOL_ENC-1] ctr_iu5_i0_src3_p;
wire [0:`CTR_POOL_ENC-1] ctr_iu5_i1_src1_p;
wire [0:`CTR_POOL_ENC-1] ctr_iu5_i1_src2_p;
wire [0:`CTR_POOL_ENC-1] ctr_iu5_i1_src3_p;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i0_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i0_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i0_src3_itag;
wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i1_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i1_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i1_src3_itag;
// I1 dependency hit vs I0 for each source this is used by RV
wire ctr_s1_dep_hit;
wire ctr_s2_dep_hit;
wire ctr_s3_dep_hit;
// Free from completion to the ctr pool
wire ctr_cp_i0_wr_v;
wire [0:`CTR_POOL_ENC-1] ctr_cp_i0_wr_a;
wire [0:`CTR_POOL_ENC-1] ctr_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] ctr_cp_i0_wr_itag;
wire ctr_cp_i1_wr_v;
wire [0:`CTR_POOL_ENC-1] ctr_cp_i1_wr_a;
wire [0:`CTR_POOL_ENC-1] ctr_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] ctr_cp_i1_wr_itag;
wire ctr_spec_i0_wr_v;
wire ctr_spec_i0_wr_v_fast;
wire [0:`CTR_POOL_ENC-1] ctr_spec_i0_wr_a;
wire [0:`CTR_POOL_ENC-1] ctr_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] ctr_spec_i0_wr_itag;
wire ctr_spec_i1_wr_v;
wire ctr_spec_i1_wr_v_fast;
wire [0:`CTR_POOL_ENC-1] ctr_spec_i1_wr_a;
wire [0:`CTR_POOL_ENC-1] ctr_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] ctr_spec_i1_wr_itag;
wire next_ctr_0_v;
wire [0:`CTR_POOL_ENC-1] next_ctr_0;
wire next_ctr_1_v;
wire [0:`CTR_POOL_ENC-1] next_ctr_1;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`XER_POOL_ENC-1] xer_iu5_i0_src1_p;
wire [0:`XER_POOL_ENC-1] xer_iu5_i0_src2_p;
wire [0:`XER_POOL_ENC-1] xer_iu5_i0_src3_p;
wire [0:`XER_POOL_ENC-1] xer_iu5_i1_src1_p;
wire [0:`XER_POOL_ENC-1] xer_iu5_i1_src2_p;
wire [0:`XER_POOL_ENC-1] xer_iu5_i1_src3_p;
// Source lookups from pools note may not be valid if source if type not of the right type
wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i0_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i0_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i0_src3_itag;
wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i1_src1_itag;
wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i1_src2_itag;
wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i1_src3_itag;
// I1 dependency hit vs I0 for each source this is used by RV
wire xer_s1_dep_hit;
wire xer_s2_dep_hit;
wire xer_s3_dep_hit;
// Free from completion to the xer pool
wire xer_cp_i0_wr_v;
wire [0:`XER_POOL_ENC-1] xer_cp_i0_wr_a;
wire [0:`XER_POOL_ENC-1] xer_cp_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] xer_cp_i0_wr_itag;
wire xer_cp_i1_wr_v;
wire [0:`XER_POOL_ENC-1] xer_cp_i1_wr_a;
wire [0:`XER_POOL_ENC-1] xer_cp_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] xer_cp_i1_wr_itag;
wire xer_spec_i0_wr_v;
wire xer_spec_i0_wr_v_fast;
wire [0:`XER_POOL_ENC-1] xer_spec_i0_wr_a;
wire [0:`XER_POOL_ENC-1] xer_spec_i0_wr_p;
wire [0:`ITAG_SIZE_ENC-1] xer_spec_i0_wr_itag;
wire xer_spec_i1_wr_v;
wire xer_spec_i1_wr_v_fast;
wire [0:`XER_POOL_ENC-1] xer_spec_i1_wr_a;
wire [0:`XER_POOL_ENC-1] xer_spec_i1_wr_p;
wire [0:`ITAG_SIZE_ENC-1] xer_spec_i1_wr_itag;
wire next_xer_0_v;
wire [0:`XER_POOL_ENC-1] next_xer_0;
wire next_xer_1_v;
wire [0:`XER_POOL_ENC-1] next_xer_1;
wire [0:1] gpr_send_cnt;
wire [0:1] cr_send_cnt;
wire [0:1] cr_send_t1_cnt;
wire [0:1] cr_send_t3_cnt;
wire [0:1] lr_send_cnt;
wire [0:1] ctr_send_cnt;
wire [0:1] xer_send_cnt;
wire [0:1] ucode_send_cnt;
wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_i0;
wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_i1;
wire cpl_credit_ok;
wire gpr_send_ok;
wire cr_send_ok;
wire lr_send_ok;
wire ctr_send_ok;
wire xer_send_ok;
wire cp_empty_ok;
wire send_instructions;
// Perfmon
wire perf_iu5_stall_d, perf_iu5_stall_l2;
wire perf_iu5_cpl_credit_stall_d, perf_iu5_cpl_credit_stall_l2;
wire perf_iu5_gpr_credit_stall_d, perf_iu5_gpr_credit_stall_l2;
wire perf_iu5_cr_credit_stall_d, perf_iu5_cr_credit_stall_l2;
wire perf_iu5_lr_credit_stall_d, perf_iu5_lr_credit_stall_l2;
wire perf_iu5_ctr_credit_stall_d, perf_iu5_ctr_credit_stall_l2;
wire perf_iu5_xer_credit_stall_d, perf_iu5_xer_credit_stall_l2;
wire perf_iu5_br_hold_stall_d, perf_iu5_br_hold_stall_l2;
wire perf_iu5_axu_hold_stall_d, perf_iu5_axu_hold_stall_l2;
// Pervasive
wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;
assign tidn = 1'b0;
assign tiup = 1'b1;
// outputs
assign frn_fdis_iu6_i0_vld = (fdis_frn_iu6_stall_l2[3] == 1'b0) ? frn_fdis_iu6_i0_vld_l2 :
stall_frn_fdis_iu6_i0_vld_l2;
assign frn_fdis_iu6_i0_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_itag_l2 :
stall_frn_fdis_iu6_i0_itag_l2;
assign frn_fdis_iu6_i0_ucode = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ucode_l2 :
stall_frn_fdis_iu6_i0_ucode_l2;
assign frn_fdis_iu6_i0_ucode_cnt = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ucode_cnt_l2 :
stall_frn_fdis_iu6_i0_ucode_cnt_l2;
assign frn_fdis_iu6_i0_2ucode = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_2ucode_l2 :
stall_frn_fdis_iu6_i0_2ucode_l2;
assign frn_fdis_iu6_i0_fuse_nop = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_fuse_nop_l2 :
stall_frn_fdis_iu6_i0_fuse_nop_l2;
assign frn_fdis_iu6_i0_rte_lq = (fdis_frn_iu6_stall_l2[5] == 1'b0) ? frn_fdis_iu6_i0_rte_lq_l2 :
stall_frn_fdis_iu6_i0_rte_lq_l2;
assign frn_fdis_iu6_i0_rte_sq = (fdis_frn_iu6_stall_l2[7] == 1'b0) ? frn_fdis_iu6_i0_rte_sq_l2 :
stall_frn_fdis_iu6_i0_rte_sq_l2;
assign frn_fdis_iu6_i0_rte_fx0 = (fdis_frn_iu6_stall_l2[9] == 1'b0) ? frn_fdis_iu6_i0_rte_fx0_l2 :
stall_frn_fdis_iu6_i0_rte_fx0_l2;
assign frn_fdis_iu6_i0_rte_fx1 = (fdis_frn_iu6_stall_l2[11] == 1'b0) ? frn_fdis_iu6_i0_rte_fx1_l2 :
stall_frn_fdis_iu6_i0_rte_fx1_l2;
assign frn_fdis_iu6_i0_rte_axu0 = (fdis_frn_iu6_stall_l2[13] == 1'b0) ? frn_fdis_iu6_i0_rte_axu0_l2 :
stall_frn_fdis_iu6_i0_rte_axu0_l2;
assign frn_fdis_iu6_i0_rte_axu1 = (fdis_frn_iu6_stall_l2[15] == 1'b0) ? frn_fdis_iu6_i0_rte_axu1_l2 :
stall_frn_fdis_iu6_i0_rte_axu1_l2;
assign frn_fdis_iu6_i0_valop = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_valop_l2 :
stall_frn_fdis_iu6_i0_valop_l2;
assign frn_fdis_iu6_i0_ord = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ord_l2 :
stall_frn_fdis_iu6_i0_ord_l2;
assign frn_fdis_iu6_i0_cord = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_cord_l2 :
stall_frn_fdis_iu6_i0_cord_l2;
assign frn_fdis_iu6_i0_error = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_error_l2 :
stall_frn_fdis_iu6_i0_error_l2;
assign frn_fdis_iu6_i0_btb_entry = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_btb_entry_l2 :
stall_frn_fdis_iu6_i0_btb_entry_l2;
assign frn_fdis_iu6_i0_btb_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_btb_hist_l2 :
stall_frn_fdis_iu6_i0_btb_hist_l2;
assign frn_fdis_iu6_i0_bta_val = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bta_val_l2 :
stall_frn_fdis_iu6_i0_bta_val_l2;
assign frn_fdis_iu6_i0_fusion = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_fusion_l2 :
stall_frn_fdis_iu6_i0_fusion_l2;
assign frn_fdis_iu6_i0_spec = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_spec_l2 :
stall_frn_fdis_iu6_i0_spec_l2;
assign frn_fdis_iu6_i0_type_fp = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_fp_l2 :
stall_frn_fdis_iu6_i0_type_fp_l2;
assign frn_fdis_iu6_i0_type_ap = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_ap_l2 :
stall_frn_fdis_iu6_i0_type_ap_l2;
assign frn_fdis_iu6_i0_type_spv = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_spv_l2 :
stall_frn_fdis_iu6_i0_type_spv_l2;
assign frn_fdis_iu6_i0_type_st = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_st_l2 :
stall_frn_fdis_iu6_i0_type_st_l2;
assign frn_fdis_iu6_i0_async_block = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_async_block_l2 :
stall_frn_fdis_iu6_i0_async_block_l2;
assign frn_fdis_iu6_i0_np1_flush = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_np1_flush_l2 :
stall_frn_fdis_iu6_i0_np1_flush_l2;
assign frn_fdis_iu6_i0_core_block = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_core_block_l2 :
stall_frn_fdis_iu6_i0_core_block_l2;
assign frn_fdis_iu6_i0_isram = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_isram_l2 :
stall_frn_fdis_iu6_i0_isram_l2;
assign frn_fdis_iu6_i0_isload = (fdis_frn_iu6_stall_l2[17] == 1'b0) ? frn_fdis_iu6_i0_isload_l2 :
stall_frn_fdis_iu6_i0_isload_l2;
assign frn_fdis_iu6_i0_isstore = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_isstore_l2 :
stall_frn_fdis_iu6_i0_isstore_l2;
assign frn_fdis_iu6_i0_instr = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_instr_l2 :
stall_frn_fdis_iu6_i0_instr_l2;
assign frn_fdis_iu6_i0_ifar = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ifar_l2 :
stall_frn_fdis_iu6_i0_ifar_l2;
assign frn_fdis_iu6_i0_bta = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bta_l2 :
stall_frn_fdis_iu6_i0_bta_l2;
assign frn_fdis_iu6_i0_br_pred = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_br_pred_l2 :
stall_frn_fdis_iu6_i0_br_pred_l2;
assign frn_fdis_iu6_i0_bh_update = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh_update_l2 :
stall_frn_fdis_iu6_i0_bh_update_l2;
assign frn_fdis_iu6_i0_bh0_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh0_hist_l2 :
stall_frn_fdis_iu6_i0_bh0_hist_l2;
assign frn_fdis_iu6_i0_bh1_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh1_hist_l2 :
stall_frn_fdis_iu6_i0_bh1_hist_l2;
assign frn_fdis_iu6_i0_bh2_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh2_hist_l2 :
stall_frn_fdis_iu6_i0_bh2_hist_l2;
assign frn_fdis_iu6_i0_gshare = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_gshare_l2 :
stall_frn_fdis_iu6_i0_gshare_l2;
assign frn_fdis_iu6_i0_ls_ptr = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ls_ptr_l2 :
stall_frn_fdis_iu6_i0_ls_ptr_l2;
assign frn_fdis_iu6_i0_match = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_match_l2 :
stall_frn_fdis_iu6_i0_match_l2;
assign frn_fdis_iu6_i0_ilat = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ilat_l2 :
stall_frn_fdis_iu6_i0_ilat_l2;
assign frn_fdis_iu6_i0_t1_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_v_l2 :
stall_frn_fdis_iu6_i0_t1_v_l2;
assign frn_fdis_iu6_i0_t1_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_t_l2 :
stall_frn_fdis_iu6_i0_t1_t_l2;
assign frn_fdis_iu6_i0_t1_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_a_l2 :
stall_frn_fdis_iu6_i0_t1_a_l2;
assign frn_fdis_iu6_i0_t1_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_p_l2 :
stall_frn_fdis_iu6_i0_t1_p_l2;
assign frn_fdis_iu6_i0_t2_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_v_l2 :
stall_frn_fdis_iu6_i0_t2_v_l2;
assign frn_fdis_iu6_i0_t2_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_a_l2 :
stall_frn_fdis_iu6_i0_t2_a_l2;
assign frn_fdis_iu6_i0_t2_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_p_l2 :
stall_frn_fdis_iu6_i0_t2_p_l2;
assign frn_fdis_iu6_i0_t2_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_t_l2 :
stall_frn_fdis_iu6_i0_t2_t_l2;
assign frn_fdis_iu6_i0_t3_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_v_l2 :
stall_frn_fdis_iu6_i0_t3_v_l2;
assign frn_fdis_iu6_i0_t3_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_a_l2 :
stall_frn_fdis_iu6_i0_t3_a_l2;
assign frn_fdis_iu6_i0_t3_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_p_l2 :
stall_frn_fdis_iu6_i0_t3_p_l2;
assign frn_fdis_iu6_i0_t3_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_t_l2 :
stall_frn_fdis_iu6_i0_t3_t_l2;
assign frn_fdis_iu6_i0_s1_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_v_l2 :
stall_frn_fdis_iu6_i0_s1_v_l2;
assign frn_fdis_iu6_i0_s1_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_a_l2 :
stall_frn_fdis_iu6_i0_s1_a_l2;
assign frn_fdis_iu6_i0_s1_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_p_l2 :
stall_frn_fdis_iu6_i0_s1_p_l2;
assign frn_fdis_iu6_i0_s1_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_itag_l2 :
stall_frn_fdis_iu6_i0_s1_itag_l2;
assign frn_fdis_iu6_i0_s1_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_t_l2 :
stall_frn_fdis_iu6_i0_s1_t_l2;
assign frn_fdis_iu6_i0_s2_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_v_l2 :
stall_frn_fdis_iu6_i0_s2_v_l2;
assign frn_fdis_iu6_i0_s2_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_a_l2 :
stall_frn_fdis_iu6_i0_s2_a_l2;
assign frn_fdis_iu6_i0_s2_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_p_l2 :
stall_frn_fdis_iu6_i0_s2_p_l2;
assign frn_fdis_iu6_i0_s2_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_itag_l2 :
stall_frn_fdis_iu6_i0_s2_itag_l2;
assign frn_fdis_iu6_i0_s2_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_t_l2 :
stall_frn_fdis_iu6_i0_s2_t_l2;
assign frn_fdis_iu6_i0_s3_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_v_l2 :
stall_frn_fdis_iu6_i0_s3_v_l2;
assign frn_fdis_iu6_i0_s3_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_a_l2 :
stall_frn_fdis_iu6_i0_s3_a_l2;
assign frn_fdis_iu6_i0_s3_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_p_l2 :
stall_frn_fdis_iu6_i0_s3_p_l2;
assign frn_fdis_iu6_i0_s3_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_itag_l2 :
stall_frn_fdis_iu6_i0_s3_itag_l2;
assign frn_fdis_iu6_i0_s3_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_t_l2 :
stall_frn_fdis_iu6_i0_s3_t_l2;
assign frn_fdis_iu6_i1_vld = (fdis_frn_iu6_stall_l2[4] == 1'b0) ? frn_fdis_iu6_i1_vld_l2 :
stall_frn_fdis_iu6_i1_vld_l2;
assign frn_fdis_iu6_i1_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_itag_l2 :
stall_frn_fdis_iu6_i1_itag_l2;
assign frn_fdis_iu6_i1_ucode = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ucode_l2 :
stall_frn_fdis_iu6_i1_ucode_l2;
assign frn_fdis_iu6_i1_ucode_cnt = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ucode_cnt_l2 :
stall_frn_fdis_iu6_i1_ucode_cnt_l2;
assign frn_fdis_iu6_i1_fuse_nop = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_fuse_nop_l2 :
stall_frn_fdis_iu6_i1_fuse_nop_l2;
assign frn_fdis_iu6_i1_rte_lq = (fdis_frn_iu6_stall_l2[6] == 1'b0) ? frn_fdis_iu6_i1_rte_lq_l2 :
stall_frn_fdis_iu6_i1_rte_lq_l2;
assign frn_fdis_iu6_i1_rte_sq = (fdis_frn_iu6_stall_l2[8] == 1'b0) ? frn_fdis_iu6_i1_rte_sq_l2 :
stall_frn_fdis_iu6_i1_rte_sq_l2;
assign frn_fdis_iu6_i1_rte_fx0 = (fdis_frn_iu6_stall_l2[10] == 1'b0) ? frn_fdis_iu6_i1_rte_fx0_l2 :
stall_frn_fdis_iu6_i1_rte_fx0_l2;
assign frn_fdis_iu6_i1_rte_fx1 = (fdis_frn_iu6_stall_l2[12] == 1'b0) ? frn_fdis_iu6_i1_rte_fx1_l2 :
stall_frn_fdis_iu6_i1_rte_fx1_l2;
assign frn_fdis_iu6_i1_rte_axu0 = (fdis_frn_iu6_stall_l2[14] == 1'b0) ? frn_fdis_iu6_i1_rte_axu0_l2 :
stall_frn_fdis_iu6_i1_rte_axu0_l2;
assign frn_fdis_iu6_i1_rte_axu1 = (fdis_frn_iu6_stall_l2[16] == 1'b0) ? frn_fdis_iu6_i1_rte_axu1_l2 :
stall_frn_fdis_iu6_i1_rte_axu1_l2;
assign frn_fdis_iu6_i1_valop = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_valop_l2 :
stall_frn_fdis_iu6_i1_valop_l2;
assign frn_fdis_iu6_i1_ord = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ord_l2 :
stall_frn_fdis_iu6_i1_ord_l2;
assign frn_fdis_iu6_i1_cord = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_cord_l2 :
stall_frn_fdis_iu6_i1_cord_l2;
assign frn_fdis_iu6_i1_error = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_error_l2 :
stall_frn_fdis_iu6_i1_error_l2;
assign frn_fdis_iu6_i1_btb_entry = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_btb_entry_l2 :
stall_frn_fdis_iu6_i1_btb_entry_l2;
assign frn_fdis_iu6_i1_btb_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_btb_hist_l2 :
stall_frn_fdis_iu6_i1_btb_hist_l2;
assign frn_fdis_iu6_i1_bta_val = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bta_val_l2 :
stall_frn_fdis_iu6_i1_bta_val_l2;
assign frn_fdis_iu6_i1_fusion = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_fusion_l2 :
stall_frn_fdis_iu6_i1_fusion_l2;
assign frn_fdis_iu6_i1_spec = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_spec_l2 :
stall_frn_fdis_iu6_i1_spec_l2;
assign frn_fdis_iu6_i1_type_fp = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_fp_l2 :
stall_frn_fdis_iu6_i1_type_fp_l2;
assign frn_fdis_iu6_i1_type_ap = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_ap_l2 :
stall_frn_fdis_iu6_i1_type_ap_l2;
assign frn_fdis_iu6_i1_type_spv = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_spv_l2 :
stall_frn_fdis_iu6_i1_type_spv_l2;
assign frn_fdis_iu6_i1_type_st = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_st_l2 :
stall_frn_fdis_iu6_i1_type_st_l2;
assign frn_fdis_iu6_i1_async_block = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_async_block_l2 :
stall_frn_fdis_iu6_i1_async_block_l2;
assign frn_fdis_iu6_i1_np1_flush = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_np1_flush_l2 :
stall_frn_fdis_iu6_i1_np1_flush_l2;
assign frn_fdis_iu6_i1_core_block = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_core_block_l2 :
stall_frn_fdis_iu6_i1_core_block_l2;
assign frn_fdis_iu6_i1_isram = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_isram_l2 :
stall_frn_fdis_iu6_i1_isram_l2;
assign frn_fdis_iu6_i1_isload = (fdis_frn_iu6_stall_l2[18] == 1'b0) ? frn_fdis_iu6_i1_isload_l2 :
stall_frn_fdis_iu6_i1_isload_l2;
assign frn_fdis_iu6_i1_isstore = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_isstore_l2 :
stall_frn_fdis_iu6_i1_isstore_l2;
assign frn_fdis_iu6_i1_instr = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_instr_l2 :
stall_frn_fdis_iu6_i1_instr_l2;
assign frn_fdis_iu6_i1_ifar = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ifar_l2 :
stall_frn_fdis_iu6_i1_ifar_l2;
assign frn_fdis_iu6_i1_bta = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bta_l2 :
stall_frn_fdis_iu6_i1_bta_l2;
assign frn_fdis_iu6_i1_br_pred = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_br_pred_l2 :
stall_frn_fdis_iu6_i1_br_pred_l2;
assign frn_fdis_iu6_i1_bh_update = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh_update_l2 :
stall_frn_fdis_iu6_i1_bh_update_l2;
assign frn_fdis_iu6_i1_bh0_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh0_hist_l2 :
stall_frn_fdis_iu6_i1_bh0_hist_l2;
assign frn_fdis_iu6_i1_bh1_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh1_hist_l2 :
stall_frn_fdis_iu6_i1_bh1_hist_l2;
assign frn_fdis_iu6_i1_bh2_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh2_hist_l2 :
stall_frn_fdis_iu6_i1_bh2_hist_l2;
assign frn_fdis_iu6_i1_gshare = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_gshare_l2 :
stall_frn_fdis_iu6_i1_gshare_l2;
assign frn_fdis_iu6_i1_ls_ptr = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ls_ptr_l2 :
stall_frn_fdis_iu6_i1_ls_ptr_l2;
assign frn_fdis_iu6_i1_match = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_match_l2 :
stall_frn_fdis_iu6_i1_match_l2;
assign frn_fdis_iu6_i1_ilat = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ilat_l2 :
stall_frn_fdis_iu6_i1_ilat_l2;
assign frn_fdis_iu6_i1_t1_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_v_l2 :
stall_frn_fdis_iu6_i1_t1_v_l2;
assign frn_fdis_iu6_i1_t1_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_t_l2 :
stall_frn_fdis_iu6_i1_t1_t_l2;
assign frn_fdis_iu6_i1_t1_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_a_l2 :
stall_frn_fdis_iu6_i1_t1_a_l2;
assign frn_fdis_iu6_i1_t1_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_p_l2 :
stall_frn_fdis_iu6_i1_t1_p_l2;
assign frn_fdis_iu6_i1_t2_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_v_l2 :
stall_frn_fdis_iu6_i1_t2_v_l2;
assign frn_fdis_iu6_i1_t2_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_a_l2 :
stall_frn_fdis_iu6_i1_t2_a_l2;
assign frn_fdis_iu6_i1_t2_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_p_l2 :
stall_frn_fdis_iu6_i1_t2_p_l2;
assign frn_fdis_iu6_i1_t2_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_t_l2 :
stall_frn_fdis_iu6_i1_t2_t_l2;
assign frn_fdis_iu6_i1_t3_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_v_l2 :
stall_frn_fdis_iu6_i1_t3_v_l2;
assign frn_fdis_iu6_i1_t3_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_a_l2 :
stall_frn_fdis_iu6_i1_t3_a_l2;
assign frn_fdis_iu6_i1_t3_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_p_l2 :
stall_frn_fdis_iu6_i1_t3_p_l2;
assign frn_fdis_iu6_i1_t3_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_t_l2 :
stall_frn_fdis_iu6_i1_t3_t_l2;
assign frn_fdis_iu6_i1_s1_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_v_l2 :
stall_frn_fdis_iu6_i1_s1_v_l2;
assign frn_fdis_iu6_i1_s1_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_a_l2 :
stall_frn_fdis_iu6_i1_s1_a_l2;
assign frn_fdis_iu6_i1_s1_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_p_l2 :
stall_frn_fdis_iu6_i1_s1_p_l2;
assign frn_fdis_iu6_i1_s1_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_itag_l2 :
stall_frn_fdis_iu6_i1_s1_itag_l2;
assign frn_fdis_iu6_i1_s1_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_t_l2 :
stall_frn_fdis_iu6_i1_s1_t_l2;
assign frn_fdis_iu6_i1_s1_dep_hit = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_dep_hit_l2 :
stall_frn_fdis_iu6_i1_s1_dep_hit_l2;
assign frn_fdis_iu6_i1_s2_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_v_l2 :
stall_frn_fdis_iu6_i1_s2_v_l2;
assign frn_fdis_iu6_i1_s2_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_a_l2 :
stall_frn_fdis_iu6_i1_s2_a_l2;
assign frn_fdis_iu6_i1_s2_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_p_l2 :
stall_frn_fdis_iu6_i1_s2_p_l2;
assign frn_fdis_iu6_i1_s2_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_itag_l2 :
stall_frn_fdis_iu6_i1_s2_itag_l2;
assign frn_fdis_iu6_i1_s2_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_t_l2 :
stall_frn_fdis_iu6_i1_s2_t_l2;
assign frn_fdis_iu6_i1_s2_dep_hit = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_dep_hit_l2 :
stall_frn_fdis_iu6_i1_s2_dep_hit_l2;
assign frn_fdis_iu6_i1_s3_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_v_l2 :
stall_frn_fdis_iu6_i1_s3_v_l2;
assign frn_fdis_iu6_i1_s3_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_a_l2 :
stall_frn_fdis_iu6_i1_s3_a_l2;
assign frn_fdis_iu6_i1_s3_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_p_l2 :
stall_frn_fdis_iu6_i1_s3_p_l2;
assign frn_fdis_iu6_i1_s3_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_itag_l2 :
stall_frn_fdis_iu6_i1_s3_itag_l2;
assign frn_fdis_iu6_i1_s3_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_t_l2 :
stall_frn_fdis_iu6_i1_s3_t_l2;
assign frn_fdis_iu6_i1_s3_dep_hit = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_dep_hit_l2 :
stall_frn_fdis_iu6_i1_s3_dep_hit_l2;
// output stall
assign fdis_frn_iu6_stall_d = {19{((frn_fdis_iu6_i0_vld_l2 | fdis_frn_iu6_stall_l2[0]) & fdis_frn_iu6_stall & (~cp_flush_l2))}};
// validate stall with iu6 vld for all upstream stages to eliminate any bubbles
assign fdis_frn_iu6_stall_dly = fdis_frn_iu6_stall_l2[0] & frn_fdis_iu6_i0_vld_l2;
assign stall_frn_fdis_iu6_i0_act = (~fdis_frn_iu6_stall_l2[0]);
assign stall_frn_fdis_iu6_i0_vld_d = frn_fdis_iu6_i0_vld_l2;
assign stall_frn_fdis_iu6_i0_itag_d = frn_fdis_iu6_i0_itag_l2;
assign stall_frn_fdis_iu6_i0_ucode_d = frn_fdis_iu6_i0_ucode_l2;
assign stall_frn_fdis_iu6_i0_ucode_cnt_d = frn_fdis_iu6_i0_ucode_cnt_l2;
assign stall_frn_fdis_iu6_i0_2ucode_d = frn_fdis_iu6_i0_2ucode_l2;
assign stall_frn_fdis_iu6_i0_fuse_nop_d = frn_fdis_iu6_i0_fuse_nop_l2;
assign stall_frn_fdis_iu6_i0_rte_lq_d = frn_fdis_iu6_i0_rte_lq_l2;
assign stall_frn_fdis_iu6_i0_rte_sq_d = frn_fdis_iu6_i0_rte_sq_l2;
assign stall_frn_fdis_iu6_i0_rte_fx0_d = frn_fdis_iu6_i0_rte_fx0_l2;
assign stall_frn_fdis_iu6_i0_rte_fx1_d = frn_fdis_iu6_i0_rte_fx1_l2;
assign stall_frn_fdis_iu6_i0_rte_axu0_d = frn_fdis_iu6_i0_rte_axu0_l2;
assign stall_frn_fdis_iu6_i0_rte_axu1_d = frn_fdis_iu6_i0_rte_axu1_l2;
assign stall_frn_fdis_iu6_i0_valop_d = frn_fdis_iu6_i0_valop_l2;
assign stall_frn_fdis_iu6_i0_ord_d = frn_fdis_iu6_i0_ord_l2;
assign stall_frn_fdis_iu6_i0_cord_d = frn_fdis_iu6_i0_cord_l2;
assign stall_frn_fdis_iu6_i0_error_d = frn_fdis_iu6_i0_error_l2;
assign stall_frn_fdis_iu6_i0_btb_entry_d = frn_fdis_iu6_i0_btb_entry_l2;
assign stall_frn_fdis_iu6_i0_btb_hist_d = frn_fdis_iu6_i0_btb_hist_l2;
assign stall_frn_fdis_iu6_i0_bta_val_d = frn_fdis_iu6_i0_bta_val_l2;
assign stall_frn_fdis_iu6_i0_fusion_d = frn_fdis_iu6_i0_fusion_l2;
assign stall_frn_fdis_iu6_i0_spec_d = frn_fdis_iu6_i0_spec_l2;
assign stall_frn_fdis_iu6_i0_type_fp_d = frn_fdis_iu6_i0_type_fp_l2;
assign stall_frn_fdis_iu6_i0_type_ap_d = frn_fdis_iu6_i0_type_ap_l2;
assign stall_frn_fdis_iu6_i0_type_spv_d = frn_fdis_iu6_i0_type_spv_l2;
assign stall_frn_fdis_iu6_i0_type_st_d = frn_fdis_iu6_i0_type_st_l2;
assign stall_frn_fdis_iu6_i0_async_block_d = frn_fdis_iu6_i0_async_block_l2;
assign stall_frn_fdis_iu6_i0_np1_flush_d = frn_fdis_iu6_i0_np1_flush_l2;
assign stall_frn_fdis_iu6_i0_core_block_d = frn_fdis_iu6_i0_core_block_l2;
assign stall_frn_fdis_iu6_i0_isram_d = frn_fdis_iu6_i0_isram_l2;
assign stall_frn_fdis_iu6_i0_isload_d = frn_fdis_iu6_i0_isload_l2;
assign stall_frn_fdis_iu6_i0_isstore_d = frn_fdis_iu6_i0_isstore_l2;
assign stall_frn_fdis_iu6_i0_instr_d = frn_fdis_iu6_i0_instr_l2;
assign stall_frn_fdis_iu6_i0_ifar_d = frn_fdis_iu6_i0_ifar_l2;
assign stall_frn_fdis_iu6_i0_bta_d = frn_fdis_iu6_i0_bta_l2;
assign stall_frn_fdis_iu6_i0_br_pred_d = frn_fdis_iu6_i0_br_pred_l2;
assign stall_frn_fdis_iu6_i0_bh_update_d = frn_fdis_iu6_i0_bh_update_l2;
assign stall_frn_fdis_iu6_i0_bh0_hist_d = frn_fdis_iu6_i0_bh0_hist_l2;
assign stall_frn_fdis_iu6_i0_bh1_hist_d = frn_fdis_iu6_i0_bh1_hist_l2;
assign stall_frn_fdis_iu6_i0_bh2_hist_d = frn_fdis_iu6_i0_bh2_hist_l2;
assign stall_frn_fdis_iu6_i0_gshare_d = frn_fdis_iu6_i0_gshare_l2;
assign stall_frn_fdis_iu6_i0_ls_ptr_d = frn_fdis_iu6_i0_ls_ptr_l2;
assign stall_frn_fdis_iu6_i0_match_d = frn_fdis_iu6_i0_match_l2;
assign stall_frn_fdis_iu6_i0_ilat_d = frn_fdis_iu6_i0_ilat_l2;
assign stall_frn_fdis_iu6_i0_t1_v_d = frn_fdis_iu6_i0_t1_v_l2;
assign stall_frn_fdis_iu6_i0_t1_t_d = frn_fdis_iu6_i0_t1_t_l2;
assign stall_frn_fdis_iu6_i0_t1_a_d = frn_fdis_iu6_i0_t1_a_l2;
assign stall_frn_fdis_iu6_i0_t1_p_d = frn_fdis_iu6_i0_t1_p_l2;
assign stall_frn_fdis_iu6_i0_t2_v_d = frn_fdis_iu6_i0_t2_v_l2;
assign stall_frn_fdis_iu6_i0_t2_a_d = frn_fdis_iu6_i0_t2_a_l2;
assign stall_frn_fdis_iu6_i0_t2_p_d = frn_fdis_iu6_i0_t2_p_l2;
assign stall_frn_fdis_iu6_i0_t2_t_d = frn_fdis_iu6_i0_t2_t_l2;
assign stall_frn_fdis_iu6_i0_t3_v_d = frn_fdis_iu6_i0_t3_v_l2;
assign stall_frn_fdis_iu6_i0_t3_a_d = frn_fdis_iu6_i0_t3_a_l2;
assign stall_frn_fdis_iu6_i0_t3_p_d = frn_fdis_iu6_i0_t3_p_l2;
assign stall_frn_fdis_iu6_i0_t3_t_d = frn_fdis_iu6_i0_t3_t_l2;
assign stall_frn_fdis_iu6_i0_s1_v_d = frn_fdis_iu6_i0_s1_v_l2;
assign stall_frn_fdis_iu6_i0_s1_a_d = frn_fdis_iu6_i0_s1_a_l2;
assign stall_frn_fdis_iu6_i0_s1_p_d = frn_fdis_iu6_i0_s1_p_l2;
assign stall_frn_fdis_iu6_i0_s1_itag_d = frn_fdis_iu6_i0_s1_itag_l2;
assign stall_frn_fdis_iu6_i0_s1_t_d = frn_fdis_iu6_i0_s1_t_l2;
assign stall_frn_fdis_iu6_i0_s2_v_d = frn_fdis_iu6_i0_s2_v_l2;
assign stall_frn_fdis_iu6_i0_s2_a_d = frn_fdis_iu6_i0_s2_a_l2;
assign stall_frn_fdis_iu6_i0_s2_p_d = frn_fdis_iu6_i0_s2_p_l2;
assign stall_frn_fdis_iu6_i0_s2_itag_d = frn_fdis_iu6_i0_s2_itag_l2;
assign stall_frn_fdis_iu6_i0_s2_t_d = frn_fdis_iu6_i0_s2_t_l2;
assign stall_frn_fdis_iu6_i0_s3_v_d = frn_fdis_iu6_i0_s3_v_l2;
assign stall_frn_fdis_iu6_i0_s3_a_d = frn_fdis_iu6_i0_s3_a_l2;
assign stall_frn_fdis_iu6_i0_s3_p_d = frn_fdis_iu6_i0_s3_p_l2;
assign stall_frn_fdis_iu6_i0_s3_itag_d = frn_fdis_iu6_i0_s3_itag_l2;
assign stall_frn_fdis_iu6_i0_s3_t_d = frn_fdis_iu6_i0_s3_t_l2;
assign stall_frn_fdis_iu6_i1_act = (~fdis_frn_iu6_stall_l2[0]);
assign stall_frn_fdis_iu6_i1_vld_d = frn_fdis_iu6_i1_vld_l2;
assign stall_frn_fdis_iu6_i1_itag_d = frn_fdis_iu6_i1_itag_l2;
assign stall_frn_fdis_iu6_i1_ucode_d = frn_fdis_iu6_i1_ucode_l2;
assign stall_frn_fdis_iu6_i1_ucode_cnt_d = frn_fdis_iu6_i1_ucode_cnt_l2;
assign stall_frn_fdis_iu6_i1_fuse_nop_d = frn_fdis_iu6_i1_fuse_nop_l2;
assign stall_frn_fdis_iu6_i1_rte_lq_d = frn_fdis_iu6_i1_rte_lq_l2;
assign stall_frn_fdis_iu6_i1_rte_sq_d = frn_fdis_iu6_i1_rte_sq_l2;
assign stall_frn_fdis_iu6_i1_rte_fx0_d = frn_fdis_iu6_i1_rte_fx0_l2;
assign stall_frn_fdis_iu6_i1_rte_fx1_d = frn_fdis_iu6_i1_rte_fx1_l2;
assign stall_frn_fdis_iu6_i1_rte_axu0_d = frn_fdis_iu6_i1_rte_axu0_l2;
assign stall_frn_fdis_iu6_i1_rte_axu1_d = frn_fdis_iu6_i1_rte_axu1_l2;
assign stall_frn_fdis_iu6_i1_valop_d = frn_fdis_iu6_i1_valop_l2;
assign stall_frn_fdis_iu6_i1_ord_d = frn_fdis_iu6_i1_ord_l2;
assign stall_frn_fdis_iu6_i1_cord_d = frn_fdis_iu6_i1_cord_l2;
assign stall_frn_fdis_iu6_i1_error_d = frn_fdis_iu6_i1_error_l2;
assign stall_frn_fdis_iu6_i1_btb_entry_d = frn_fdis_iu6_i1_btb_entry_l2;
assign stall_frn_fdis_iu6_i1_btb_hist_d = frn_fdis_iu6_i1_btb_hist_l2;
assign stall_frn_fdis_iu6_i1_bta_val_d = frn_fdis_iu6_i1_bta_val_l2;
assign stall_frn_fdis_iu6_i1_fusion_d = frn_fdis_iu6_i1_fusion_l2;
assign stall_frn_fdis_iu6_i1_spec_d = frn_fdis_iu6_i1_spec_l2;
assign stall_frn_fdis_iu6_i1_type_fp_d = frn_fdis_iu6_i1_type_fp_l2;
assign stall_frn_fdis_iu6_i1_type_ap_d = frn_fdis_iu6_i1_type_ap_l2;
assign stall_frn_fdis_iu6_i1_type_spv_d = frn_fdis_iu6_i1_type_spv_l2;
assign stall_frn_fdis_iu6_i1_type_st_d = frn_fdis_iu6_i1_type_st_l2;
assign stall_frn_fdis_iu6_i1_async_block_d = frn_fdis_iu6_i1_async_block_l2;
assign stall_frn_fdis_iu6_i1_np1_flush_d = frn_fdis_iu6_i1_np1_flush_l2;
assign stall_frn_fdis_iu6_i1_core_block_d = frn_fdis_iu6_i1_core_block_l2;
assign stall_frn_fdis_iu6_i1_isram_d = frn_fdis_iu6_i1_isram_l2;
assign stall_frn_fdis_iu6_i1_isload_d = frn_fdis_iu6_i1_isload_l2;
assign stall_frn_fdis_iu6_i1_isstore_d = frn_fdis_iu6_i1_isstore_l2;
assign stall_frn_fdis_iu6_i1_instr_d = frn_fdis_iu6_i1_instr_l2;
assign stall_frn_fdis_iu6_i1_ifar_d = frn_fdis_iu6_i1_ifar_l2;
assign stall_frn_fdis_iu6_i1_bta_d = frn_fdis_iu6_i1_bta_l2;
assign stall_frn_fdis_iu6_i1_br_pred_d = frn_fdis_iu6_i1_br_pred_l2;
assign stall_frn_fdis_iu6_i1_bh_update_d = frn_fdis_iu6_i1_bh_update_l2;
assign stall_frn_fdis_iu6_i1_bh0_hist_d = frn_fdis_iu6_i1_bh0_hist_l2;
assign stall_frn_fdis_iu6_i1_bh1_hist_d = frn_fdis_iu6_i1_bh1_hist_l2;
assign stall_frn_fdis_iu6_i1_bh2_hist_d = frn_fdis_iu6_i1_bh2_hist_l2;
assign stall_frn_fdis_iu6_i1_gshare_d = frn_fdis_iu6_i1_gshare_l2;
assign stall_frn_fdis_iu6_i1_ls_ptr_d = frn_fdis_iu6_i1_ls_ptr_l2;
assign stall_frn_fdis_iu6_i1_match_d = frn_fdis_iu6_i1_match_l2;
assign stall_frn_fdis_iu6_i1_ilat_d = frn_fdis_iu6_i1_ilat_l2;
assign stall_frn_fdis_iu6_i1_t1_v_d = frn_fdis_iu6_i1_t1_v_l2;
assign stall_frn_fdis_iu6_i1_t1_t_d = frn_fdis_iu6_i1_t1_t_l2;
assign stall_frn_fdis_iu6_i1_t1_a_d = frn_fdis_iu6_i1_t1_a_l2;
assign stall_frn_fdis_iu6_i1_t1_p_d = frn_fdis_iu6_i1_t1_p_l2;
assign stall_frn_fdis_iu6_i1_t2_v_d = frn_fdis_iu6_i1_t2_v_l2;
assign stall_frn_fdis_iu6_i1_t2_a_d = frn_fdis_iu6_i1_t2_a_l2;
assign stall_frn_fdis_iu6_i1_t2_p_d = frn_fdis_iu6_i1_t2_p_l2;
assign stall_frn_fdis_iu6_i1_t2_t_d = frn_fdis_iu6_i1_t2_t_l2;
assign stall_frn_fdis_iu6_i1_t3_v_d = frn_fdis_iu6_i1_t3_v_l2;
assign stall_frn_fdis_iu6_i1_t3_a_d = frn_fdis_iu6_i1_t3_a_l2;
assign stall_frn_fdis_iu6_i1_t3_p_d = frn_fdis_iu6_i1_t3_p_l2;
assign stall_frn_fdis_iu6_i1_t3_t_d = frn_fdis_iu6_i1_t3_t_l2;
assign stall_frn_fdis_iu6_i1_s1_v_d = frn_fdis_iu6_i1_s1_v_l2;
assign stall_frn_fdis_iu6_i1_s1_a_d = frn_fdis_iu6_i1_s1_a_l2;
assign stall_frn_fdis_iu6_i1_s1_p_d = frn_fdis_iu6_i1_s1_p_l2;
assign stall_frn_fdis_iu6_i1_s1_itag_d = frn_fdis_iu6_i1_s1_itag_l2;
assign stall_frn_fdis_iu6_i1_s1_t_d = frn_fdis_iu6_i1_s1_t_l2;
assign stall_frn_fdis_iu6_i1_s1_dep_hit_d = frn_fdis_iu6_i1_s1_dep_hit_l2;
assign stall_frn_fdis_iu6_i1_s2_v_d = frn_fdis_iu6_i1_s2_v_l2;
assign stall_frn_fdis_iu6_i1_s2_a_d = frn_fdis_iu6_i1_s2_a_l2;
assign stall_frn_fdis_iu6_i1_s2_p_d = frn_fdis_iu6_i1_s2_p_l2;
assign stall_frn_fdis_iu6_i1_s2_itag_d = frn_fdis_iu6_i1_s2_itag_l2;
assign stall_frn_fdis_iu6_i1_s2_t_d = frn_fdis_iu6_i1_s2_t_l2;
assign stall_frn_fdis_iu6_i1_s2_dep_hit_d = frn_fdis_iu6_i1_s2_dep_hit_l2;
assign stall_frn_fdis_iu6_i1_s3_v_d = frn_fdis_iu6_i1_s3_v_l2;
assign stall_frn_fdis_iu6_i1_s3_a_d = frn_fdis_iu6_i1_s3_a_l2;
assign stall_frn_fdis_iu6_i1_s3_p_d = frn_fdis_iu6_i1_s3_p_l2;
assign stall_frn_fdis_iu6_i1_s3_itag_d = frn_fdis_iu6_i1_s3_itag_l2;
assign stall_frn_fdis_iu6_i1_s3_t_d = frn_fdis_iu6_i1_s3_t_l2;
assign stall_frn_fdis_iu6_i1_s3_dep_hit_d = frn_fdis_iu6_i1_s3_dep_hit_l2;
assign inc_0 = (fdec_frn_iu5_i0_vld & send_instructions);
assign inc_1 = (fdec_frn_iu5_i1_vld & send_instructions);
iuq_cpl_ctrl_inc #(.SIZE(`ITAG_SIZE_ENC), .WRAP(`CPL_Q_DEPTH - 1)) iu6_i0_itag_inc(
.inc({inc_0, inc_1}),
.i(next_itag_0_l2),
.o(i0_itag_next)
);
iuq_cpl_ctrl_inc #(.SIZE(`ITAG_SIZE_ENC), .WRAP(`CPL_Q_DEPTH - 1)) iu6_i1_itag_inc(
.inc({inc_0, inc_1}),
.i(next_itag_1_l2),
.o(i1_itag_next)
);
assign next_itag_0_d = ((cp_flush_l2) == 1'b1) ? cp_rn_i0_itag :
i0_itag_next;
assign next_itag_1_d = ((cp_flush_l2) == 1'b1) ? cp_rn_i1_itag :
i1_itag_next;
assign cp_flush_d = cp_flush;
assign cp_flush_into_uc_d = cp_flush_into_uc;
assign br_iu_hold_d = ((br_iu_redirect | br_iu_hold_l2) |
(send_instructions & fdec_frn_iu5_i0_np1_flush) |
(send_instructions & fdec_frn_iu5_i1_vld & fdec_frn_iu5_i1_np1_flush)) & (~cp_flush_l2);
assign gpr_send_cnt = {(fdec_frn_iu5_i0_t1_v & ~fdec_frn_iu5_i0_t1_t[0] & ~fdec_frn_iu5_i0_t1_t[1] & ~fdec_frn_iu5_i0_t1_t[2]),
(fdec_frn_iu5_i1_t1_v & ~fdec_frn_iu5_i1_t1_t[0] & ~fdec_frn_iu5_i1_t1_t[1] & ~fdec_frn_iu5_i1_t1_t[2])};
assign cr_send_cnt = {((fdec_frn_iu5_i0_t3_v & ~fdec_frn_iu5_i0_t3_t[0] & ~fdec_frn_iu5_i0_t3_t[1] & fdec_frn_iu5_i0_t3_t[2]) |
(fdec_frn_iu5_i0_t1_v & ~fdec_frn_iu5_i0_t1_t[0] & ~fdec_frn_iu5_i0_t1_t[1] & fdec_frn_iu5_i0_t1_t[2])),
((fdec_frn_iu5_i1_t3_v & ~fdec_frn_iu5_i1_t3_t[0] & ~fdec_frn_iu5_i1_t3_t[1] & fdec_frn_iu5_i1_t3_t[2]) |
(fdec_frn_iu5_i1_t1_v & ~fdec_frn_iu5_i1_t1_t[0] & ~fdec_frn_iu5_i1_t1_t[1] & fdec_frn_iu5_i1_t1_t[2]))};
assign cr_send_t1_cnt = {(fdec_frn_iu5_i0_t1_v & ~fdec_frn_iu5_i0_t1_t[0] & ~fdec_frn_iu5_i0_t1_t[1] & fdec_frn_iu5_i0_t1_t[2]),
(fdec_frn_iu5_i1_t1_v & ~fdec_frn_iu5_i1_t1_t[0] & ~fdec_frn_iu5_i1_t1_t[1] & fdec_frn_iu5_i1_t1_t[2])};
assign cr_send_t3_cnt = {(fdec_frn_iu5_i0_t3_v & ~fdec_frn_iu5_i0_t3_t[0] & ~fdec_frn_iu5_i0_t3_t[1] & fdec_frn_iu5_i0_t3_t[2]),
(fdec_frn_iu5_i1_t3_v & ~fdec_frn_iu5_i1_t3_t[0] & ~fdec_frn_iu5_i1_t3_t[1] & fdec_frn_iu5_i1_t3_t[2])};
assign lr_send_cnt = {(fdec_frn_iu5_i0_t3_v & ~fdec_frn_iu5_i0_t3_t[0] & fdec_frn_iu5_i0_t3_t[1] & ~fdec_frn_iu5_i0_t3_t[2]),
(fdec_frn_iu5_i1_t3_v & ~fdec_frn_iu5_i1_t3_t[0] & fdec_frn_iu5_i1_t3_t[1] & ~fdec_frn_iu5_i1_t3_t[2])};
assign ctr_send_cnt = {(fdec_frn_iu5_i0_t2_v & ~fdec_frn_iu5_i0_t2_t[0] & fdec_frn_iu5_i0_t2_t[1] & fdec_frn_iu5_i0_t2_t[2]),
(fdec_frn_iu5_i1_t2_v & ~fdec_frn_iu5_i1_t2_t[0] & fdec_frn_iu5_i1_t2_t[1] & fdec_frn_iu5_i1_t2_t[2])};
assign xer_send_cnt = {(fdec_frn_iu5_i0_t2_v & fdec_frn_iu5_i0_t2_t[0] & ~fdec_frn_iu5_i0_t2_t[1] & ~fdec_frn_iu5_i0_t2_t[2]),
(fdec_frn_iu5_i1_t2_v & fdec_frn_iu5_i1_t2_t[0] & ~fdec_frn_iu5_i1_t2_t[1] & ~fdec_frn_iu5_i1_t2_t[2])};
assign ucode_send_cnt = {(fdec_frn_iu5_i0_ucode[1]), (fdec_frn_iu5_i1_ucode[1])};
assign cp_credit_cnt_mux = ({`CPL_Q_DEPTH_ENC{high_pri_mask_l2}} & cp_high_credit_cnt_l2) |
({`CPL_Q_DEPTH_ENC{~high_pri_mask_l2}} & cp_med_credit_cnt_l2);
assign cpl_credit_ok = ((~fdec_frn_iu5_i0_vld & ~fdec_frn_iu5_i1_vld) |
((fdec_frn_iu5_i0_vld ^ fdec_frn_iu5_i1_vld) & |cp_credit_cnt_mux) |
(|cp_credit_cnt_mux[0:`CPL_Q_DEPTH_ENC - 1]));
assign gpr_send_ok = (~gpr_send_cnt[0] & ~gpr_send_cnt[1]) |
((gpr_send_cnt[0] ^ gpr_send_cnt[1]) & next_gpr_0_v) |
(next_gpr_0_v & next_gpr_1_v);
assign cr_send_ok = (~cr_send_cnt[0] & ~cr_send_cnt[1]) |
((cr_send_cnt[0] ^ cr_send_cnt[1]) & next_cr_0_v) |
(next_cr_0_v & next_cr_1_v);
assign lr_send_ok = (~lr_send_cnt[0] & ~lr_send_cnt[1]) |
((lr_send_cnt[0] ^ lr_send_cnt[1]) & next_lr_0_v) |
(next_lr_0_v & next_lr_1_v);
assign ctr_send_ok = (~ctr_send_cnt[0] & ~ctr_send_cnt[1]) |
((ctr_send_cnt[0] ^ ctr_send_cnt[1]) & next_ctr_0_v) |
(next_ctr_0_v & next_ctr_1_v);
assign xer_send_ok = (~xer_send_cnt[0] & ~xer_send_cnt[1]) |
((xer_send_cnt[0] ^ xer_send_cnt[1]) & next_xer_0_v) |
(next_xer_0_v & next_xer_1_v);
assign cp_empty_ok = (((fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_core_block) | (fdec_frn_iu5_i1_vld & fdec_frn_iu5_i1_core_block)) & cp_rn_empty_l2) |
(~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_core_block) & ~(fdec_frn_iu5_i1_vld & fdec_frn_iu5_i1_core_block));
assign send_instructions = (cpl_credit_ok & gpr_send_ok & cr_send_ok & lr_send_ok & ctr_send_ok & xer_send_ok & cp_empty_ok &
au_iu_iu5_axu0_send_ok & au_iu_iu5_axu1_send_ok & fdec_frn_iu5_i0_vld) & (~(hold_instructions_l2));
assign hold_instructions_d = (fdis_frn_iu6_stall_d[0] & frn_fdis_iu6_i0_vld_d) | br_iu_hold_d | cp_flush_d;
// To AXU rename
assign iu_au_iu5_send_ok = (cpl_credit_ok & gpr_send_ok & cr_send_ok & lr_send_ok & ctr_send_ok & xer_send_ok & cp_empty_ok) & (~fdis_frn_iu6_stall_dly);
assign iu_au_iu5_next_itag_i0 = next_itag_0_l2;
assign iu_au_iu5_next_itag_i1 = next_itag_1_l2;
assign high_cnt_plus2_temp = cp_high_credit_cnt_l2 + value_2[31-`CPL_Q_DEPTH_ENC:31];
assign high_cnt_plus2 = (high_cnt_plus2_temp > spr_cpcr3_cp_cnt) ? spr_cpcr3_cp_cnt :
high_cnt_plus2_temp;
assign high_cnt_plus1_temp = cp_high_credit_cnt_l2 + value_1[31-`CPL_Q_DEPTH_ENC:31];
assign high_cnt_plus1 = (high_cnt_plus1_temp > spr_cpcr3_cp_cnt) ? spr_cpcr3_cp_cnt :
high_cnt_plus1_temp;
assign high_cnt_minus1_temp = cp_high_credit_cnt_l2 - value_1[31-`CPL_Q_DEPTH_ENC:31];
assign high_cnt_minus1 = high_cnt_minus1_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} :
high_cnt_minus1_temp;
assign high_cnt_minus2_temp = cp_high_credit_cnt_l2 - value_2[31-`CPL_Q_DEPTH_ENC:31];
assign high_cnt_minus2 = high_cnt_minus2_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} :
high_cnt_minus2_temp;
assign med_cnt_plus2_temp = cp_med_credit_cnt_l2 + value_2[31-`CPL_Q_DEPTH_ENC:31];
assign med_cnt_plus2 = (med_cnt_plus2_temp > spr_cpcr5_cp_cnt) ? spr_cpcr5_cp_cnt :
med_cnt_plus2_temp;
assign med_cnt_plus1_temp = cp_med_credit_cnt_l2 + value_1[31-`CPL_Q_DEPTH_ENC:31];
assign med_cnt_plus1 = (med_cnt_plus1_temp > spr_cpcr5_cp_cnt) ? spr_cpcr5_cp_cnt :
med_cnt_plus1_temp;
assign med_cnt_minus1_temp = cp_med_credit_cnt_l2 - value_1[31-`CPL_Q_DEPTH_ENC:31];
assign med_cnt_minus1 = med_cnt_minus1_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} :
med_cnt_minus1_temp;
assign med_cnt_minus2_temp = cp_med_credit_cnt_l2 - value_2[31-`CPL_Q_DEPTH_ENC:31];
assign med_cnt_minus2 = med_cnt_minus2_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} :
med_cnt_minus2_temp;
always @(*)
begin: cp_credit_proc
cp_high_credit_cnt_d = cp_high_credit_cnt_l2;
cp_med_credit_cnt_d = cp_med_credit_cnt_l2;
if (spr_cpcr_we == 1'b1 | cp_flush_l2 == 1'b1)
if (spr_single_issue == 1'b1)
begin
cp_high_credit_cnt_d = 7'b0000010;
cp_med_credit_cnt_d = 7'b0000010;
end
else if(spr_cpcr_we == 1'b1)
begin
cp_high_credit_cnt_d = spr_cpcr3_cp_cnt - value_1[31-`CPL_Q_DEPTH_ENC:31];
cp_med_credit_cnt_d = spr_cpcr5_cp_cnt - value_1[31-`CPL_Q_DEPTH_ENC:31];
end
else
begin
cp_high_credit_cnt_d = spr_cpcr3_cp_cnt;
cp_med_credit_cnt_d = spr_cpcr5_cp_cnt;
end
else
if (send_instructions == 1'b0)
begin
if (cp_rn_i0_v == 1'b1 ^ cp_rn_i1_v == 1'b1)
begin
cp_high_credit_cnt_d = high_cnt_plus1;
cp_med_credit_cnt_d = med_cnt_plus1;
end
else if (cp_rn_i0_v == 1'b1 & cp_rn_i1_v == 1'b1)
begin
cp_high_credit_cnt_d = high_cnt_plus2;
cp_med_credit_cnt_d = med_cnt_plus2;
end
end
else if (send_instructions == 1'b1)
begin
if (fdec_frn_iu5_i1_vld == 1'b1 & (cp_rn_i0_v == 1'b1 ^ cp_rn_i1_v == 1'b1))
begin
cp_high_credit_cnt_d = high_cnt_minus1;
cp_med_credit_cnt_d = med_cnt_minus1;
end
else if (fdec_frn_iu5_i1_vld == 1'b0 & (cp_rn_i0_v == 1'b1 & cp_rn_i1_v == 1'b1))
begin
cp_high_credit_cnt_d = high_cnt_plus1;
cp_med_credit_cnt_d = med_cnt_plus1;
end
else if (cp_rn_i0_v == 1'b0 & cp_rn_i1_v == 1'b0)
begin
if (fdec_frn_iu5_i1_vld == 1'b1)
begin
cp_high_credit_cnt_d = high_cnt_minus2;
cp_med_credit_cnt_d = med_cnt_minus2;
end
else
begin
cp_high_credit_cnt_d = high_cnt_minus1;
cp_med_credit_cnt_d = med_cnt_minus1;
end
end
end
end
always @(*)
begin: ucode_cnt_proc
ucode_cnt_d = ucode_cnt_l2;
if (cp_flush_l2 == 1'b1 & cp_flush_into_uc_l2 == 1'b0)
ucode_cnt_d = ucode_cnt_save_l2 - value_1[32-`UCODE_ENTRIES_ENC:31];
else if (cp_flush_l2 == 1'b1 & cp_flush_into_uc_l2 == 1'b1)
ucode_cnt_d = ucode_cnt_save_l2;
else
if (send_instructions == 1'b1 & (ucode_send_cnt[0] == 1'b1 | ucode_send_cnt[1] == 1'b1))
ucode_cnt_d = ucode_cnt_l2 + value_1[32-`UCODE_ENTRIES_ENC:31];
end
always @(*)
begin: ucode_cnt_save_proc
ucode_cnt_save_d = ucode_cnt_save_l2;
if (cp_rn_uc_credit_free == 1'b1)
ucode_cnt_save_d = ucode_cnt_save_l2 + value_1[32-`UCODE_ENTRIES_ENC:31];
end
assign ucode_cnt_i0 = (ucode_send_cnt[0] == 1'b1) ? ucode_cnt_l2 + value_1[32-`UCODE_ENTRIES_ENC:31] :
ucode_cnt_l2;
assign ucode_cnt_i1 = (ucode_send_cnt[1] == 1'b1) ? ucode_cnt_l2 + value_1[32-`UCODE_ENTRIES_ENC:31] :
ucode_cnt_l2;
//-----------------------------------------------------------------------
//-- Outputs
//-----------------------------------------------------------------------
assign frn_fdec_iu5_stall = (~(cpl_credit_ok & gpr_send_ok &