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344 KiB
Verilog

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
`timescale 1 ns / 1 ns
// VHDL 1076 Macro Expander C version 07/11/00
// job was run on Thu Apr 14 13:14:38 2011
//********************************************************************
//*
//* TITLE:
//*
//* NAME: iuq_idec.v
//*
//*********************************************************************
module iuq_idec(
vdd,
gnd,
clk,
rst,
pc_iu_sg_2,
pc_iu_func_sl_thold_2,
clkoff_b,
act_dis,
tc_ac_ccflush_dc,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
scan_in,
scan_out,
xu_iu_epcr_dgtmi,
xu_iu_msrp_uclep,
xu_iu_msr_pr,
xu_iu_msr_gs,
xu_iu_msr_ucle,
xu_iu_ccr2_ucode_dis,
mm_iu_tlbwe_binv,
spr_dec_mask,
spr_dec_match,
cp_iu_iu4_flush,
uc_ib_iu3_flush_all,
br_iu_redirect,
ib_id_iu4_valid,
ib_id_iu4_ifar,
ib_id_iu4_bta,
ib_id_iu4_instr,
ib_id_iu4_ucode,
ib_id_iu4_ucode_ext,
ib_id_iu4_isram,
ib_id_iu4_fuse_val,
ib_id_iu4_fuse_data,
au_iu_iu4_i_dec_b,
au_iu_iu4_ucode,
au_iu_iu4_t1_v,
au_iu_iu4_t1_t,
au_iu_iu4_t1_a,
au_iu_iu4_t2_v,
au_iu_iu4_t2_a,
au_iu_iu4_t2_t,
au_iu_iu4_t3_v,
au_iu_iu4_t3_a,
au_iu_iu4_t3_t,
au_iu_iu4_s1_v,
au_iu_iu4_s1_a,
au_iu_iu4_s1_t,
au_iu_iu4_s2_v,
au_iu_iu4_s2_a,
au_iu_iu4_s2_t,
au_iu_iu4_s3_v,
au_iu_iu4_s3_a,
au_iu_iu4_s3_t,
au_iu_iu4_ilat,
au_iu_iu4_ord,
au_iu_iu4_cord,
au_iu_iu4_spec,
au_iu_iu4_type_fp,
au_iu_iu4_type_ap,
au_iu_iu4_type_spv,
au_iu_iu4_type_st,
au_iu_iu4_async_block,
au_iu_iu4_isload,
au_iu_iu4_isstore,
au_iu_iu4_rte_lq,
au_iu_iu4_rte_sq,
au_iu_iu4_rte_axu0,
au_iu_iu4_rte_axu1,
au_iu_iu4_no_ram,
fdec_frn_iu5_ix_vld,
fdec_frn_iu5_ix_ucode,
fdec_frn_iu5_ix_2ucode,
fdec_frn_iu5_ix_fuse_nop,
fdec_frn_iu5_ix_rte_lq,
fdec_frn_iu5_ix_rte_sq,
fdec_frn_iu5_ix_rte_fx0,
fdec_frn_iu5_ix_rte_fx1,
fdec_frn_iu5_ix_rte_axu0,
fdec_frn_iu5_ix_rte_axu1,
fdec_frn_iu5_ix_valop,
fdec_frn_iu5_ix_ord,
fdec_frn_iu5_ix_cord,
fdec_frn_iu5_ix_error,
fdec_frn_iu5_ix_fusion,
fdec_frn_iu5_ix_spec,
fdec_frn_iu5_ix_type_fp,
fdec_frn_iu5_ix_type_ap,
fdec_frn_iu5_ix_type_spv,
fdec_frn_iu5_ix_type_st,
fdec_frn_iu5_ix_async_block,
fdec_frn_iu5_ix_np1_flush,
fdec_frn_iu5_ix_core_block,
fdec_frn_iu5_ix_isram,
fdec_frn_iu5_ix_isload,
fdec_frn_iu5_ix_isstore,
fdec_frn_iu5_ix_instr,
fdec_frn_iu5_ix_ifar,
fdec_frn_iu5_ix_bta,
fdec_frn_iu5_ix_ilat,
fdec_frn_iu5_ix_t1_v,
fdec_frn_iu5_ix_t1_t,
fdec_frn_iu5_ix_t1_a,
fdec_frn_iu5_ix_t2_v,
fdec_frn_iu5_ix_t2_a,
fdec_frn_iu5_ix_t2_t,
fdec_frn_iu5_ix_t3_v,
fdec_frn_iu5_ix_t3_a,
fdec_frn_iu5_ix_t3_t,
fdec_frn_iu5_ix_s1_v,
fdec_frn_iu5_ix_s1_a,
fdec_frn_iu5_ix_s1_t,
fdec_frn_iu5_ix_s2_v,
fdec_frn_iu5_ix_s2_a,
fdec_frn_iu5_ix_s2_t,
fdec_frn_iu5_ix_s3_v,
fdec_frn_iu5_ix_s3_a,
fdec_frn_iu5_ix_s3_t,
fdec_frn_iu5_ix_br_pred,
fdec_frn_iu5_ix_bh_update,
fdec_frn_iu5_ix_bh0_hist,
fdec_frn_iu5_ix_bh1_hist,
fdec_frn_iu5_ix_bh2_hist,
fdec_frn_iu5_ix_gshare,
fdec_frn_iu5_ix_ls_ptr,
fdec_frn_iu5_ix_match,
fdec_frn_iu5_ix_btb_entry,
fdec_frn_iu5_ix_btb_hist,
fdec_frn_iu5_ix_bta_val,
frn_fdec_iu5_stall
);
// parameter `GPR_WIDTH = 64;
// parameter `EFF_IFAR_ARCH = 62;
// parameter `EFF_IFAR_WIDTH = 20;
// parameter `GPR_POOL_ENC = 6;
`include "tri_a2o.vh"
inout vdd;
inout gnd;
input clk;
input rst;
input pc_iu_sg_2;
input pc_iu_func_sl_thold_2;
input clkoff_b;
input act_dis;
input tc_ac_ccflush_dc;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input scan_in;
output scan_out;
input xu_iu_epcr_dgtmi;
input xu_iu_msrp_uclep;
input xu_iu_msr_pr;
input xu_iu_msr_gs;
input xu_iu_msr_ucle;
input xu_iu_ccr2_ucode_dis;
input mm_iu_tlbwe_binv;
input [0:31] spr_dec_mask;
input [0:31] spr_dec_match;
input cp_iu_iu4_flush;
input uc_ib_iu3_flush_all;
input br_iu_redirect;
input ib_id_iu4_valid;
input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_ifar;
input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_bta;
input [0:69] ib_id_iu4_instr;
input [0:2] ib_id_iu4_ucode;
input [0:3] ib_id_iu4_ucode_ext;
input ib_id_iu4_isram;
input ib_id_iu4_fuse_val;
input [0:31] ib_id_iu4_fuse_data;
input au_iu_iu4_i_dec_b;
input [0:2] au_iu_iu4_ucode;
input au_iu_iu4_t1_v;
input [0:2] au_iu_iu4_t1_t;
input [0:`GPR_POOL_ENC-1] au_iu_iu4_t1_a;
input au_iu_iu4_t2_v;
input [0:`GPR_POOL_ENC-1] au_iu_iu4_t2_a;
input [0:2] au_iu_iu4_t2_t;
input au_iu_iu4_t3_v;
input [0:`GPR_POOL_ENC-1] au_iu_iu4_t3_a;
input [0:2] au_iu_iu4_t3_t;
input au_iu_iu4_s1_v;
input [0:`GPR_POOL_ENC-1] au_iu_iu4_s1_a;
input [0:2] au_iu_iu4_s1_t;
input au_iu_iu4_s2_v;
input [0:`GPR_POOL_ENC-1] au_iu_iu4_s2_a;
input [0:2] au_iu_iu4_s2_t;
input au_iu_iu4_s3_v;
input [0:`GPR_POOL_ENC-1] au_iu_iu4_s3_a;
input [0:2] au_iu_iu4_s3_t;
input [0:2] au_iu_iu4_ilat;
input au_iu_iu4_ord;
input au_iu_iu4_cord;
input au_iu_iu4_spec;
input au_iu_iu4_type_fp;
input au_iu_iu4_type_ap;
input au_iu_iu4_type_spv;
input au_iu_iu4_type_st;
input au_iu_iu4_async_block;
input au_iu_iu4_isload;
input au_iu_iu4_isstore;
input au_iu_iu4_rte_lq;
input au_iu_iu4_rte_sq;
input au_iu_iu4_rte_axu0;
input au_iu_iu4_rte_axu1;
input au_iu_iu4_no_ram;
output fdec_frn_iu5_ix_vld;
output [0:2] fdec_frn_iu5_ix_ucode;
output fdec_frn_iu5_ix_2ucode;
output fdec_frn_iu5_ix_fuse_nop;
output fdec_frn_iu5_ix_rte_lq;
output fdec_frn_iu5_ix_rte_sq;
output fdec_frn_iu5_ix_rte_fx0;
output fdec_frn_iu5_ix_rte_fx1;
output fdec_frn_iu5_ix_rte_axu0;
output fdec_frn_iu5_ix_rte_axu1;
output fdec_frn_iu5_ix_valop;
output fdec_frn_iu5_ix_ord;
output fdec_frn_iu5_ix_cord;
output [0:2] fdec_frn_iu5_ix_error;
output [0:19] fdec_frn_iu5_ix_fusion;
output fdec_frn_iu5_ix_spec;
output fdec_frn_iu5_ix_type_fp;
output fdec_frn_iu5_ix_type_ap;
output fdec_frn_iu5_ix_type_spv;
output fdec_frn_iu5_ix_type_st;
output fdec_frn_iu5_ix_async_block;
output fdec_frn_iu5_ix_np1_flush;
output fdec_frn_iu5_ix_core_block;
output fdec_frn_iu5_ix_isram;
output fdec_frn_iu5_ix_isload;
output fdec_frn_iu5_ix_isstore;
output [0:31] fdec_frn_iu5_ix_instr;
output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_ix_ifar;
output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_ix_bta;
output [0:3] fdec_frn_iu5_ix_ilat;
output fdec_frn_iu5_ix_t1_v;
output [0:2] fdec_frn_iu5_ix_t1_t;
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_t1_a;
output fdec_frn_iu5_ix_t2_v;
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_t2_a;
output [0:2] fdec_frn_iu5_ix_t2_t;
output fdec_frn_iu5_ix_t3_v;
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_t3_a;
output [0:2] fdec_frn_iu5_ix_t3_t;
output fdec_frn_iu5_ix_s1_v;
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_s1_a;
output [0:2] fdec_frn_iu5_ix_s1_t;
output fdec_frn_iu5_ix_s2_v;
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_s2_a;
output [0:2] fdec_frn_iu5_ix_s2_t;
output fdec_frn_iu5_ix_s3_v;
output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_s3_a;
output [0:2] fdec_frn_iu5_ix_s3_t;
output fdec_frn_iu5_ix_br_pred;
output fdec_frn_iu5_ix_bh_update;
output [0:1] fdec_frn_iu5_ix_bh0_hist;
output [0:1] fdec_frn_iu5_ix_bh1_hist;
output [0:1] fdec_frn_iu5_ix_bh2_hist;
output [0:17] fdec_frn_iu5_ix_gshare;
output [0:2] fdec_frn_iu5_ix_ls_ptr;
output fdec_frn_iu5_ix_match;
output fdec_frn_iu5_ix_btb_entry;
output [0:1] fdec_frn_iu5_ix_btb_hist;
output fdec_frn_iu5_ix_bta_val;
input frn_fdec_iu5_stall;
//@@ Signal Declarations
wire [1:107] br_dep_pt;
wire [1:223] instruction_decoder_pt;
wire updatescr;
wire [0:1] updatescr_sel;
wire updatesctr;
wire updateslr;
wire updatesxer;
wire usescr;
wire usescr2;
wire [0:1] usescr_sel;
wire usesctr;
wire useslr;
wire usestar;
wire usesxer;
wire async_block;
wire core_block;
wire dec_val;
wire isload;
wire issue_fx0;
wire issue_fx1;
wire issue_lq;
wire issue_sq;
wire [0:3] latency;
wire no_pre;
wire no_ram;
wire np1_flush;
wire ordered;
wire s1_sel;
wire s1_vld;
wire s2_sel;
wire s2_vld;
wire s3_vld;
wire spec;
wire ta_sel;
wire ta_vld;
wire zero_r0;
// Scan chain connenctions
parameter iu5_vld_offset = 0;
parameter iu5_ucode_offset = iu5_vld_offset + 1;
parameter iu5_2ucode_offset = iu5_ucode_offset + 3;
parameter iu5_fuse_nop_offset = iu5_2ucode_offset + 1;
parameter iu5_error_offset = iu5_fuse_nop_offset + 1;
parameter iu5_btb_entry_offset = iu5_error_offset + 3;
parameter iu5_btb_hist_offset = iu5_btb_entry_offset + 1;
parameter iu5_bta_val_offset = iu5_btb_hist_offset + 2;
parameter iu5_fusion_offset = iu5_bta_val_offset + 1;
parameter iu5_rte_lq_offset = iu5_fusion_offset + 20;
parameter iu5_rte_sq_offset = iu5_rte_lq_offset + 1;
parameter iu5_rte_fx0_offset = iu5_rte_sq_offset + 1;
parameter iu5_rte_fx1_offset = iu5_rte_fx0_offset + 1;
parameter iu5_rte_axu0_offset = iu5_rte_fx1_offset + 1;
parameter iu5_rte_axu1_offset = iu5_rte_axu0_offset + 1;
parameter iu5_valop_offset = iu5_rte_axu1_offset + 1;
parameter iu5_ord_offset = iu5_valop_offset + 1;
parameter iu5_cord_offset = iu5_ord_offset + 1;
parameter iu5_spec_offset = iu5_cord_offset + 1;
parameter iu5_isram_offset = iu5_spec_offset + 1;
parameter iu5_type_fp_offset = iu5_isram_offset + 1;
parameter iu5_type_ap_offset = iu5_type_fp_offset + 1;
parameter iu5_type_spv_offset = iu5_type_ap_offset + 1;
parameter iu5_type_st_offset = iu5_type_spv_offset + 1;
parameter iu5_async_block_offset = iu5_type_st_offset + 1;
parameter iu5_np1_flush_offset = iu5_async_block_offset + 1;
parameter iu5_core_block_offset = iu5_np1_flush_offset + 1;
parameter iu5_isload_offset = iu5_core_block_offset + 1;
parameter iu5_isstore_offset = iu5_isload_offset + 1;
parameter iu5_instr_offset = iu5_isstore_offset + 1;
parameter iu5_ifar_offset = iu5_instr_offset + 32;
parameter iu5_bta_offset = iu5_ifar_offset + `EFF_IFAR_WIDTH;
parameter iu5_ilat_offset = iu5_bta_offset + `EFF_IFAR_WIDTH;
parameter iu5_t1_v_offset = iu5_ilat_offset + 4;
parameter iu5_t1_t_offset = iu5_t1_v_offset + 1;
parameter iu5_t1_a_offset = iu5_t1_t_offset + 3;
parameter iu5_t2_v_offset = iu5_t1_a_offset + `GPR_POOL_ENC;
parameter iu5_t2_a_offset = iu5_t2_v_offset + 1;
parameter iu5_t2_t_offset = iu5_t2_a_offset + `GPR_POOL_ENC;
parameter iu5_t3_v_offset = iu5_t2_t_offset + 3;
parameter iu5_t3_a_offset = iu5_t3_v_offset + 1;
parameter iu5_t3_t_offset = iu5_t3_a_offset + `GPR_POOL_ENC;
parameter iu5_s1_v_offset = iu5_t3_t_offset + 3;
parameter iu5_s1_a_offset = iu5_s1_v_offset + 1;
parameter iu5_s1_t_offset = iu5_s1_a_offset + `GPR_POOL_ENC;
parameter iu5_s2_v_offset = iu5_s1_t_offset + 3;
parameter iu5_s2_a_offset = iu5_s2_v_offset + 1;
parameter iu5_s2_t_offset = iu5_s2_a_offset + `GPR_POOL_ENC;
parameter iu5_s3_v_offset = iu5_s2_t_offset + 3;
parameter iu5_s3_a_offset = iu5_s3_v_offset + 1;
parameter iu5_s3_t_offset = iu5_s3_a_offset + `GPR_POOL_ENC;
parameter iu5_br_pred_offset = iu5_s3_t_offset + 3;
parameter iu5_bh_update_offset = iu5_br_pred_offset + 1;
parameter iu5_bh0_hist_offset = iu5_bh_update_offset + 1;
parameter iu5_bh1_hist_offset = iu5_bh0_hist_offset + 2;
parameter iu5_bh2_hist_offset = iu5_bh1_hist_offset + 2;
parameter iu5_gshare_offset = iu5_bh2_hist_offset + 2;
parameter iu5_ls_ptr_offset = iu5_gshare_offset + 18;
parameter iu5_match_offset = iu5_ls_ptr_offset + 3;
parameter spr_epcr_dgtmi_offset = iu5_match_offset + 1;
parameter spr_msrp_uclep_offset = spr_epcr_dgtmi_offset + 1;
parameter spr_msr_pr_offset = spr_msrp_uclep_offset + 1;
parameter spr_msr_gs_offset = spr_msr_pr_offset + 1;
parameter spr_msr_ucle_offset = spr_msr_gs_offset + 1;
parameter spr_ccr2_ucode_dis_offset = spr_msr_ucle_offset + 1;
parameter cp_flush_offset = spr_ccr2_ucode_dis_offset + 1;
parameter scan_right = cp_flush_offset + 1 - 1;
// signals for hooking up scanchains
wire [0:scan_right] siv;
wire [0:scan_right] sov;
// hard ties
wire tiup;
wire core64;
wire cp_flush_d;
wire cp_flush_q;
// instruction fields
wire iu4_instr_vld;
wire [62-`EFF_IFAR_WIDTH:61] iu4_ifar;
wire [62-`EFF_IFAR_WIDTH:61] iu4_bta;
wire [0:31] iu4_instr;
wire [0:3] iu4_instr_ucode_ext;
wire iu4_instr_br_pred;
wire iu4_instr_bh_update;
wire [0:1] iu4_instr_bh0_hist;
wire [0:1] iu4_instr_bh1_hist;
wire [0:1] iu4_instr_bh2_hist;
wire [0:17] iu4_instr_gshare;
wire [0:2] iu4_instr_ls_ptr;
wire iu4_instr_match;
wire [0:2] iu4_instr_error;
wire iu4_instr_btb_entry;
wire [0:1] iu4_instr_btb_hist;
wire iu4_instr_bta_val;
wire [0:2] iu4_instr_ucode;
wire iu4_instr_2ucode;
wire iu4_instr_isram;
wire iu4_fuse_val;
wire [0:31] iu4_fuse_cmp;
wire iu4_fuse_nop;
wire iu4_is_mtcpcr;
// Latch definitions
reg iu5_vld_d;
reg [0:2] iu5_ucode_d;
reg iu5_2ucode_d;
reg iu5_fuse_nop_d;
reg [0:2] iu5_error_d;
reg iu5_btb_entry_d;
reg [0:1] iu5_btb_hist_d;
reg iu5_bta_val_d;
reg [0:19] iu5_fusion_d;
reg iu5_rte_lq_d;
reg iu5_rte_sq_d;
reg iu5_rte_fx0_d;
reg iu5_rte_fx1_d;
reg iu5_rte_axu0_d;
reg iu5_rte_axu1_d;
reg iu5_valop_d;
reg iu5_ord_d;
reg iu5_cord_d;
reg iu5_spec_d;
reg iu5_type_fp_d;
reg iu5_type_ap_d;
reg iu5_type_spv_d;
reg iu5_type_st_d;
reg iu5_async_block_d;
reg iu5_np1_flush_d;
reg iu5_core_block_d;
reg iu5_isram_d;
reg iu5_isload_d;
reg iu5_isstore_d;
reg [0:31] iu5_instr_d;
reg [62-`EFF_IFAR_WIDTH:61] iu5_ifar_d;
reg [62-`EFF_IFAR_WIDTH:61] iu5_bta_d;
reg [0:3] iu5_ilat_d;
reg iu5_t1_v_d;
reg [0:2] iu5_t1_t_d;
reg [0:`GPR_POOL_ENC-1] iu5_t1_a_d;
reg iu5_t2_v_d;
reg [0:`GPR_POOL_ENC-1] iu5_t2_a_d;
reg [0:2] iu5_t2_t_d;
reg iu5_t3_v_d;
reg [0:`GPR_POOL_ENC-1] iu5_t3_a_d;
reg [0:2] iu5_t3_t_d;
reg iu5_s1_v_d;
reg [0:`GPR_POOL_ENC-1] iu5_s1_a_d;
reg [0:2] iu5_s1_t_d;
reg iu5_s2_v_d;
reg [0:`GPR_POOL_ENC-1] iu5_s2_a_d;
reg [0:2] iu5_s2_t_d;
reg iu5_s3_v_d;
reg [0:`GPR_POOL_ENC-1] iu5_s3_a_d;
reg [0:2] iu5_s3_t_d;
reg iu5_br_pred_d;
reg iu5_bh_update_d;
reg [0:1] iu5_bh0_hist_d;
reg [0:1] iu5_bh1_hist_d;
reg [0:1] iu5_bh2_hist_d;
reg [0:17] iu5_gshare_d;
reg [0:2] iu5_ls_ptr_d;
reg iu5_match_d;
wire iu5_vld_q;
wire [0:2] iu5_ucode_q;
wire iu5_2ucode_q;
wire iu5_fuse_nop_q;
wire [0:2] iu5_error_q;
wire iu5_btb_entry_q;
wire [0:1] iu5_btb_hist_q;
wire iu5_bta_val_q;
wire [0:19] iu5_fusion_q;
wire iu5_rte_lq_q;
wire iu5_rte_sq_q;
wire iu5_rte_fx0_q;
wire iu5_rte_fx1_q;
wire iu5_rte_axu0_q;
wire iu5_rte_axu1_q;
wire iu5_valop_q;
wire iu5_ord_q;
wire iu5_cord_q;
wire iu5_spec_q;
wire iu5_type_fp_q;
wire iu5_type_ap_q;
wire iu5_type_spv_q;
wire iu5_type_st_q;
wire iu5_async_block_q;
wire iu5_np1_flush_q;
wire iu5_core_block_q;
wire iu5_isram_q;
wire iu5_isload_q;
wire iu5_isstore_q;
wire [0:31] iu5_instr_q;
wire [62-`EFF_IFAR_WIDTH:61] iu5_ifar_q;
wire [62-`EFF_IFAR_WIDTH:61] iu5_bta_q;
wire [0:3] iu5_ilat_q;
wire iu5_t1_v_q;
wire [0:2] iu5_t1_t_q;
wire [0:`GPR_POOL_ENC-1] iu5_t1_a_q;
wire iu5_t2_v_q;
wire [0:`GPR_POOL_ENC-1] iu5_t2_a_q;
wire [0:2] iu5_t2_t_q;
wire iu5_t3_v_q;
wire [0:`GPR_POOL_ENC-1] iu5_t3_a_q;
wire [0:2] iu5_t3_t_q;
wire iu5_s1_v_q;
wire [0:`GPR_POOL_ENC-1] iu5_s1_a_q;
wire [0:2] iu5_s1_t_q;
wire iu5_s2_v_q;
wire [0:`GPR_POOL_ENC-1] iu5_s2_a_q;
wire [0:2] iu5_s2_t_q;
wire iu5_s3_v_q;
wire [0:`GPR_POOL_ENC-1] iu5_s3_a_q;
wire [0:2] iu5_s3_t_q;
wire iu5_br_pred_q;
wire iu5_bh_update_q;
wire [0:1] iu5_bh0_hist_q;
wire [0:1] iu5_bh1_hist_q;
wire [0:1] iu5_bh2_hist_q;
wire [0:17] iu5_gshare_q;
wire [0:2] iu5_ls_ptr_q;
wire iu5_match_q;
wire iu5_vld_din;
wire [0:2] iu5_ucode_din;
wire iu5_2ucode_din;
wire iu5_fuse_nop_din;
wire [0:2] iu5_error_din;
wire iu5_btb_entry_din;
wire [0:1] iu5_btb_hist_din;
wire iu5_bta_val_din;
wire [0:19] iu5_fusion_din;
wire iu5_rte_lq_din;
wire iu5_rte_sq_din;
wire iu5_rte_fx0_din;
wire iu5_rte_fx1_din;
wire iu5_rte_axu0_din;
wire iu5_rte_axu1_din;
wire iu5_valop_din;
wire iu5_ord_din;
wire iu5_cord_din;
wire iu5_spec_din;
wire iu5_type_fp_din;
wire iu5_type_ap_din;
wire iu5_type_spv_din;
wire iu5_type_st_din;
wire iu5_async_block_din;
wire iu5_np1_flush_din;
wire iu5_core_block_din;
wire iu5_isram_din;
wire iu5_isload_din;
wire iu5_isstore_din;
wire [0:31] iu5_instr_din;
wire [62-`EFF_IFAR_WIDTH:61] iu5_ifar_din;
wire [62-`EFF_IFAR_WIDTH:61] iu5_bta_din;
wire [0:3] iu5_ilat_din;
wire iu5_t1_v_din;
wire [0:2] iu5_t1_t_din;
wire [0:`GPR_POOL_ENC-1] iu5_t1_a_din;
wire iu5_t2_v_din;
wire [0:`GPR_POOL_ENC-1] iu5_t2_a_din;
wire [0:2] iu5_t2_t_din;
wire iu5_t3_v_din;
wire [0:`GPR_POOL_ENC-1] iu5_t3_a_din;
wire [0:2] iu5_t3_t_din;
wire iu5_s1_v_din;
wire [0:`GPR_POOL_ENC-1] iu5_s1_a_din;
wire [0:2] iu5_s1_t_din;
wire iu5_s2_v_din;
wire [0:`GPR_POOL_ENC-1] iu5_s2_a_din;
wire [0:2] iu5_s2_t_din;
wire iu5_s3_v_din;
wire [0:`GPR_POOL_ENC-1] iu5_s3_a_din;
wire [0:2] iu5_s3_t_din;
wire iu5_br_pred_din;
wire iu5_bh_update_din;
wire [0:1] iu5_bh0_hist_din;
wire [0:1] iu5_bh1_hist_din;
wire [0:1] iu5_bh2_hist_din;
wire [0:17] iu5_gshare_din;
wire [0:2] iu5_ls_ptr_din;
wire iu5_match_din;
wire iu5_vld_woaxu;
wire [0:2] iu5_ucode_woaxu;
wire iu5_2ucode_woaxu;
wire iu5_fuse_nop_woaxu;
wire [0:2] iu5_error_woaxu;
wire iu5_btb_entry_woaxu;
wire [0:1] iu5_btb_hist_woaxu;
wire iu5_bta_val_woaxu;
wire [0:19] iu5_fusion_woaxu;
wire iu5_rte_lq_woaxu;
wire iu5_rte_sq_woaxu;
wire iu5_rte_fx0_woaxu;
wire iu5_rte_fx1_woaxu;
wire iu5_rte_axu0_woaxu;
wire iu5_rte_axu1_woaxu;
wire iu5_valop_woaxu;
wire iu5_ord_woaxu;
wire iu5_cord_woaxu;
wire iu5_spec_woaxu;
wire iu5_type_fp_woaxu;
wire iu5_type_ap_woaxu;
wire iu5_type_spv_woaxu;
wire iu5_type_st_woaxu;
wire iu5_async_block_woaxu;
wire iu5_np1_flush_woaxu;
wire iu5_core_block_woaxu;
wire iu5_isram_woaxu;
wire iu5_isload_woaxu;
wire iu5_isstore_woaxu;
wire [0:31] iu5_instr_woaxu;
wire [62-`EFF_IFAR_WIDTH:61] iu5_ifar_woaxu;
wire [62-`EFF_IFAR_WIDTH:61] iu5_bta_woaxu;
wire [0:3] iu5_ilat_woaxu;
wire iu5_t1_v_woaxu;
wire [0:2] iu5_t1_t_woaxu;
wire [0:`GPR_POOL_ENC-1] iu5_t1_a_woaxu;
wire iu5_t2_v_woaxu;
wire [0:`GPR_POOL_ENC-1] iu5_t2_a_woaxu;
wire [0:2] iu5_t2_t_woaxu;
wire iu5_t3_v_woaxu;
wire [0:`GPR_POOL_ENC-1] iu5_t3_a_woaxu;
wire [0:2] iu5_t3_t_woaxu;
wire iu5_s1_v_woaxu;
wire [0:`GPR_POOL_ENC-1] iu5_s1_a_woaxu;
wire [0:2] iu5_s1_t_woaxu;
wire iu5_s2_v_woaxu;
wire [0:`GPR_POOL_ENC-1] iu5_s2_a_woaxu;
wire [0:2] iu5_s2_t_woaxu;
wire iu5_s3_v_woaxu;
wire [0:`GPR_POOL_ENC-1] iu5_s3_a_woaxu;
wire [0:2] iu5_s3_t_woaxu;
wire iu5_br_pred_woaxu;
wire iu5_bh_update_woaxu;
wire [0:1] iu5_bh0_hist_woaxu;
wire [0:1] iu5_bh1_hist_woaxu;
wire [0:1] iu5_bh2_hist_woaxu;
wire [0:17] iu5_gshare_woaxu;
wire [0:2] iu5_ls_ptr_woaxu;
wire iu5_match_woaxu;
wire [0:5] iu5_t1_a_woaxu6;
wire [0:5] iu5_t2_a_woaxu6;
wire [0:5] iu5_t3_a_woaxu6;
wire [0:5] iu5_s1_a_woaxu6;
wire [0:5] iu5_s2_a_woaxu6;
wire [0:5] iu5_s3_a_woaxu6;
wire iu5_valid_act;
wire iu5_instr_act;
wire iu4_is_mtiar;
wire spr_epcr_dgtmi_q;
wire spr_msrp_uclep_q;
wire spr_msr_pr_q;
wire spr_msr_gs_q;
wire spr_msr_ucle_q;
wire spr_ccr2_ucode_dis_q;
// Pervasive
wire pc_iu_func_sl_thold_1;
wire pc_iu_func_sl_thold_0;
wire pc_iu_func_sl_thold_0_b;
wire pc_iu_sg_1;
wire pc_iu_sg_0;
wire force_t;
wire axu;
wire naxu;
wire multi_cr;
wire or_ppr32_val;
wire or_ppr32;
wire mtspr_trace_val;
wire erativax_val;
wire tlbwe_with_binv;
wire mtspr_nop;
wire mfspr_nop;
wire spr_nop;
wire mtspr_tar;
wire mfspr_tar;
wire mtspr_tenc;
wire mtspr_xucr0;
wire mtspr_ccr0;
wire mfspr_mmucr1;
//temp
wire [0:5] SPR_addr;
//@@ START OF EXECUTABLE CODE FOR IUQ_IDEC
assign tiup = 1'b1;
assign cp_flush_d = cp_iu_iu4_flush | br_iu_redirect | uc_ib_iu3_flush_all;
assign iu4_instr_vld = ib_id_iu4_valid;
assign iu4_ifar = ib_id_iu4_ifar;
assign iu4_bta = ib_id_iu4_bta;
assign iu4_instr = ib_id_iu4_instr[0:31];
assign iu4_instr_br_pred = ib_id_iu4_instr[32];
assign iu4_instr_bh_update = ib_id_iu4_instr[33];
assign iu4_instr_bh0_hist = ib_id_iu4_instr[34:35];
assign iu4_instr_bh1_hist = ib_id_iu4_instr[36:37];
assign iu4_instr_bh2_hist = ib_id_iu4_instr[38:39];
assign iu4_instr_gshare = {ib_id_iu4_instr[40:49], ib_id_iu4_instr[62:69]};
assign iu4_instr_ls_ptr = ib_id_iu4_instr[50:52];
assign iu4_instr_match = (spr_dec_mask[0:31] & iu4_instr[0:31]) == (spr_dec_mask[0:31] & spr_dec_match[0:31]);
assign iu4_instr_error = ib_id_iu4_instr[53:55];
// bit 56 = to ucode, and is not used by decode any more
// bit 57 = fuse en, and is not used by decode any more
assign iu4_fuse_nop = ib_id_iu4_instr[57];
assign iu4_instr_btb_entry = ib_id_iu4_instr[58];
assign iu4_instr_btb_hist = ib_id_iu4_instr[59:60];
assign iu4_instr_bta_val = ib_id_iu4_instr[61];
assign iu4_instr_ucode_ext = ib_id_iu4_ucode_ext;
assign iu4_instr_ucode = ib_id_iu4_ucode;
assign iu4_instr_2ucode = ib_id_iu4_instr[59];
assign iu4_instr_isram = ib_id_iu4_isram;
assign iu4_is_mtiar = ((iu4_instr[0:5] == 6'b011111) & (iu4_instr[11:20] == 10'b1001011011) & (iu4_instr[21:30] == 10'b0111010011)) ? 1'b1 :
1'b0;
assign iu4_fuse_val = ib_id_iu4_fuse_val;
assign iu4_fuse_cmp = ib_id_iu4_fuse_data;
assign iu4_is_mtcpcr = (~iu4_fuse_val & (iu4_instr[0:5] == 6'b011111) & (iu4_instr[21:30] == 10'b0111010011)) &
((iu4_instr[11:20] == 10'b1000011001) | (iu4_instr[11:20] == 10'b1000111001) | (iu4_instr[11:20] == 10'b1001011001) |
(iu4_instr[11:20] == 10'b1010011001) | (iu4_instr[11:20] == 10'b1010111001) | (iu4_instr[11:20] == 10'b1011011001));
//64-bit core
generate
if (`GPR_WIDTH == 64)
begin : c64
assign core64 = 1'b1;
end
endgenerate
//32-bit core
generate
if (`GPR_WIDTH == 32)
begin : c32
assign core64 = 1'b0;
end
endgenerate
assign multi_cr = (~(iu4_instr[12:19] == 8'b00000000 | iu4_instr[12:19] == 8'b10000000 | iu4_instr[12:19] == 8'b01000000 | iu4_instr[12:19] == 8'b00100000 | iu4_instr[12:19] == 8'b00010000 | iu4_instr[12:19] == 8'b00001000 | iu4_instr[12:19] == 8'b00000100 | iu4_instr[12:19] == 8'b00000010 | iu4_instr[12:19] == 8'b00000001));
assign or_ppr32 = (iu4_instr[0:5] == 6'b011111 & iu4_instr[21:31] == 11'b01101111000) & (iu4_instr[6:10] == iu4_instr[11:15] & iu4_instr[11:15] == iu4_instr[16:20]);
assign or_ppr32_val = (iu4_instr[16:20] == 5'b11111 | iu4_instr[16:20] == 5'b00001 | iu4_instr[16:20] == 5'b00110 | iu4_instr[16:20] == 5'b00010 | iu4_instr[16:20] == 5'b00101 | iu4_instr[16:20] == 5'b00011 | iu4_instr[16:20] == 5'b00111) & or_ppr32 & (~(|(iu4_instr_ucode)));
assign mtspr_trace_val = (iu4_instr[0:5] == 6'b011111) & (iu4_instr[11:30] == 20'b01110111110111010011);
assign erativax_val = (iu4_instr[0:5] == 6'b011111 & iu4_instr[21:30] == 10'b1100110011);
assign tlbwe_with_binv = (iu4_instr[0:5] == 6'b011111 & iu4_instr[21:30] == 10'b1111010010) & mm_iu_tlbwe_binv;
assign mtspr_nop = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:13] == 3'b010 & iu4_instr[16:30] == 15'b110010111010011;
assign mfspr_nop = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:13] == 3'b010 & iu4_instr[16:30] == 15'b110010101010011;
assign spr_nop = mtspr_nop | mfspr_nop;
assign mtspr_tar = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b0111111001 & iu4_instr[21:30] == 10'b0111010011;
assign mfspr_tar = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b0111111001 & iu4_instr[21:30] == 10'b0101010011;
assign mtspr_tenc = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1011101101 & iu4_instr[21:30] == 10'b0111010011;
assign mtspr_xucr0 = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1011011111 & iu4_instr[21:30] == 10'b0111010011;
assign mtspr_ccr0 = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1000011111 & iu4_instr[21:30] == 10'b0111010011;
assign mfspr_mmucr1 = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1110111111 & iu4_instr[21:30] == 10'b0101010011;
//-------------------------------------------------------------------------------------------------------
// branch dependency. branches bite. branches can update LR and CTR, and can use LR, CR, and CTR.
//-------------------------------------------------------------------------------------------------------
//-------------------------------------------------------------------------------------------------------
// Main Instruction Decoder. Select and Type definitions
//-------------------------------------------------------------------------------------------------------
//table_start
//?TABLE br_dep LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET);
//*INPUTS*===========================================================*OUTPUTS*=============================================*
//| | |
//| | updateslr |
//| | | updatescr |
//| | | | updatesctr |
//| | | | | updatesxer |
//| core64 | | | | | |
//| | iu4_fuse_val | | | | | |
//| | iu4_instr | iu4_fuse_cmp | | | | | useslr |
//| | | iu4_instr | | | | | | | | usescr |
//| | | | iu4_instr | | | | | | | | | usesctr |
//| | | | | iu4_instr iu4_instr | | iu4_fuse_cmp | | | | | | | | usesxer usescr2 |
//| | | | | | | | | | | | | | | | | | | usestar | usescr_sel |
//| | | | | | | | | | | | | | | | | | | | | | updatescr_sel|
//| | | | | 1111111112 22222222233 | | 22222222233 | | | | | | | | | | | | | |
//| | 012345 6 8 1234567890 12345678901 | 012345 12345678901 | | | | | | | | | | | 01 01 |
//*TYPE*=============================================================+=====================================================+
//| P PPPPPP P P PPPPPPPPPP PPPPPPPPPPP P PPPPPP PPPPPPPPPPP | S S S S S S S S S S SS SS |
//*TERMS*============================================================+=====================================================+
//| . 010000 . 0 .......... ..........0 1 00101. ........... | 0 1 1 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bc/bca
//| . 010000 . 0 .......... ..........1 1 00101. ........... | 1 1 1 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bcl/bcla
//| . 010000 . 1 .......... ..........0 1 00101. ........... | 0 1 0 0 0 0 0 1 0 0 00 01 | cmpi/cmpli -> bc/bca
//| . 010000 . 1 .......... ..........1 1 00101. ........... | 1 1 0 0 0 0 0 1 0 0 00 01 | cmpi/cmpli -> bcl/bcla
//| . 010011 . 1 .......... 00000100000 1 00101. ........... | 0 1 0 0 1 0 0 1 0 0 00 01 | cmpi/cmpli -> bclr
//| . 010011 . 1 .......... 00000100001 1 00101. ........... | 1 1 0 0 1 0 0 1 0 0 00 01 | cmpi/cmpli -> bclrl
//| . 010011 . 1 .......... 10001100000 1 00101. ........... | 0 1 0 0 0 0 0 1 1 0 00 01 | cmpi/cmpli -> bctar
//| . 010011 . 1 .......... 10001100001 1 00101. ........... | 1 1 0 0 0 0 0 1 1 0 00 01 | cmpi/cmpli -> bctarl
//| . 010011 . 1 .......... 10000100000 1 00101. ........... | 0 1 0 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bcctr
//| . 010011 . 1 .......... 10000100001 1 00101. ........... | 1 1 0 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bcctrl
//| . 010000 . 1 .......... ..........0 1 011111 0000.00000. | 0 1 0 0 0 0 0 1 0 0 00 01 | cmp/cmpl -> bc/bca
//| . 010000 . 1 .......... ..........1 1 011111 0000.00000. | 1 1 0 0 0 0 0 1 0 0 00 01 | cmp/cmpl -> bcl/bcla
//| . 011111 . . .......... 01000010101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | add.
//| . 011111 . . .......... 00000010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addc
//| . 011111 . . .......... 00000010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addc.
//| . 011111 . . .......... 10000010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addco
//| . 011111 . . .......... 10000010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addco.
//| . 011111 . . .......... 00100010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | adde
//| . 011111 . . .......... 00100010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | adde.
//| . 011111 . . .......... 10100010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addeo
//| . 011111 . . .......... 10100010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addeo.
//| . 001100 . . .......... ........... 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addic
//| . 001101 . . .......... ........... 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addic.
//| . 011111 . . .......... 00111010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addme
//| . 011111 . . .......... 00111010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addme.
//| . 011111 . . .......... 10111010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addmeo
//| . 011111 . . .......... 10111010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addmeo.
//| . 011111 . . .......... 11000010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addo
//| . 011111 . . .......... 11000010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addo.
//| . 011111 . . .......... 00110010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addze
//| . 011111 . . .......... 00110010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addze.
//| . 011111 . . .......... 10110010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addzeo
//| . 011111 . . .......... 10110010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addzeo.
//| . 011111 . . .......... 00000111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | and.
//| . 011111 . . .......... 00001111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | andc.
//| . 011100 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | andi.
//| . 011101 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | andis.
//| . 010000 0 0 .......... .........00 0 ...... ........... | 0 0 1 0 0 1 1 0 0 0 01 00 | bc
//| . 010000 0 1 .......... .........00 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 01 00 | bc
//| . 010000 0 0 .......... .........10 0 ...... ........... | 0 0 1 0 0 1 1 0 0 0 01 00 | bca
//| . 010000 0 1 .......... .........10 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 01 00 | bca
//| . 010011 0 1 .......... 10000100000 0 ...... ........... | 0 0 0 0 0 1 1 0 0 0 01 00 | bcctr
//| . 010011 0 1 .......... 10000100001 0 ...... ........... | 1 0 0 0 0 1 1 0 0 0 01 00 | bcctrl
//| . 010000 0 0 .......... .........01 0 ...... ........... | 1 0 1 0 0 1 1 0 0 0 01 00 | bcl
//| . 010000 0 1 .......... .........01 0 ...... ........... | 1 0 0 0 0 1 0 0 0 0 01 00 | bcl
//| . 010000 0 0 .......... .........11 0 ...... ........... | 1 0 1 0 0 1 1 0 0 0 01 00 | bcla
//| . 010000 0 1 .......... .........11 0 ...... ........... | 1 0 0 0 0 1 0 0 0 0 01 00 | bcla
//| . 010011 0 0 .......... 00000100000 0 ...... ........... | 0 0 1 0 1 1 1 0 0 0 01 00 | bclr
//| . 010011 0 1 .......... 00000100000 0 ...... ........... | 0 0 0 0 1 1 0 0 0 0 01 00 | bclr
//| . 010011 0 0 .......... 00000100001 0 ...... ........... | 1 0 1 0 1 1 1 0 0 0 01 00 | bclrl
//| . 010011 0 1 .......... 00000100001 0 ...... ........... | 1 0 0 0 1 1 0 0 0 0 01 00 | bclrl
//| . 010011 0 0 .......... 10001100000 0 ...... ........... | 0 0 1 0 0 1 1 0 1 0 01 00 | bctar
//| . 010011 0 1 .......... 10001100000 0 ...... ........... | 0 0 0 0 0 1 0 0 1 0 01 00 | bctar
//| . 010011 0 0 .......... 10001100001 0 ...... ........... | 1 0 1 0 0 1 1 0 1 0 01 00 | bctarl
//| . 010011 0 1 .......... 10001100001 0 ...... ........... | 1 0 0 0 0 1 0 0 1 0 01 00 | bctarl
//| . 010000 1 0 .......... .........00 0 ...... ........... | 0 0 1 0 0 0 1 0 0 0 01 00 | bc
//| . 010000 1 1 .......... .........00 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 01 00 | bc
//| . 010000 1 0 .......... .........10 0 ...... ........... | 0 0 1 0 0 0 1 0 0 0 01 00 | bca
//| . 010000 1 1 .......... .........10 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 01 00 | bca
//| . 010011 1 1 .......... 10000100000 0 ...... ........... | 0 0 0 0 0 0 1 0 0 0 01 00 | bcctr
//| . 010011 1 1 .......... 10000100001 0 ...... ........... | 1 0 0 0 0 0 1 0 0 0 01 00 | bcctrl
//| . 010000 1 0 .......... .........01 0 ...... ........... | 1 0 1 0 0 0 1 0 0 0 01 00 | bcl
//| . 010000 1 1 .......... .........01 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 01 00 | bcl
//| . 010000 1 0 .......... .........11 0 ...... ........... | 1 0 1 0 0 0 1 0 0 0 01 00 | bcla
//| . 010000 1 1 .......... .........11 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 01 00 | bcla
//| . 010011 1 0 .......... 00000100000 0 ...... ........... | 0 0 1 0 1 0 1 0 0 0 01 00 | bclr
//| . 010011 1 1 .......... 00000100000 0 ...... ........... | 0 0 0 0 1 0 0 0 0 0 01 00 | bclr
//| . 010011 1 0 .......... 00000100001 0 ...... ........... | 1 0 1 0 1 0 1 0 0 0 01 00 | bclrl
//| . 010011 1 1 .......... 00000100001 0 ...... ........... | 1 0 0 0 1 0 0 0 0 0 01 00 | bclrl
//| . 010011 1 0 .......... 10001100000 0 ...... ........... | 0 0 1 0 0 0 1 0 1 0 01 00 | bctar
//| . 010011 1 1 .......... 10001100000 0 ...... ........... | 0 0 0 0 0 0 0 0 1 0 01 00 | bctar
//| . 010011 1 0 .......... 10001100001 0 ...... ........... | 1 0 1 0 0 0 1 0 1 0 01 00 | bctarl
//| . 010011 1 1 .......... 10001100001 0 ...... ........... | 1 0 0 0 0 0 0 0 1 0 01 00 | bctarl
//| . 010010 . . .......... .........01 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 00 00 | bl
//| . 010010 . . .......... .........11 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 00 00 | bla
//| . 011111 . . .......... 0000000000. 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmp
//| . 001011 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmpi
//| . 011111 . . .......... 0000100000. 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmpl
//| . 001010 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmpli
//| 1 011111 . . .......... 00001110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | cntlzd.
//| . 011111 . . .......... 00000110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | cntlzw.
//| . 010011 . . .......... 0100000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crand
//| . 010011 . . .......... 0010000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crandc
//| . 010011 . . .......... 0100100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | creqv
//| . 010011 . . .......... 0011100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crnand
//| . 010011 . . .......... 0000100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crnor
//| . 010011 . . .......... 0111000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | cror
//| . 010011 . . .......... 0110100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crorc
//| . 010011 . . .......... 0011000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crxor
//| 1 011111 . . .......... 01111010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divd.
//| 1 011111 . . .......... 01101010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divde.
//| 1 011111 . . .......... 11101010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divdeo
//| 1 011111 . . .......... 11101010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divdeo.
//| 1 011111 . . .......... 01100010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divdeu.
//| 1 011111 . . .......... 11100010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divdeuo
//| 1 011111 . . .......... 11100010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divdeuo.
//| 1 011111 . . .......... 11111010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divdo
//| 1 011111 . . .......... 11111010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divdo.
//| 1 011111 . . .......... 01110010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divdu.
//| 1 011111 . . .......... 11110010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divduo
//| 1 011111 . . .......... 11110010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divduo.
//| . 011111 . . .......... 01111010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divw.
//| . 011111 . . .......... 01101010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divwe.
//| . 011111 . . .......... 11101010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divweo
//| . 011111 . . .......... 11101010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divweo.
//| . 011111 . . .......... 01100010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divweu.
//| . 011111 . . .......... 11100010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divweuo
//| . 011111 . . .......... 11100010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divweuo.
//| . 011111 . . .......... 11111010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divwo
//| . 011111 . . .......... 11111010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divwo.
//| . 011111 . . .......... 01110010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divwu.
//| . 011111 . . .......... 11110010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divwuo
//| . 011111 . . .......... 11110010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divwuo.
//| . 011111 . . .......... 00010011100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | dlmzb
//| . 011111 . . .......... 00010011101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | dlmzb.
//| . 011111 . . .......... 01000111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | eqv.
//| . 011111 . . .......... 00100100111 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | eratsx.
//| . 011111 . . .......... 11101110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | extsb.
//| . 011111 . . .......... 11100110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | extsh.
//| 1 011111 . . .......... 11110110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | extsw.
//| . 011111 . . .......... 11101101100 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | icswepx
//| . 011111 . . .......... 11101101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | icswepx.
//| . 011111 . . .......... 01100101100 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | icswx
//| . 011111 . . .......... 01100101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | icswx.
//| . 011111 . . .......... .....01111. 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 10 00 | isel
//| . 011111 . . .......... 00110101001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | ldawx.
//| . 011111 . . .......... 1000010101. 0 ...... ........... | 0 0 0 0 0 0 0 1 0 0 00 00 | lswx
//| . 010011 . . .......... 0000000000. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 0 01 10 | mcrf
//| . 011111 . . .......... 1000000000. 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 10 | mcrxr
//| . 011111 . . 0......... 0000010011. 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 00 00 | mfcr
//| . 011111 . . .......... 00001000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mfdp.
//| . 011111 . . .......... 00000000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mfdpx.
//| . 011111 . . .......... 0001010011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mfmsr
//| . 011111 . . 1......... 0000010011. 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 11 00 | mfocrf Script needs update
//| . 011111 . . 0100000000 0101010011. 0 ...... ........... | 0 0 0 0 1 0 0 0 0 0 00 00 | mfspr (lr )
//| . 011111 . . 0100100000 0101010011. 0 ...... ........... | 0 0 0 0 0 0 1 0 0 0 00 00 | mfspr (ctr)
//| . 011111 . . 0000100000 0101010011. 0 ...... ........... | 0 0 0 0 0 0 0 1 0 0 00 00 | mfspr (xer)
//| . 011111 . . P.PP.PPPPP 0101010011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mfspr (spr) Not sure why script is putting next line in
//| . 011111 . . .......... 0101110011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mftb
//| . 011111 . . 0......... 0010010000. 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | mtcrf
//| . 011111 . . .......... 00011000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mtdp.
//| . 011111 . . .......... 00010000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mtdpx.
//| . 011111 . . .......... 0010010010. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mtmsr
//| . 011111 . . 1PPPPPPPP. 0010010000. 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 11 | mtocrf
//| . 011111 . . 100000000. 0010010000. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mtocrf
//| . 011111 . . 0100000000 0111010011. 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 00 00 | mtspr (lr )
//| . 011111 . . 0100100000 0111010011. 0 ...... ........... | 0 0 1 0 0 0 0 0 0 0 00 00 | mtspr (ctr)
//| . 011111 . . 0000100000 0111010011. 0 ...... ........... | 0 0 0 1 0 0 0 0 0 0 00 00 | mtspr (xer)
//| . 011111 . . P.PP.PPPPP 0111010011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mtspr (spr) Not sure why script is putting next line in
//| 1 011111 . . .......... .0010010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhd.
//| 1 011111 . . .......... .0000010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhdu.
//| . 011111 . . .......... .0010010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhw.
//| . 011111 . . .......... .0000010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhwu.
//| 1 011111 . . .......... 00111010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulld.
//| 1 011111 . . .......... 10111010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | mulldo
//| 1 011111 . . .......... 10111010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | mulldo.
//| . 011111 . . .......... 00111010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mullw.
//| . 011111 . . .......... 10111010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | mullwo
//| . 011111 . . .......... 10111010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | mullwo.
//| . 011111 . . .......... 01110111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | nand.
//| . 011111 . . .......... 00011010001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | neg.
//| . 011111 . . .......... 10011010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | nego
//| . 011111 . . .......... 10011010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | nego.
//| . 011111 . . .......... 00011111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | nor.
//| . 011111 . . .......... 01101111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | or.
//| . 011111 . . .......... 01100111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | orc.
//| . 010011 . . .......... 0000110011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfci
//| . 010011 . . .......... 0001100110. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfgi
//| . 010011 . . .......... 0000110010. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfi
//| . 010011 . . .......... 0000100110. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfmci
//| 1 011110 . . .......... ......10001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldcl.
//| 1 011110 . . .......... ......10011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldcr.
//| 1 011110 . . .......... ......010.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldic.
//| 1 011110 . . .......... ......000.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldicl.
//| 1 011110 . . .......... ......001.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldicr.
//| 1 011110 . . .......... ......011.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldimi.
//| . 010100 . . .......... ..........1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rlwimi.
//| . 010101 . . .......... ..........1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rlwinm.
//| . 010111 . . .......... ..........1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rlwnm.
//| . 010001 . . .......... .........1. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | sc
//| 1 011111 . . .......... 00000110111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | sld.
//| . 011111 . . .......... 00000110001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | slw.
//| 1 011111 . . .......... 11000110100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | srad
//| 1 011111 . . .......... 11000110101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | srad.
//| 1 011111 . . .......... 110011101.0 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | sradi
//| 1 011111 . . .......... 110011101.1 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | sradi.
//| . 011111 . . .......... 11000110000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | sraw
//| . 011111 . . .......... 11000110001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | sraw.
//| . 011111 . . .......... 11001110000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | srawi
//| . 011111 . . .......... 11001110001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | srawi.
//| 1 011111 . . .......... 10000110111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | srd.
//| . 011111 . . .......... 10000110001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | srw.
//| . 011111 . . .......... 10101101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | stbcx. had to remove xer user to fix string ops that have 4 sources
//| 1 011111 . . .......... 00110101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | stdcx. had to remove xer user to fix string ops that have 4 sources
//| . 011111 . . .......... 10110101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | sthcx. had to remove xer user to fix string ops that have 4 sources
//| . 011111 . . .......... 1010010101. 0 ...... ........... | 0 0 0 0 0 0 0 1 0 0 00 00 | stswx
//| . 011111 . . .......... 00100101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | stwcx. had to remove xer user to fix string ops that have 4 sources
//| . 011111 . . .......... 00001010001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | subf.
//| . 011111 . . .......... 00000010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfc
//| . 011111 . . .......... 00000010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfc.
//| . 011111 . . .......... 10000010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfco
//| . 011111 . . .......... 10000010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfco.
//| . 011111 . . .......... 00100010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfe
//| . 011111 . . .......... 00100010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfe.
//| . 011111 . . .......... 10100010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfeo
//| . 011111 . . .......... 10100010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfeo.
//| . 001000 . . .......... ........... 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfic
//| . 011111 . . .......... 00111010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfme
//| . 011111 . . .......... 00111010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfme.
//| . 011111 . . .......... 10111010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfmeo
//| . 011111 . . .......... 10111010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfmeo.
//| . 011111 . . .......... 10001010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfo
//| . 011111 . . .......... 10001010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfo.
//| . 011111 . . .......... 00110010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfze
//| . 011111 . . .......... 00110010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfze.
//| . 011111 . . .......... 10110010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfzeo
//| . 011111 . . .......... 10110010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfzeo.
//| . 011111 . . .......... 11010100101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | tlbsrx.
//| . 011111 . . .......... 11100100101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | tlbsx.
//| . 011111 . . .......... 1110000110. 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | wchkall
//| . 011111 . . .......... 1110100110. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | wclr
//| . 011111 . . .......... 0010000011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | wrtee
//| . 011111 . . .......... 0010100011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | wrteei
//| . 011111 . . .......... 01001111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | xor.
//*END*==============================================================+=====================================================+
//?TABLE END br_dep;
//
//?TABLE instruction_decoder LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET);
//*INPUTS*========================================================*OUTPUTS*========================================================================================*
//| | |
//| core64 | |
//| | iu4_fuse_val | |
//| | iu4_instr | iu4_fuse_cmp | ta_vld s1_vld s2_vld s3_vld |
//| | | iu4_instr | | | | | | | |
//| | | | iu4_instr | | | | ta_sel | s1_sel | s2_sel | |
//| | | | | iu4_instr | | iu4_fuse_cmp | | | | | | | | |
//| | | | | | | | | | | | | | | | | |
//| | | | | | | | | | | | | | | | | |
//| | | | | | | | | | | | | | | | | ordered |
//| | | | | | | | | | | | | | | | | | spec |
//| | | | | | | | | | | | | | | | | | | isload |
//| | | | | | | | | | | | | | | | | | | | zero_r0 |
//| | | | | | | | | | | | | | | | | | | | | dec_val |
//| | | | | | | | | | | | | | | | | issue_lq | | | | | |
//| | | | | | | | | | | | | | | | | | issue_sq | | | | | async_block |
//| | | | | | | | | | | | | | | | | | | issue_fx0 | | | | | | np1_flush |
//| | | | | | | | | | | | | | | | | | | | issue_fx1 latency | | | | | | | core_block |
//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | no_ram |
//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | no_pre |
//| | | | 1 1111111112 22222222233 | | 22222222233 | | | | | | | | | | | | | | | | | | | | | | | |
//| | 012345 67890 1234567890 12345678901 | 012345 12345678901 | | | | | | | | | | | | 0123 | | | | | | | | | | |
//*TYPE*==========================================================+================================================================================================+
//| P PPPPPP PPPPP PPPPPPPPPP PPPPPPPPPPP P PPPPPP PPPPPPPPPPP | S S S S S S S S S S S SSSS S S S S S S S S S S |
//*TERMS*=========================================================+================================================================================================+
//| . ...... ..... .......... ........... 1 011111 0000000000. | 0 - 1 0 1 0 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmp (fused)
//| . ...... ..... .......... ........... 1 001011 ........... | 0 - 1 0 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmpi (fused)
//| . ...... ..... .......... ........... 1 011111 0000100000. | 0 - 1 0 1 0 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmpl (fused)
//| . ...... ..... .......... ........... 1 001010 ........... | 0 - 1 0 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmpli (fused)
//| . 011111 ..... .......... 01000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0000 0 0 0 0 1 0 0 0 0 0 | add
//| . 011111 ..... .......... 01000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | add.
//| . 011111 ..... .......... 00000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addc
//| . 011111 ..... .......... 00000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addc.
//| . 011111 ..... .......... 10000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addco
//| . 011111 ..... .......... 10000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addco.
//| . 011111 ..... .......... 00100010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | adde
//| . 011111 ..... .......... 00100010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | adde.
//| . 011111 ..... .......... 10100010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addeo
//| . 011111 ..... .......... 10100010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addeo.
//| . 011111 ..... .......... .001001010. 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | addg6s
//| . 001110 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0000 0 0 0 1 1 0 0 0 0 0 | addi
//| . 001100 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addic
//| . 001101 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addic.
//| . 001111 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0000 0 0 0 1 1 0 0 0 0 0 | addis
//| . 011111 ..... .......... 00111010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addme
//| . 011111 ..... .......... 00111010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addme.
//| . 011111 ..... .......... 10111010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addmeo
//| . 011111 ..... .......... 10111010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addmeo.
//| . 011111 ..... .......... 11000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addo
//| . 011111 ..... .......... 11000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addo.
//| . 011111 ..... .......... 00110010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addze
//| . 011111 ..... .......... 00110010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addze.
//| . 011111 ..... .......... 10110010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addzeo
//| . 011111 ..... .......... 10110010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addzeo.
//| . 011111 ..... .......... 00000111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | and
//| . 011111 ..... .......... 00000111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | and.
//| . 011111 ..... .......... 00001111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andc
//| . 011111 ..... .......... 00001111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andc.
//| . 011100 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andi.
//| . 011101 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andis.
//| . 000000 ..... .......... 0100000000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0110 0 0 0 0 1 0 1 0 0 0 | attn
//| . 010010 ..... .......... .........00 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | b
//| . 010010 ..... .......... .........10 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | ba
//| . 010000 ..0.. .......... .........00 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bc
//| . 010000 ..1.. .......... .........00 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bc
//| . 010000 ..0.. .......... .........10 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bca
//| . 010000 ..1.. .......... .........10 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bca
//| . 010011 ..1.. .......... 10000100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcctr
//| . 010011 ..1.. .......... 10000100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcctrl
//| . 010000 ..0.. .......... .........01 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcl
//| . 010000 ..1.. .......... .........01 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcl
//| . 010000 ..0.. .......... .........11 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcla
//| . 010000 ..1.. .......... .........11 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcla
//| . 010011 ..0.. .......... 00000100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclr
//| . 010011 ..1.. .......... 00000100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclr
//| . 010011 ..0.. .......... 00000100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclrl
//| . 010011 ..1.. .......... 00000100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclrl
//| . 010011 ..0.. .......... 10001100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctar
//| . 010011 ..1.. .......... 10001100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctar
//| . 010011 ..0.. .......... 10001100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctarl
//| . 010011 ..1.. .......... 10001100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctarl
//| . 010010 ..... .......... .........01 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bl
//| . 010010 ..... .......... .........11 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bla
//| 1 011111 ..... .......... 0011111100. 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | bpermd
//| . 011111 ..... .......... 0100111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cbcdtd
//| . 011111 ..... .......... 0100011010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cdtbcd
//| . 011111 ..... .......... 0000000000. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmp
//| . 011111 ..... .......... 0111111100. 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpb
//| . 001011 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpi
//| . 011111 ..... .......... 0000100000. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpl
//| . 001010 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpli
//| 1 011111 ..... .......... 00001110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzd
//| 1 011111 ..... .......... 00001110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzd.
//| . 011111 ..... .......... 00000110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzw
//| . 011111 ..... .......... 00000110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzw.
//| . 010011 ..... .......... 0100000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crand
//| . 010011 ..... .......... 0010000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crandc
//| . 010011 ..... .......... 0100100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | creqv
//| . 010011 ..... .......... 0011100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crnand
//| . 010011 ..... .......... 0000100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crnor
//| . 010011 ..... .......... 0111000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cror
//| . 010011 ..... .......... 0110100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crorc
//| . 010011 ..... .......... 0011000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crxor
//| . 011111 ..... .......... 1011110110. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 0 0 ---- 0 0 0 1 1 0 0 0 0 0 | dcba
//| . 011111 ..... .......... 0001010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbf
//| . 011111 ..... .......... 0001111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbfep
//| . 011111 ..... .......... 0111010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbi
//| . 011111 ..... .......... 0110000110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcblc
//| . 011111 ..... .......... 0000110110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbst
//| . 011111 ..... .......... 0000111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbstep
//| . 011111 ..... .......... 0100010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbt
//| . 011111 ..... .......... 0100111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtep
//| . 011111 ..... .......... 0010100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtls
//| . 011111 ..... .......... 0011110110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtst
//| . 011111 ..... .......... 0011111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtstep
//| . 011111 ..... .......... 0010000110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtstls
//| . 011111 ..... .......... 1111110110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbz
//| . 011111 ..... .......... 1111111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbzep
//| . 011111 ..... .......... 0111000110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | dci
//| 1 011111 ..... .......... 01111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divd
//| 1 011111 ..... .......... 01111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divd.
//| 1 011111 ..... .......... 01101010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divde
//| 1 011111 ..... .......... 01101010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divde.
//| 1 011111 ..... .......... 11101010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeo
//| 1 011111 ..... .......... 11101010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeo.
//| 1 011111 ..... .......... 01100010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeu
//| 1 011111 ..... .......... 01100010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeu.
//| 1 011111 ..... .......... 11100010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeuo
//| 1 011111 ..... .......... 11100010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeuo.
//| 1 011111 ..... .......... 11111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdo
//| 1 011111 ..... .......... 11111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdo.
//| 1 011111 ..... .......... 01110010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdu
//| 1 011111 ..... .......... 01110010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdu.
//| 1 011111 ..... .......... 11110010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divduo
//| 1 011111 ..... .......... 11110010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divduo.
//| . 011111 ..... .......... 01111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divw
//| . 011111 ..... .......... 01111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divw.
//| . 011111 ..... .......... 01101010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwe
//| . 011111 ..... .......... 01101010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwe.
//| . 011111 ..... .......... 11101010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweo
//| . 011111 ..... .......... 11101010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweo.
//| . 011111 ..... .......... 01100010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweu
//| . 011111 ..... .......... 01100010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweu.
//| . 011111 ..... .......... 11100010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweuo
//| . 011111 ..... .......... 11100010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweuo.
//| . 011111 ..... .......... 11111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwo
//| . 011111 ..... .......... 11111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwo.
//| . 011111 ..... .......... 01110010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwu
//| . 011111 ..... .......... 01110010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwu.
//| . 011111 ..... .......... 11110010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwuo
//| . 011111 ..... .......... 11110010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwuo.
//| . 011111 ..... .......... 00010011100 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | dlmzb
//| . 011111 ..... .......... 00010011101 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | dlmzb.
//| . 010011 ..... .......... 0011000110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 1 0 0 0 | dnh
//| . 011111 ..... .......... 0100001110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | ehpriv
//| . 011111 ..... .......... 01000111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | eqv
//| . 011111 ..... .......... 01000111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | eqv.
//| . 011111 ..... .......... 0000110011. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0111 1 0 0 1 1 1 1 1 0 0 | eratilx
//| . 011111 ..... .......... 1100110011. 0 ...... ........... | 0 - 1 0 1 0 1 0 0 1 0 0111 1 0 0 1 1 1 1 1 0 0 | erativax
//| . 011111 ..... .......... 0010110011. 0 ...... ........... | 1 0 0 - 1 1 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | eratre
//| . 011111 ..... .......... 0010010011. 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 1 1 1 0 0 0 0 | eratsx
//| . 011111 ..... .......... 00100100111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | eratsx.
//| . 011111 ..... .......... 0011010011. 0 ...... ........... | 0 - 1 1 1 1 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | eratwe
//| . 011111 ..... .......... 11101110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsb
//| . 011111 ..... .......... 11101110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsb.
//| . 011111 ..... .......... 11100110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsh
//| . 011111 ..... .......... 11100110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsh.
//| 1 011111 ..... .......... 11110110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsw
//| 1 011111 ..... .......... 11110110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsw.
//| . 011111 ..... .......... 1111010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | icbi
//| . 011111 ..... .......... 1111011111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | icbiep
//| . 011111 ..... .......... 0011100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | icblc
//| . 011111 ..... .......... 0000010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | icbt
//| . 011111 ..... .......... 0111100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | icbtls
//| . 011111 ..... .......... 1111000110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | ici
//| . 011111 ..... .......... 11101101100 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 0 | icswepx
//| . 011111 ..... .......... 11101101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 1 0 0 0 | icswepx.
//| . 011111 ..... .......... 01100101100 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 0 | icswx
//| . 011111 ..... .......... 01100101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 1 0 0 0 | icswx.
//| . 011111 ..... .......... .....01111. 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 1 1 0 0 0 0 0 | isel
//| . 010011 ..... .......... 0010010110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 1 0 0 0 | isync
//| . 011111 ..... .......... 0000110100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | lbarx
//| . 011111 ..... .......... 0001011111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lbepx
//| . 100010 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lbz
//| . 100011 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lbzu
//| . 011111 ..... .......... 0001110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lbzux
//| . 011111 ..... .......... 0001010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lbzx
//| 1 111010 ..... .......... .........00 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ld
//| 1 011111 ..... .......... 0001010100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | ldarx
//| . 011111 ..... .......... 00110101001 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | ldawx.
//| 1 011111 ..... .......... 1000010100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ldbrx
//| 1 011111 ..... .......... 0000011101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ldepx
//| 1 111010 ..... .......... .........01 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | ldu
//| 1 011111 ..... .......... 0000110101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | ldux
//| 1 011111 ..... .......... 0000010101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ldx
//| . 101010 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lha
//| . 011111 ..... .......... 0001110100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | lharx
//| . 101011 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhau
//| . 011111 ..... .......... 0101110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhaux
//| . 011111 ..... .......... 0101010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhax
//| . 011111 ..... .......... 1100010110. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhbrx
//| . 011111 ..... .......... 0100011111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhepx
//| . 101000 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhz
//| . 101001 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhzu
//| . 011111 ..... .......... 0100110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhzux
//| . 011111 ..... .......... 0100010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhzx
//| . 101110 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 1 0 | lmw
//| . 011111 ..... .......... 1001010101. 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 1 1 0 0 0 1 0 | lswi
//| . 011111 ..... .......... 1000010101. 0 ...... ........... | 1 0 1 0 1 0 0 1 1 0 1 0011 0 1 0 1 1 0 0 0 1 0 | lswx
//| 1 111010 ..... .......... .........10 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwa
//| . 011111 ..... .......... 0000010100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | lwarx
//| 1 011111 ..... .......... 0101110101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lwaux
//| 1 011111 ..... .......... 0101010101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwax
//| . 011111 ..... .......... 1000010110. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwbrx
//| . 011111 ..... .......... 0000011111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwepx
//| . 100000 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwz
//| . 100001 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lwzu
//| . 011111 ..... .......... 0000110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lwzux
//| . 011111 ..... .......... 0000010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwzx
//| . 011111 ..... .......... 0000110010. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | makeitso
//| . 011111 ..... .......... 1101010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | mbar
//| . 010011 ..... .......... 0000000000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mcrf
//| . 011111 ..... .......... 1000000000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 1 0 | mcrxr
//| . 011111 ..... 0......... 0000010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 1 0 | mfcr
//| . 011111 ..... .......... 0101000011. 0 ...... ........... | 0 0 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mfdcr
//| . 011111 ..... .......... 0100100011. 0 ...... ........... | 0 0 0 - 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mfdcrux
//| . 011111 ..... .......... 0100000011. 0 ...... ........... | 0 0 0 - 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mfdcrx
//| . 011111 ..... .......... 00001000110 0 ...... ........... | 1 0 0 - 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdp
//| . 011111 ..... .......... 00001000111 0 ...... ........... | 1 0 0 - 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdp.
//| . 011111 ..... .......... 00000000110 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdpx
//| . 011111 ..... .......... 00000000111 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdpx.
//| . 011111 ..... .......... 0001010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mfmsr
//| . 011111 ..... 1......... 0000010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfocrf
//| . 011111 ..... 0100000000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfspr (lr) need clean up
//| . 011111 ..... 0100100000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfspr (ctr)
//| . 011111 ..... 0000100000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfspr (xer)
//| . 011111 ..... 0000000000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mfspr (spr)
//| . 011111 ..... P.PP.PPPPP 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mfspr (spr)
//| . 011111 ..... .......... 0101110011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mftb
//| . 011111 ..... .......... 0011101110. 0 ...... ........... | 0 - 0 - 1 0 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | msgclr
//| . 011111 ..... .......... 0011001110. 0 ...... ........... | 0 - 0 - 1 0 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | msgsnd
//| . 011111 ..... 0......... 0010010000. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 1 0 | mtcrf
//| . 011111 ..... .......... 0111000011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mtdcr
//| . 011111 ..... .......... 0110100011. 0 ...... ........... | 0 - 1 1 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mtdcrux
//| . 011111 ..... .......... 0110000011. 0 ...... ........... | 0 - 1 1 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mtdcrx
//| . 011111 ..... .......... 00011000110 0 ...... ........... | 0 - 0 - 0 - 1 1 0 0 0 0011 0 0 0 0 1 0 0 0 0 0 | mtdp
//| . 011111 ..... .......... 00011000111 0 ...... ........... | 0 - 0 - 0 - 1 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mtdp.
//| . 011111 ..... .......... 00010000110 0 ...... ........... | 0 - 1 0 0 - 1 1 0 0 0 0011 0 0 0 0 1 0 0 0 0 0 | mtdpx
//| . 011111 ..... .......... 00010000111 0 ...... ........... | 0 - 1 0 0 - 1 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mtdpx.
//| . 011111 ..... .......... 0010010010. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | mtmsr
//| . 011111 ..... 1PPPPPPPP. 0010010000. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mtocrf
//| . 011111 ..... 100000000. 0010010000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | mtocrf
//| . 011111 ..... 0100000000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 1 0 0 0 0 | mtspr (lr)
//| . 011111 ..... 0100100000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 1 0 0 0 0 | mtspr (ctr)
//| . 011111 ..... 0000100000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 1 0 0 0 0 | mtspr (xer)
//| . 011111 ..... 0000000000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | mtspr (spr)
//| . 011111 ..... P.PP.PPPPP 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | mtspr (spr)
//| 1 011111 ..... .......... .0010010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhd
//| 1 011111 ..... .......... .0010010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhd.
//| 1 011111 ..... .......... .0000010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhdu
//| 1 011111 ..... .......... .0000010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhdu.
//| . 011111 ..... .......... .0010010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhw
//| . 011111 ..... .......... .0010010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhw.
//| . 011111 ..... .......... .0000010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhwu
//| . 011111 ..... .......... .0000010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhwu.
//| 1 011111 ..... .......... 00111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0110 0 0 0 0 1 0 0 0 0 0 | mulld
//| 1 011111 ..... .......... 00111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0110 0 0 0 0 1 0 0 0 0 0 | mulld.
//| 1 011111 ..... .......... 10111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulldo
//| 1 011111 ..... .......... 10111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulldo.
//| . 000111 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 0 0101 0 0 0 0 1 0 0 0 0 0 | mulli
//| . 011111 ..... .......... 00111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullw
//| . 011111 ..... .......... 00111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullw.
//| . 011111 ..... .......... 10111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullwo
//| . 011111 ..... .......... 10111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullwo.
//| . 011111 ..... .......... 01110111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nand
//| . 011111 ..... .......... 01110111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nand.
//| . 011111 ..... .......... 00011010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | neg
//| . 011111 ..... .......... 00011010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | neg.
//| . 011111 ..... .......... 10011010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nego
//| . 011111 ..... .......... 10011010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nego.
//| . 011111 ..... .......... 00011111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nor
//| . 011111 ..... .......... 00011111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nor.
//| . 011111 ..... .......... 01101111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | or
//| . 011111 ..... .......... 01101111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | or.
//| . 011111 ..... .......... 01100111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | orc
//| . 011111 ..... .......... 01100111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | orc.
//| . 011000 00000 0000000000 00000000000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | ori (nop)
//| . 011000 PPPPP PPPPPPPPPP PPPPPPPPPPP 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | ori (ori)
//| . 011001 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | oris
//| . 011111 ..... .......... 0001111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | popcntb
//| 1 011111 ..... .......... 0111111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | popcntd
//| . 011111 ..... .......... 0101111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | popcntw
//| 1 011111 ..... .......... 0010111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | prtyd
//| . 011111 ..... .......... 0010011010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | prtyw
//| . 011111 ..... .......... 1000010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1000110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1001010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1001110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1010010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1010110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1011010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 011111 ..... .......... 1011110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved
//| . 010011 ..... .......... 0000110011. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfci
//| . 010011 ..... .......... 0001100110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfgi
//| . 010011 ..... .......... 0000110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfi
//| . 010011 ..... .......... 0000100110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfmci
//| 1 011110 ..... .......... ......10000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcl
//| 1 011110 ..... .......... ......10001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcl.
//| 1 011110 ..... .......... ......10010 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcr
//| 1 011110 ..... .......... ......10011 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcr.
//| 1 011110 ..... .......... ......010.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldic
//| 1 011110 ..... .......... ......010.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldic.
//| 1 011110 ..... .......... ......000.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicl
//| 1 011110 ..... .......... ......000.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicl.
//| 1 011110 ..... .......... ......001.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicr
//| 1 011110 ..... .......... ......001.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicr.
//| 1 011110 ..... .......... ......011.0 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldimi
//| 1 011110 ..... .......... ......011.1 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldimi.
//| . 010100 ..... .......... ..........0 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwimi
//| . 010100 ..... .......... ..........1 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwimi.
//| . 010101 ..... .......... ..........0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwinm
//| . 010101 ..... .......... ..........1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwinm.
//| . 010111 ..... .......... ..........0 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwnm
//| . 010111 ..... .......... ..........1 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwnm.
//| . 010001 ..... .......... .........1. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | sc
//| 1 011111 ..... .......... 00000110110 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sld
//| 1 011111 ..... .......... 00000110111 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sld.
//| . 011111 ..... .......... 00000110000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | slw
//| . 011111 ..... .......... 00000110001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | slw.
//| 1 011111 ..... .......... 11000110100 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srad
//| 1 011111 ..... .......... 11000110101 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srad.
//| 1 011111 ..... .......... 110011101.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sradi
//| 1 011111 ..... .......... 110011101.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sradi.
//| . 011111 ..... .......... 11000110000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sraw
//| . 011111 ..... .......... 11000110001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sraw.
//| . 011111 ..... .......... 11001110000 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srawi
//| . 011111 ..... .......... 11001110001 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srawi.
//| 1 011111 ..... .......... 10000110110 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srd
//| 1 011111 ..... .......... 10000110111 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srd.
//| . 011111 ..... .......... 10000110000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srw
//| . 011111 ..... .......... 10000110001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srw.
//| . 100110 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stb
//| . 011111 ..... .......... 10101101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | stbcx.
//| . 011111 ..... .......... 0011011111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stbepx
//| . 100111 ..... .......... ........... 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stbu
//| . 011111 ..... .......... 0011110111. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stbux
//| . 011111 ..... .......... 0011010111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stbx
//| 1 111110 ..... .......... .........00 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | std
//| 1 011111 ..... .......... 1010010100. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stdbrx
//| 1 011111 ..... .......... 00110101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | stdcx.
//| 1 011111 ..... .......... 0010011101. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stdepx
//| 1 111110 ..... .......... .........01 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stdu
//| 1 011111 ..... .......... 0010110101. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stdux
//| 1 011111 ..... .......... 0010010101. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stdx
//| . 101100 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sth
//| . 011111 ..... .......... 1110010110. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sthbrx
//| . 011111 ..... .......... 10110101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | sthcx.
//| . 011111 ..... .......... 0110011111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sthepx
//| . 101101 ..... .......... ........... 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | sthu
//| . 011111 ..... .......... 0110110111. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | sthux
//| . 011111 ..... .......... 0110010111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sthx
//| . 101111 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 1 0 0 0 0011 0 1 0 1 1 0 0 0 1 0 | stmw always ucode only preissue
//| . 011111 ..... .......... 1011010101. 0 ...... ........... | 0 - 1 0 0 - 0 1 0 0 0 0011 0 1 0 1 1 0 0 0 1 0 | stswi always ucode only preissue
//| . 011111 ..... .......... 1010010101. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 1 0011 0 1 0 1 1 0 0 0 1 0 | stswx always ucode only preissue
//| . 100100 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stw
//| . 011111 ..... .......... 1010010110. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stwbrx
//| . 011111 ..... .......... 00100101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | stwcx.
//| . 011111 ..... .......... 0010011111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stwepx
//| . 100101 ..... .......... ........... 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stwu
//| . 011111 ..... .......... 0010110111. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stwux
//| . 011111 ..... .......... 0010010111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stwx
//| . 011111 ..... .......... 00001010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0000 0 0 0 0 1 0 0 0 0 0 | subf
//| . 011111 ..... .......... 00001010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subf.
//| . 011111 ..... .......... 00000010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfc
//| . 011111 ..... .......... 00000010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfc.
//| . 011111 ..... .......... 10000010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfco
//| . 011111 ..... .......... 10000010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfco.
//| . 011111 ..... .......... 00100010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfe
//| . 011111 ..... .......... 00100010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfe.
//| . 011111 ..... .......... 10100010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfeo
//| . 011111 ..... .......... 10100010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfeo.
//| . 001000 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfic
//| . 011111 ..... .......... 00111010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfme
//| . 011111 ..... .......... 00111010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfme.
//| . 011111 ..... .......... 10111010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfmeo
//| . 011111 ..... .......... 10111010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfmeo.
//| . 011111 ..... .......... 10001010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfo
//| . 011111 ..... .......... 10001010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfo.
//| . 011111 ..... .......... 00110010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfze
//| . 011111 ..... .......... 00110010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfze.
//| . 011111 ..... .......... 10110010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfzeo
//| . 011111 ..... .......... 10110010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfzeo.
//| . 011111 ...00 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | hwsync
//| . 011111 ...01 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | lwsync
//| . 011111 ...10 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | reserve sync
//| . 011111 ...11 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | reserve sync
//| 1 011111 ..... .......... 0001000100. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | td
//| 1 000010 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | tdi
//| . 011111 ..... .......... 0000010010. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 1 1 0 0 | tlbilx
//| . 011111 ..... .......... 1100010010. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 1 1 0 0 | tlbivax
//| . 011111 ..... .......... 1110110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0110 1 0 0 0 1 1 0 0 0 0 | tlbre
//| . 011111 ..... .......... 11010100101 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 0 0 0 0 | tlbsrx.
//| . 011111 ..... .......... 1110010010. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 0 0 0 0 | tlbsx
//| . 011111 ..... .......... 11100100101 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 0 1 1 0 0 0 0 | tlbsx.
//| . 011111 ..... .......... 1000110110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | tlbsync
//| . 011111 ..... .......... 1111010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0110 1 0 0 0 1 1 1 0 0 0 | tlbwe
//| . 011111 ..... .......... 0000000100. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | tw
//| . 000011 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | twi
//| . 011111 ..... .......... 0000111110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0000 1 0 0 0 1 1 0 0 0 0 | wait
//| . 011111 ..... .......... 1110000110. 0 ...... ........... | 0 - 0 - 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 0 0 | wchkall
//| . 011111 ..... .......... 1110100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | wclr
//| . 011111 ..... .......... 0010000011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | wrtee
//| . 011111 ..... .......... 0010100011. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | wrteei
//| . 011111 ..... .......... 01001111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xor
//| . 011111 ..... .......... 01001111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xor.
//| . 011010 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xori
//| . 011011 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xoris
//*END*===========================================================+================================================================================================+
//?TABLE END instruction_decoder ;
//table_end
//assign_start
assign br_dep_pt[1] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[31] ,
iu4_fuse_cmp[0] , iu4_fuse_cmp[1] ,
iu4_fuse_cmp[2] , iu4_fuse_cmp[3] ,
iu4_fuse_cmp[4] , iu4_fuse_cmp[5] ,
iu4_fuse_cmp[21] , iu4_fuse_cmp[22] ,
iu4_fuse_cmp[23] , iu4_fuse_cmp[24] ,
iu4_fuse_cmp[26] , iu4_fuse_cmp[27] ,
iu4_fuse_cmp[28] , iu4_fuse_cmp[29] ,
iu4_fuse_cmp[30] }) === 23'b01000011011111000000000);
assign br_dep_pt[2] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_fuse_val ,
iu4_fuse_cmp[0] , iu4_fuse_cmp[1] ,
iu4_fuse_cmp[2] , iu4_fuse_cmp[3] ,
iu4_fuse_cmp[4] , iu4_fuse_cmp[5] ,
iu4_fuse_cmp[21] , iu4_fuse_cmp[22] ,
iu4_fuse_cmp[23] , iu4_fuse_cmp[24] ,
iu4_fuse_cmp[26] , iu4_fuse_cmp[27] ,
iu4_fuse_cmp[28] , iu4_fuse_cmp[29] ,
iu4_fuse_cmp[30] }) === 23'b01000011011111000000000);
assign br_dep_pt[3] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[12] ,
iu4_instr[13] , iu4_instr[14] ,
iu4_instr[15] , iu4_instr[16] ,
iu4_instr[17] , iu4_instr[18] ,
iu4_instr[19] , iu4_instr[20] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 27'b011111010010000001110100110);
assign br_dep_pt[4] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[12] ,
iu4_instr[13] , iu4_instr[14] ,
iu4_instr[15] , iu4_instr[16] ,
iu4_instr[17] , iu4_instr[18] ,
iu4_instr[19] , iu4_instr[20] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 27'b011111010000000001110100110);
assign br_dep_pt[5] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[12] ,
iu4_instr[13] , iu4_instr[14] ,
iu4_instr[15] , iu4_instr[16] ,
iu4_instr[17] , iu4_instr[18] ,
iu4_instr[19] , iu4_instr[20] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 27'b011111010000000001010100110);
assign br_dep_pt[6] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[12] ,
iu4_instr[13] , iu4_instr[14] ,
iu4_instr[15] , iu4_instr[16] ,
iu4_instr[17] , iu4_instr[18] ,
iu4_instr[19] , iu4_instr[20] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 27'b011111000010000001110100110);
assign br_dep_pt[7] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[12] ,
iu4_instr[13] , iu4_instr[14] ,
iu4_instr[15] , iu4_instr[16] ,
iu4_instr[17] , iu4_instr[18] ,
iu4_instr[19] , iu4_instr[20] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 27'b011111010010000001010100110);
assign br_dep_pt[8] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[11] ,
iu4_instr[12] , iu4_instr[13] ,
iu4_instr[14] , iu4_instr[15] ,
iu4_instr[16] , iu4_instr[17] ,
iu4_instr[18] , iu4_instr[19] ,
iu4_instr[20] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 26'b01111000010000001010100110);
assign br_dep_pt[9] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_cmp[0] ,
iu4_fuse_cmp[1] , iu4_fuse_cmp[2] ,
iu4_fuse_cmp[3] , iu4_fuse_cmp[4]
}) === 22'b0100111000010000100101);
assign br_dep_pt[10] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_cmp[0] ,
iu4_fuse_cmp[1] , iu4_fuse_cmp[2] ,
iu4_fuse_cmp[3] , iu4_fuse_cmp[4]
}) === 22'b0100111100010000100101);
assign br_dep_pt[11] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val ,
iu4_fuse_cmp[0] , iu4_fuse_cmp[1] ,
iu4_fuse_cmp[2] , iu4_fuse_cmp[3] ,
iu4_fuse_cmp[4] }) === 23'b01001111000110000100101);
assign br_dep_pt[12] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val ,
iu4_fuse_cmp[0] , iu4_fuse_cmp[1] ,
iu4_fuse_cmp[2] , iu4_fuse_cmp[3] ,
iu4_fuse_cmp[4] }) === 23'b01001111000010000100101);
assign br_dep_pt[13] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val ,
iu4_fuse_cmp[0] , iu4_fuse_cmp[1] ,
iu4_fuse_cmp[2] , iu4_fuse_cmp[3] ,
iu4_fuse_cmp[4] }) === 23'b01001110000010000100101);
assign br_dep_pt[14] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_fuse_cmp[0] ,
iu4_fuse_cmp[1] , iu4_fuse_cmp[2] ,
iu4_fuse_cmp[3] , iu4_fuse_cmp[4]
}) === 12'b010000000101);
assign br_dep_pt[15] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[31] , iu4_fuse_cmp[0] ,
iu4_fuse_cmp[1] , iu4_fuse_cmp[2] ,
iu4_fuse_cmp[3] , iu4_fuse_cmp[4]
}) === 12'b010000100101);
assign br_dep_pt[16] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[6] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01001100000000000);
assign br_dep_pt[17] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 17'b01001000001000010);
assign br_dep_pt[18] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[6] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 18'b010011010001100000);
assign br_dep_pt[19] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 18'b010011010001100000);
assign br_dep_pt[20] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[6] , iu4_instr[8] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 18'b010011010000100000);
assign br_dep_pt[21] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 17'b01001100011000010);
assign br_dep_pt[22] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b1011111001110110);
assign br_dep_pt[23] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b0111000100111010);
assign br_dep_pt[24] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 18'b010011110000100000);
assign br_dep_pt[25] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[8] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 18'b010011000000100000);
assign br_dep_pt[26] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[8] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 17'b01001100001000010);
assign br_dep_pt[27] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 18'b011111100000100110);
assign br_dep_pt[28] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[19] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[29] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[18] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[30] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[17] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[31] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[16] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[32] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[14] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[33] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[13] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[34] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[15] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[35] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[11] , iu4_instr[12] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 19'b0111111100100100000);
assign br_dep_pt[36] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_fuse_val , iu4_fuse_cmp[0] ,
iu4_fuse_cmp[1] , iu4_fuse_cmp[2] ,
iu4_fuse_cmp[3] , iu4_fuse_cmp[4]
}) === 12'b010000100101);
assign br_dep_pt[37] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[2] ,
iu4_instr[3] , iu4_instr[4] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_fuse_val }) === 17'b10111111100111010);
assign br_dep_pt[38] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01001110001100000);
assign br_dep_pt[39] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01111100010011100);
assign br_dep_pt[40] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[2] ,
iu4_instr[3] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b1011100110101010);
assign br_dep_pt[41] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[2] ,
iu4_instr[3] , iu4_instr[4] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_fuse_val
}) === 16'b1011111101110100);
assign br_dep_pt[42] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01001100000100000);
assign br_dep_pt[43] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b101111100110010);
assign br_dep_pt[44] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_fuse_val
}) === 16'b0111111011101010);
assign br_dep_pt[45] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01111100000100110);
assign br_dep_pt[46] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b0111101101011010);
assign br_dep_pt[47] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01111111100001100);
assign br_dep_pt[48] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011111001100010);
assign br_dep_pt[49] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0100110101000010);
assign br_dep_pt[50] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[11] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01111000100100000);
assign br_dep_pt[51] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0100110110000010);
assign br_dep_pt[52] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[2] ,
iu4_instr[3] , iu4_instr[4] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[30] ,
iu4_fuse_val }) === 15'b101111111101010);
assign br_dep_pt[53] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0100110011000010);
assign br_dep_pt[54] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b0111110101001010);
assign br_dep_pt[55] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0100110001000010);
assign br_dep_pt[56] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011111011011010);
assign br_dep_pt[57] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 15'b011111111010110);
assign br_dep_pt[58] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0100110100000010);
assign br_dep_pt[59] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[2] ,
iu4_instr[3] , iu4_instr[4] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b1011111110011000);
assign br_dep_pt[60] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0111111001010000);
assign br_dep_pt[61] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b1011111101101010);
assign br_dep_pt[62] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01001100000000000);
assign br_dep_pt[63] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0100110010000010);
assign br_dep_pt[64] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 15'b011111000101010);
assign br_dep_pt[65] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b0111001101010010);
assign br_dep_pt[66] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b0111001001001110);
assign br_dep_pt[67] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0111111000010100);
assign br_dep_pt[68] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 16'b0111111100110000);
assign br_dep_pt[69] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011101001011010);
assign br_dep_pt[70] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011101101110010);
assign br_dep_pt[71] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011111100101010);
assign br_dep_pt[72] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[21] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_instr[31] , iu4_fuse_val
}) === 16'b1011100001101010);
assign br_dep_pt[73] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 13'b0111011010010);
assign br_dep_pt[74] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011100011110010);
assign br_dep_pt[75] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[29] , iu4_instr[30] ,
iu4_fuse_val }) === 17'b01111110000000000);
assign br_dep_pt[76] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[31] , iu4_fuse_val
}) === 14'b10111011101010);
assign br_dep_pt[77] =
(({ core64 , iu4_instr[0] ,
iu4_instr[1] , iu4_instr[3] ,
iu4_instr[5] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b101110000101110);
assign br_dep_pt[78] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[21] , iu4_instr[22] ,
iu4_instr[23] , iu4_instr[24] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 15'b011111101101010);
assign br_dep_pt[79] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[22] , iu4_instr[23] ,
iu4_instr[24] , iu4_instr[25] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[31] , iu4_fuse_val
}) === 14'b01110111010110);
assign br_dep_pt[80] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[2] , iu4_instr[3] ,
iu4_instr[4] , iu4_instr[5] ,
iu4_instr[26] , iu4_instr[27] ,
iu4_instr[28] , iu4_instr[29] ,
iu4_instr[30] , iu4_fuse_val
}) === 12'b011111011110);
assign br_dep_pt[81] =
(({ iu4_instr[0] , iu4_instr[1] ,
iu4_instr[3] , iu4_instr[5] ,
iu4_instr[22] , iu4_instr[24] ,
iu4_instr[25] , iu4_instr[26] ,
iu4_instr[27] , iu4_instr[28] ,
iu4_instr[30] , iu4_instr[31] ,
iu4_fuse_val }) === 13'b0111000010010);
assign br_dep_pt[82] =
(({ iu4_instr[0] , iu4_instr[1] ,