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10460 lines
399 KiB
Verilog

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
`timescale 1 ns / 1 ns
// Description: Completion Unit
//
//*****************************************************************************
`include "tri_a2o.vh"
module iuq_cpl_ctrl(
// Clocks
input clk,
input rst,
// Pervasive
input d_mode_dc,
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input func_slp_sl_force,
input func_slp_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,
// Perfomance selectors
input pc_iu_event_bus_enable,
input [0:2] pc_iu_event_count_mode,
input [0:15] spr_cp_perf_event_mux_ctrls,
input [0:3] event_bus_in,
output [0:3] event_bus_out,
// Instruction Dispatch
input rn_cp_iu6_i0_vld,
input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_i0_itag,
input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i0_ifar,
input [0:31] rn_cp_iu6_i0_instr,
input [0:2] rn_cp_iu6_i0_ucode,
input rn_cp_iu6_i0_fuse_nop,
input [0:2] rn_cp_iu6_i0_error,
input rn_cp_iu6_i0_valop,
input rn_cp_iu6_i0_is_rfi,
input rn_cp_iu6_i0_is_rfgi,
input rn_cp_iu6_i0_is_rfci,
input rn_cp_iu6_i0_is_rfmci,
input rn_cp_iu6_i0_is_isync,
input rn_cp_iu6_i0_is_sc,
input rn_cp_iu6_i0_is_np1_flush,
input rn_cp_iu6_i0_is_sc_hyp,
input rn_cp_iu6_i0_is_sc_ill,
input rn_cp_iu6_i0_is_dcr_ill,
input rn_cp_iu6_i0_is_attn,
input rn_cp_iu6_i0_is_ehpriv,
input rn_cp_iu6_i0_is_folded,
input rn_cp_iu6_i0_async_block,
input rn_cp_iu6_i0_is_br,
input rn_cp_iu6_i0_br_add_chk,
input rn_cp_iu6_i0_pred,
input rn_cp_iu6_i0_rollover,
input rn_cp_iu6_i0_isram,
input rn_cp_iu6_i0_match,
input rn_cp_iu6_i1_vld,
input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_i1_itag,
input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i1_ifar,
input [0:31] rn_cp_iu6_i1_instr,
input [0:2] rn_cp_iu6_i1_ucode,
input rn_cp_iu6_i1_fuse_nop,
input [0:2] rn_cp_iu6_i1_error,
input rn_cp_iu6_i1_valop,
input rn_cp_iu6_i1_is_rfi,
input rn_cp_iu6_i1_is_rfgi,
input rn_cp_iu6_i1_is_rfci,
input rn_cp_iu6_i1_is_rfmci,
input rn_cp_iu6_i1_is_isync,
input rn_cp_iu6_i1_is_sc,
input rn_cp_iu6_i1_is_np1_flush,
input rn_cp_iu6_i1_is_sc_hyp,
input rn_cp_iu6_i1_is_sc_ill,
input rn_cp_iu6_i1_is_dcr_ill,
input rn_cp_iu6_i1_is_attn,
input rn_cp_iu6_i1_is_ehpriv,
input rn_cp_iu6_i1_is_folded,
input rn_cp_iu6_i1_async_block,
input rn_cp_iu6_i1_is_br,
input rn_cp_iu6_i1_br_add_chk,
input rn_cp_iu6_i1_pred,
input rn_cp_iu6_i1_rollover,
input rn_cp_iu6_i1_isram,
input rn_cp_iu6_i1_match,
// Instruction Completed
output cp2_i0_completed,
output cp2_i1_completed,
output [1:`ITAG_SIZE_ENC-1] cp0_i0_completed_itag,
output [1:`ITAG_SIZE_ENC-1] cp0_i1_completed_itag,
input [62-`EFF_IFAR_WIDTH:61] cp2_i0_ifar,
input [62-`EFF_IFAR_WIDTH:61] cp2_i1_ifar,
input [62-`EFF_IFAR_WIDTH:61] cp2_i0_bp_bta,
input [62-`EFF_IFAR_WIDTH:61] cp2_i1_bp_bta,
input cp2_i0_rfi,
input cp2_i0_rfgi,
input cp2_i0_rfci,
input cp2_i0_rfmci,
input cp2_i0_sc,
input cp2_i0_mtiar,
input cp2_i0_rollover,
input cp2_i1_rfi,
input cp2_i1_rfgi,
input cp2_i1_rfci,
input cp2_i1_rfmci,
input cp2_i1_sc,
input cp2_i1_mtiar,
input cp2_i1_rollover,
output cp2_i0_bp_pred,
output cp2_i1_bp_pred,
output cp2_i0_br_pred,
output cp2_i1_br_pred,
output [62-`EFF_IFAR_WIDTH:61] cp2_i0_bta,
output [62-`EFF_IFAR_WIDTH:61] cp2_i1_bta,
input cp2_i0_isram,
input cp2_i1_isram,
input cp2_i0_ld,
input cp2_i1_ld,
input cp2_i0_st,
input cp2_i1_st,
input cp2_i0_epid,
input cp2_i1_epid,
input [0:2] cp2_i0_ucode,
input [0:2] cp2_i1_ucode,
input cp2_i0_type_fp,
input cp2_i1_type_fp,
input cp2_i0_type_ap,
input cp2_i1_type_ap,
input cp2_i0_type_spv,
input cp2_i1_type_spv,
input cp2_i0_type_st,
input cp2_i1_type_st,
input cp2_i0_attn,
input cp2_i1_attn,
input cp2_i0_fuse_nop,
input cp2_i1_fuse_nop,
input cp2_i0_icmp_block,
input cp2_i1_icmp_block,
output cp2_i0_axu_exception_val,
output [0:3] cp2_i0_axu_exception,
output cp2_i1_axu_exception_val,
output [0:3] cp2_i1_axu_exception,
input cp2_i0_nonspec,
input cp2_i1_nonspec,
// LQ Instruction Executed
input lq0_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] lq0_iu_itag,
input lq0_iu_n_flush,
input lq0_iu_np1_flush,
input lq0_iu_dacr_type,
input [0:3] lq0_iu_dacrw,
input [0:31] lq0_iu_instr,
input [64-`GPR_WIDTH:63] lq0_iu_eff_addr,
input lq0_iu_exception_val,
input [0:5] lq0_iu_exception,
input lq0_iu_flush2ucode,
input lq0_iu_flush2ucode_type,
input lq0_iu_recirc_val,
input lq0_iu_dear_val,
input lq1_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] lq1_iu_itag,
input lq1_iu_n_flush,
input lq1_iu_np1_flush,
input lq1_iu_exception_val,
input [0:5] lq1_iu_exception,
input lq1_iu_dacr_type,
input [0:3] lq1_iu_dacrw,
input [0:3] lq1_iu_perf_events,
output iu_lq_i0_completed,
output [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag,
output iu_lq_i1_completed,
output [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag,
output iu_lq_recirc_val,
// BR Instruction Executed
input br_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] br_iu_itag,
input br_iu_redirect,
input [62-`EFF_IFAR_ARCH:61] br_iu_bta,
input br_iu_taken,
input [0:3] br_iu_perf_events,
// XU0 Instruction Executed
input xu_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] xu_iu_itag,
input xu_iu_n_flush,
input xu_iu_np1_flush,
input xu_iu_flush2ucode,
input xu_iu_exception_val,
input [0:4] xu_iu_exception,
input xu_iu_mtiar,
input [62-`EFF_IFAR_ARCH:61] xu_iu_bta,
input [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar,
input [0:3] xu_iu_perf_events,
// XU1 Instruction Executed
input xu1_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] xu1_iu_itag,
// AXU0 Instruction Executed
input axu0_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] axu0_iu_itag,
input axu0_iu_n_flush,
input axu0_iu_np1_flush,
input axu0_iu_n_np1_flush,
input axu0_iu_flush2ucode,
input axu0_iu_flush2ucode_type,
input axu0_iu_exception_val,
input [0:3] axu0_iu_exception,
input [0:3] axu0_iu_perf_events,
// AXU0 Instruction Executed
input axu1_iu_execute_vld,
input [0:`ITAG_SIZE_ENC-1] axu1_iu_itag,
input axu1_iu_n_flush,
input axu1_iu_np1_flush,
input axu1_iu_n_np1_flush,
input axu1_iu_flush2ucode,
input axu1_iu_flush2ucode_type,
input axu1_iu_exception_val,
input [0:3] axu1_iu_exception,
input [0:3] axu1_iu_perf_events,
// Signals to SPR partition
output iu_xu_rfi,
output iu_xu_rfgi,
output iu_xu_rfci,
output iu_xu_rfmci,
output iu_xu_int,
output iu_xu_gint,
output iu_xu_cint,
output iu_xu_mcint,
output [62-`EFF_IFAR_ARCH:61] iu_xu_nia,
output [0:16] iu_xu_esr,
output [0:14] iu_xu_mcsr,
output [0:18] iu_xu_dbsr,
output iu_xu_dear_update,
output [64-`GPR_WIDTH:63] iu_xu_dear,
output iu_xu_dbsr_update,
output iu_xu_dbsr_ude,
output iu_xu_dbsr_ide,
output iu_xu_esr_update,
output iu_xu_act,
output iu_xu_dbell_taken,
output iu_xu_cdbell_taken,
output iu_xu_gdbell_taken,
output iu_xu_gcdbell_taken,
output iu_xu_gmcdbell_taken,
output iu_xu_instr_cpl,
input xu_iu_np1_async_flush,
output iu_xu_async_complete,
input dp_cp_hold_req,
output iu_mm_hold_ack,
input dp_cp_bus_snoop_hold_req,
output iu_mm_bus_snoop_hold_ack,
output iu_spr_eheir_update,
output [0:31] iu_spr_eheir,
input xu_iu_msr_de,
input xu_iu_msr_pr,
input xu_iu_msr_cm,
input xu_iu_msr_gs,
input xu_iu_msr_me,
input xu_iu_dbcr0_edm,
input xu_iu_dbcr0_idm,
input xu_iu_dbcr0_icmp,
input xu_iu_dbcr0_brt,
input xu_iu_dbcr0_irpt,
input xu_iu_dbcr0_trap,
input xu_iu_iac1_en,
input xu_iu_iac2_en,
input xu_iu_iac3_en,
input xu_iu_iac4_en,
input [0:1] xu_iu_dbcr0_dac1,
input [0:1] xu_iu_dbcr0_dac2,
input [0:1] xu_iu_dbcr0_dac3,
input [0:1] xu_iu_dbcr0_dac4,
input xu_iu_dbcr0_ret,
input xu_iu_dbcr1_iac12m,
input xu_iu_dbcr1_iac34m,
input lq_iu_spr_dbcr3_ivc,
input xu_iu_epcr_extgs,
input xu_iu_epcr_dtlbgs,
input xu_iu_epcr_itlbgs,
input xu_iu_epcr_dsigs,
input xu_iu_epcr_isigs,
input xu_iu_epcr_duvd,
input xu_iu_epcr_icm,
input xu_iu_epcr_gicm,
input xu_iu_ccr2_ucode_dis,
input xu_iu_hid_mmu_mode,
input xu_iu_xucr4_mmu_mchk,
// Interrupts
input an_ac_uncond_dbg_event,
input xu_iu_external_mchk,
input xu_iu_ext_interrupt,
input xu_iu_dec_interrupt,
input xu_iu_udec_interrupt,
input xu_iu_perf_interrupt,
input xu_iu_fit_interrupt,
input xu_iu_crit_interrupt,
input xu_iu_wdog_interrupt,
input xu_iu_gwdog_interrupt,
input xu_iu_gfit_interrupt,
input xu_iu_gdec_interrupt,
input xu_iu_dbell_interrupt,
input xu_iu_cdbell_interrupt,
input xu_iu_gdbell_interrupt,
input xu_iu_gcdbell_interrupt,
input xu_iu_gmcdbell_interrupt,
input xu_iu_dbsr_ide,
input axu0_iu_async_fex,
// Flushes
output iu_flush,
output cp_flush_into_uc,
output [43:61] cp_uc_flush_ifar,
output cp_uc_np1_flush,
output cp_flush,
output [0:`ITAG_SIZE_ENC-1] cp_next_itag,
output [0:`ITAG_SIZE_ENC-1] cp_flush_itag,
output [62-`EFF_IFAR_ARCH:61] cp_flush_ifar,
output cp_iu0_flush_2ucode,
output cp_iu0_flush_2ucode_type,
output cp_iu0_flush_nonspec,
input pc_iu_init_reset,
// SPRs
input xu_iu_single_instr_mode,
input spr_single_issue,
input [64-`GPR_WIDTH:51] spr_ivpr,
input [64-`GPR_WIDTH:51] spr_givpr,
input [62-`EFF_IFAR_ARCH:61] spr_iac1,
input [62-`EFF_IFAR_ARCH:61] spr_iac2,
input [62-`EFF_IFAR_ARCH:61] spr_iac3,
input [62-`EFF_IFAR_ARCH:61] spr_iac4,
// Signals from pervasive
input pc_iu_ram_active,
input pc_iu_ram_flush_thread,
input xu_iu_msrovride_enab,
output iu_pc_ram_done,
output iu_pc_ram_interrupt,
output iu_pc_ram_unsupported,
input pc_iu_stop,
input pc_iu_step,
input [0:2] pc_iu_dbg_action,
output iu_pc_step_done,
output [0:`THREADS-1] iu_pc_stop_dbg_event,
output iu_pc_err_debug_event,
output iu_pc_attention_instr,
output iu_pc_err_mchk_disabled,
output ac_an_debug_trigger,
output iu_xu_stop,
output iu_xu_quiesce,
// MMU Errors
input mm_iu_ierat_rel_val,
input mm_iu_ierat_pt_fault,
input mm_iu_ierat_lrat_miss,
input mm_iu_ierat_tlb_inelig,
input mm_iu_tlb_multihit_err,
input mm_iu_tlb_par_err,
input mm_iu_lru_par_err,
input mm_iu_tlb_miss,
input mm_iu_reload_hit,
input ic_cp_nonspec_hit,
output [0:5] cp_mm_except_taken,
// completion empty
output cp_rn_empty,
output cp_async_block,
// Power
inout vdd,
inout gnd);
// Latches
wire [1:`ITAG_SIZE_ENC-1] iu6_i0_itag_q;
wire [1:`ITAG_SIZE_ENC-1] iu6_i1_itag_q;
wire [0:`ITAG_SIZE_ENC-1] cp1_i0_itag_q;
wire [0:`ITAG_SIZE_ENC-1] cp0_i0_itag;
wire [0:`CPL_Q_DEPTH-1] cp1_i0_ptr_q;
wire [0:`CPL_Q_DEPTH-1] cp0_i0_ptr;
wire [0:`ITAG_SIZE_ENC-1] cp1_i1_itag_q;
wire [0:`ITAG_SIZE_ENC-1] cp0_i1_itag;
wire [0:`CPL_Q_DEPTH-1] cp1_i1_ptr_q;
wire [0:`CPL_Q_DEPTH-1] cp0_i1_ptr;
wire [0:`ITAG_SIZE_ENC-1] cp2_i0_itag_q;
wire [0:`ITAG_SIZE_ENC-1] cp2_i1_itag_q;
wire cp2_async_int_val_q;
wire cp1_async_int_val;
wire [0:31] cp2_async_int_q;
wire [0:31] cp1_async_int;
wire cp2_i0_complete_q;
wire cp1_i0_complete;
wire cp2_i1_complete_q;
wire cp1_i1_complete;
wire cp2_i0_np1_flush_q;
wire cp1_i0_np1_flush;
wire cp2_i1_np1_flush_q;
wire cp1_i1_np1_flush;
wire cp2_i0_n_np1_flush_q;
wire cp1_i0_n_np1_flush;
wire cp2_i1_n_np1_flush_q;
wire cp1_i1_n_np1_flush;
wire cp2_i0_bp_pred_q;
wire cp1_i0_bp_pred;
wire cp2_i1_bp_pred_q;
wire cp1_i1_bp_pred;
wire cp2_i0_br_pred_q;
wire cp1_i0_br_pred;
wire cp2_i1_br_pred_q;
wire cp1_i1_br_pred;
wire cp2_i0_br_miss_q;
wire cp1_i0_br_miss;
wire cp2_i1_br_miss_q;
wire cp1_i1_br_miss;
wire cp2_i0_flush2ucode_q;
wire cp1_i0_flush2ucode;
wire cp2_i0_flush2ucode_type_q;
wire cp1_i0_flush2ucode_type;
wire cp2_i1_flush2ucode_q;
wire cp1_i1_flush2ucode;
wire cp2_i1_flush2ucode_type_q;
wire cp1_i1_flush2ucode_type;
wire [62-`EFF_IFAR_ARCH:61] cp2_i_bta_q;
wire [62-`EFF_IFAR_ARCH:61] cp1_i_bta;
wire cp2_i0_iu_excvec_val_q;
wire cp1_i0_iu_excvec_val;
wire [0:3] cp2_i0_iu_excvec_q;
reg [0:3] cp1_i0_iu_excvec;
wire cp2_i1_iu_excvec_val_q;
wire cp1_i1_iu_excvec_val;
wire [0:3] cp2_i1_iu_excvec_q;
reg [0:3] cp1_i1_iu_excvec;
wire cp2_i0_lq_excvec_val_q;
wire cp1_i0_lq_excvec_val;
wire [0:5] cp2_i0_lq_excvec_q;
reg [0:5] cp1_i0_lq_excvec;
wire cp2_i1_lq_excvec_val_q;
wire cp1_i1_lq_excvec_val;
wire [0:5] cp2_i1_lq_excvec_q;
reg [0:5] cp1_i1_lq_excvec;
wire cp2_i0_xu_excvec_val_q;
wire cp1_i0_xu_excvec_val;
wire [0:4] cp2_i0_xu_excvec_q;
reg [0:4] cp1_i0_xu_excvec;
wire cp2_i1_xu_excvec_val_q;
wire cp1_i1_xu_excvec_val;
wire [0:4] cp2_i1_xu_excvec_q;
reg [0:4] cp1_i1_xu_excvec;
wire cp2_i0_axu_excvec_val_q;
wire cp1_i0_axu_excvec_val;
wire [0:3] cp2_i0_axu_excvec_q;
reg [0:3] cp1_i0_axu_excvec;
wire cp2_i1_axu_excvec_val_q;
wire cp1_i1_axu_excvec_val;
wire [0:3] cp2_i1_axu_excvec_q;
reg [0:3] cp1_i1_axu_excvec;
wire cp2_i0_db_val_q;
wire cp1_i0_db_val;
wire [0:18] cp2_i0_db_events_q;
reg [0:18] cp1_i0_db_events;
wire cp2_i1_db_val_q;
wire cp1_i1_db_val;
wire [0:18] cp2_i1_db_events_q;
reg [0:18] cp1_i1_db_events;
wire [0:3] cp2_i0_perf_events_q;
reg [0:3] cp1_i0_perf_events;
wire [0:3] cp2_i1_perf_events_q;
reg [0:3] cp1_i1_perf_events;
wire [0:`CPL_Q_DEPTH-1] cp1_executed_q;
wire [0:`CPL_Q_DEPTH-1] cp0_executed;
wire [0:`CPL_Q_DEPTH-1] cp1_dispatched_q;
wire [0:`CPL_Q_DEPTH-1] cp0_dispatched;
wire [0:`CPL_Q_DEPTH-1] cp1_n_flush_q;
wire [0:`CPL_Q_DEPTH-1] cp0_n_flush;
wire [0:`CPL_Q_DEPTH-1] cp1_np1_flush_q;
wire [0:`CPL_Q_DEPTH-1] cp0_np1_flush;
wire [0:`CPL_Q_DEPTH-1] cp1_n_np1_flush_q;
wire [0:`CPL_Q_DEPTH-1] cp0_n_np1_flush;
wire [0:`CPL_Q_DEPTH-1] cp1_flush2ucode_q;
wire [0:`CPL_Q_DEPTH-1] cp0_flush2ucode;
wire [0:`CPL_Q_DEPTH-1] cp1_flush2ucode_type_q;
wire [0:`CPL_Q_DEPTH-1] cp0_flush2ucode_type;
wire [0:`CPL_Q_DEPTH-1] cp1_recirc_vld_q;
wire [0:`CPL_Q_DEPTH-1] cp0_recirc_vld;
wire [0:3] cp1_perf_events_q[0:`CPL_Q_DEPTH-1];
wire [0:3] cp0_perf_events[0:`CPL_Q_DEPTH-1];
wire [0:`CPL_Q_DEPTH-1] cp1_iu_excvec_val_q;
wire [0:`CPL_Q_DEPTH-1] cp0_iu_excvec_val;
wire [0:3] cp1_iu_excvec_q[0:`CPL_Q_DEPTH-1];
wire [0:3] cp0_iu_excvec[0:`CPL_Q_DEPTH-1];
wire [0:`CPL_Q_DEPTH-1] cp1_lq_excvec_val_q;
wire [0:`CPL_Q_DEPTH-1] cp0_lq_excvec_val;
wire [0:5] cp1_lq_excvec_q[0:`CPL_Q_DEPTH-1];
wire [0:5] cp0_lq_excvec[0:`CPL_Q_DEPTH-1];
wire [0:`CPL_Q_DEPTH-1] cp1_xu_excvec_val_q;
wire [0:`CPL_Q_DEPTH-1] cp0_xu_excvec_val;
wire [0:4] cp1_xu_excvec_q[0:`CPL_Q_DEPTH-1];
wire [0:4] cp0_xu_excvec[0:`CPL_Q_DEPTH-1];
wire [0:`CPL_Q_DEPTH-1] cp1_axu_excvec_val_q;
wire [0:`CPL_Q_DEPTH-1] cp0_axu_excvec_val;
wire [0:3] cp1_axu_excvec_q[0:`CPL_Q_DEPTH-1];
wire [0:3] cp0_axu_excvec[0:`CPL_Q_DEPTH-1];
wire [0:18] cp1_db_events_q[0:`CPL_Q_DEPTH-1];
wire [0:18] cp0_db_events[0:`CPL_Q_DEPTH-1];
wire [0:`CPL_Q_DEPTH-1] cp1_db_IAC_IVC_event;
wire [0:`CPL_Q_DEPTH-1] cp1_async_block_q;
wire [0:`CPL_Q_DEPTH-1] cp0_async_block;
wire [0:`CPL_Q_DEPTH-1] cp1_is_br_q;
wire [0:`CPL_Q_DEPTH-1] cp0_is_br;
wire [0:`CPL_Q_DEPTH-1] cp1_br_add_chk_q;
wire [0:`CPL_Q_DEPTH-1] cp0_br_add_chk;
wire [0:`CPL_Q_DEPTH-1] cp1_bp_pred_q;
wire [0:`CPL_Q_DEPTH-1] cp0_bp_pred;
wire [0:`CPL_Q_DEPTH-1] cp1_br_pred_q;
wire [0:`CPL_Q_DEPTH-1] cp0_br_pred;
wire [0:`CPL_Q_DEPTH-1] cp1_br_miss_q;
wire [0:`CPL_Q_DEPTH-1] cp0_br_miss;
wire cp0_br_bta_act;
wire [62-`EFF_IFAR_ARCH:61] cp1_br_bta_q;
wire [62-`EFF_IFAR_ARCH:61] cp0_br_bta;
reg [62-`EFF_IFAR_ARCH:61] cp0_br_bta_tmp;
wire cp1_br_bta_v_q;
reg cp0_br_bta_v;
wire [0:`ITAG_SIZE_ENC-1] cp1_br_bta_itag_q;
wire [0:`ITAG_SIZE_ENC-1] cp0_br_bta_itag;
reg [0:`ITAG_SIZE_ENC-1] cp0_br_bta_itag_tmp;
wire iu6_i0_dispatched_d; // rn_cp_iu6_i0_vld
wire iu6_i1_dispatched_d; // rn_cp_iu6_i1_vld
wire iu6_i0_dispatched_q; // rn_cp_iu6_i0_vld
wire iu6_i1_dispatched_q; // rn_cp_iu6_i1_vld
wire [62-`EFF_IFAR_WIDTH:61] iu6_i0_ifar_q; // rn_cp_iu6_i0_ifar
wire [0:2] iu6_i0_ucode_q; // rn_cp_iu6_i0_ucode
wire iu6_i0_fuse_nop_q; // rn_cp_iu6_i0_fuse_nop
wire [0:2] iu6_i0_error_q; // rn_cp_iu6_i0_error
wire iu6_i0_valop_q; // rn_cp_iu6_i0_valop
wire iu6_i0_is_rfi_q; // rn_cp_iu6_i0_is_rfi
wire iu6_i0_is_rfgi_q; // rn_cp_iu6_i0_is_rfgi
wire iu6_i0_is_rfci_q; // rn_cp_iu6_i0_is_rfci
wire iu6_i0_is_rfmci_q; // rn_cp_iu6_i0_is_rfmci
wire iu6_i0_is_isync_q; // rn_cp_iu6_i0_is_isync
wire iu6_i0_is_sc_q; // rn_cp_iu6_i0_is_sc
wire iu6_i0_is_np1_flush_q; // rn_cp_iu6_i0_is_np1_flush
wire iu6_i0_is_sc_hyp_q; // rn_cp_iu6_i0_is_sc_hyp
wire iu6_i0_is_sc_ill_q; // rn_cp_iu6_i0_is_sc_ill
wire iu6_i0_is_dcr_ill_q; // rn_cp_iu6_i0_is_dcr_ill
wire iu6_i0_is_attn_q; // rn_cp_iu6_i0_is_attn
wire iu6_i0_is_ehpriv_q; // rn_cp_iu6_i0_is_ehpriv
wire iu6_i0_is_folded_q; // rn_cp_iu6_i0_is_folded
wire iu6_i0_async_block_q; // rn_cp_iu6_i0_async_block
wire iu6_i0_is_br_q; // rn_cp_iu6_i0_is_br
wire iu6_i0_br_add_chk_q; // rn_cp_iu6_i0_br_add_chk
wire iu6_i0_bp_pred_q; // rn_cp_iu6_i0_pred
wire iu6_i0_rollover_q; // rn_cp_iu6_i0_rollover
wire iu6_i0_isram_q; // rn_cp_iu6_i0_isram
wire iu6_i0_match_q; // rn_cp_iu6_i0_match
wire [62-`EFF_IFAR_WIDTH:61] iu6_i1_ifar_q; // rn_cp_iu6_i1_ifar
wire [0:2] iu6_i1_ucode_q; // rn_cp_iu6_i1_ucode
wire iu6_i1_fuse_nop_q; // rn_cp_iu6_i1_fuse_nop
wire [0:2] iu6_i1_error_q; // rn_cp_iu6_i1_error
wire iu6_i1_valop_q; // rn_cp_iu6_i1_valop
wire iu6_i1_is_rfi_q; // rn_cp_iu6_i1_is_rfi
wire iu6_i1_is_rfgi_q; // rn_cp_iu6_i1_is_rfgi
wire iu6_i1_is_rfci_q; // rn_cp_iu6_i1_is_rfci
wire iu6_i1_is_rfmci_q; // rn_cp_iu6_i1_is_rfmci
wire iu6_i1_is_isync_q; // rn_cp_iu6_i1_is_isync
wire iu6_i1_is_sc_q; // rn_cp_iu6_i1_is_sc
wire iu6_i1_is_np1_flush_q; // rn_cp_iu6_i1_is_np1_flush
wire iu6_i1_is_sc_hyp_q; // rn_cp_iu6_i1_is_sc_hyp
wire iu6_i1_is_sc_ill_q; // rn_cp_iu6_i1_is_sc_ill
wire iu6_i1_is_dcr_ill_q; // rn_cp_iu6_i1_is_dcr_ill
wire iu6_i1_is_attn_q; // rn_cp_iu6_i1_is_attn
wire iu6_i1_is_ehpriv_q; // rn_cp_iu6_i1_is_ehpriv
wire iu6_i1_is_folded_q; // rn_cp_iu6_i1_is_folded
wire iu6_i1_async_block_q; // rn_cp_iu6_i1_async_block
wire iu6_i1_is_br_q; // rn_cp_iu6_i1_is_br
wire iu6_i1_br_add_chk_q; // rn_cp_iu6_i1_br_add_chk
wire iu6_i1_bp_pred_q; // rn_cp_iu6_i1_pred
wire iu6_i1_rollover_q; // rn_cp_iu6_i1_rollover
wire iu6_i1_isram_q; // rn_cp_iu6_i1_isram
wire iu6_i1_match_q; // rn_cp_iu6_i1_match
wire iu6_uc_hold_rollover_q;
wire iu6_uc_hold_rollover_d;
wire [0:`CPL_Q_DEPTH-1] cp1_i0_dispatched_delay_q; // Added these to delay checking for completion due to completion array write for I1
wire [0:`CPL_Q_DEPTH-1] cp1_i0_dispatched_delay_d;
wire [0:`CPL_Q_DEPTH-1] cp1_i1_dispatched_delay_q; // Added these to delay checking for completion due to completion array write for I1
wire [0:`CPL_Q_DEPTH-1] cp1_i1_dispatched_delay_d;
wire iu7_i0_is_folded_q; // Added these to delay checking for completion due to completion array write for I1
wire iu7_i0_is_folded_d;
wire iu7_i1_is_folded_q; // Added these to delay checking for completion due to completion array write for I1
wire iu7_i1_is_folded_d;
wire lq0_execute_vld_d; // lq0_iu_execute_vld
wire lq0_execute_vld_q; // lq0_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] lq0_itag_q; // lq0_iu_itag
wire lq0_n_flush_q; // lq0_iu_n_flush
wire lq0_np1_flush_q; // lq0_iu_np1_flush
wire lq0_dacr_type_q; // lq0_iu_dacr_type
wire [0:3] lq0_dacrw_q; // lq0_iu_dacrw
wire [0:31] lq0_instr_q; // lq0_iu_instr
wire [64-`GPR_WIDTH:63] lq0_eff_addr_q; // lq0_iu_eff_addr
wire lq0_exception_val_d;
wire lq0_exception_val_q; // lq0_iu_exception_val
wire [0:5] lq0_exception_q; // lq0_iu_exception
wire lq0_flush2ucode_q; // lq0_iu_flush2ucode
wire lq0_flush2ucode_type_q; // lq0_iu_flush2ucode_type
wire lq0_recirc_val_q; // lq0_iu_recirc_val
wire lq1_execute_vld_d; // lq1_iu_execute_vld
wire lq1_execute_vld_q; // lq1_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] lq1_itag_q; // lq1_iu_itag
wire lq1_n_flush_q; // lq1_iu_n_flush
wire lq1_np1_flush_q; // lq1_iu_np1_flush
wire lq1_exception_val_q; // lq1_iu_exception_val
wire [0:5] lq1_exception_q; // lq1_iu_exception
wire lq1_dacr_type_q;
wire [0:3] lq1_dacrw_q;
wire [0:3] lq1_perf_events_q;
wire br_execute_vld_d; // br_iu_execute_vld
wire br_execute_vld_q; // br_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] br_itag_q; // br_iu_itag
wire br_taken_q; // br_iu_taken
wire br_redirect_q; // br_iu_redirect
wire [62-`EFF_IFAR_ARCH:61] br_bta_q; // br_iu_bta
wire [62-`EFF_IFAR_ARCH:61] br_bta_d;
wire [0:3] br_perf_events_q;
wire xu_execute_vld_d; // xu_iu_execute_vld
wire xu_execute_vld_q; // xu_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] xu_itag_q; // xu_iu_itag
wire xu_n_flush_q; // xu_iu_n_flush
wire xu_np1_flush_q; // xu_iu_np1_flush
wire xu_flush2ucode_q; // xu_iu_flush2ucode
wire xu_exception_val_q; // xu_iu_exception_val
wire xu_exception_val_d;
wire [0:4] xu_exception_q; // xu_iu_exception
wire xu_mtiar_q; // xu_iu_mtiar
wire [62-`EFF_IFAR_ARCH:61] xu_bta_q; // xu_iu_bta
wire [0:3] xu_perf_events_q;
wire xu1_execute_vld_d; // xu1_iu_execute_vld
wire xu1_execute_vld_q; // xu1_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] xu1_itag_q; // xu1_iu_itag
wire axu0_execute_vld_d; // axu0_iu_execute_vld
wire axu0_execute_vld_q; // axu0_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] axu0_itag_q; // axu0_iu_itag
wire axu0_n_flush_q; // axu0_iu_n_flush
wire axu0_np1_flush_q; // axu0_iu_np1_flush
wire axu0_n_np1_flush_q; // axu0_iu_n_np1_flush
wire axu0_flush2ucode_q; // axu0_iu_flush2ucode
wire axu0_flush2ucode_type_q; // axu0_iu_flush2ucode_type
wire axu0_exception_val_q; // axu0_iu_exception_val
wire [0:3] axu0_exception_q; // axu0_iu_exception
wire [0:3] axu0_perf_events_q;
wire axu1_execute_vld_d; // axu1_iu_execute_vld
wire axu1_execute_vld_q; // axu1_iu_execute_vld
wire [0:`ITAG_SIZE_ENC-1] axu1_itag_q; // axu1_iu_itag
wire axu1_n_flush_q; // axu1_iu_n_flush
wire axu1_np1_flush_q; // axu1_iu_np1_flush
wire axu1_n_np1_flush_q; // axu1_iu_n_np1_flush
wire axu1_flush2ucode_q; // axu1_iu_flush2ucode
wire axu1_flush2ucode_type_q; // axu1_iu_flush2ucode_type
wire axu1_exception_val_q; // axu1_iu_exception_val
wire [0:3] axu1_exception_q; // axu1_iu_exception
wire [0:3] axu1_perf_events_q;
wire iu_xu_cp3_rfi_q;
wire iu_xu_cp2_rfi_d;
wire iu_xu_cp3_rfgi_q;
wire iu_xu_cp2_rfgi_d;
wire iu_xu_cp3_rfci_q;
wire iu_xu_cp2_rfci_d;
wire iu_xu_cp3_rfmci_q;
wire iu_xu_cp2_rfmci_d;
wire iu_xu_cp4_rfi_q;
wire iu_xu_cp4_rfgi_q;
wire iu_xu_cp4_rfci_q;
wire iu_xu_cp4_rfmci_q;
wire cp3_ld_save_q;
wire cp3_ld_save_d;
wire cp3_st_save_q;
wire cp3_st_save_d;
wire cp3_fp_save_q;
wire cp3_fp_save_d;
wire cp3_ap_save_q;
wire cp3_ap_save_d;
wire cp3_spv_save_q;
wire cp3_spv_save_d;
wire cp3_epid_save_q;
wire cp3_epid_save_d;
wire cp3_async_hold_q;
wire cp3_async_hold_d;
wire cp2_async_hold;
wire cp2_flush_q;
wire cp1_flush;
wire cp3_flush_q; // cp3_flush_q
wire cp3_flush_d;
wire cp4_flush_q; // cp4_flush_q used to gate off incoming executes
wire cp3_rfi_q; // cp3_rfi_q
wire cp2_rfi;
wire cp3_attn_q; // cp3_attn_q
wire cp2_attn;
wire cp3_sc_q; // cp3_sc_q
wire cp2_sc;
wire cp3_icmp_block_q; // cp2_icmp_block
wire cp2_icmp_block;
wire cp3_async_int_val_q;
wire [0:31] cp3_async_int_q;
wire cp3_iu_excvec_val_q;
wire cp2_iu_excvec_val;
wire [0:3] cp3_iu_excvec_q;
wire [0:3] cp2_iu_excvec;
wire cp3_lq_excvec_val_q;
wire cp2_lq_excvec_val;
wire [0:5] cp3_lq_excvec_q;
wire [0:5] cp2_lq_excvec;
wire cp3_xu_excvec_val_q;
wire cp2_xu_excvec_val;
wire [0:4] cp3_xu_excvec_q;
wire [0:4] cp2_xu_excvec;
wire cp3_axu_excvec_val_q;
wire cp2_axu_excvec_val;
wire [0:3] cp3_axu_excvec_q;
wire [0:3] cp2_axu_excvec;
wire cp3_db_val_q;
wire cp2_db_val;
wire [0:18] cp3_db_events_q;
wire [0:18] cp2_db_events;
wire cp3_ld_q;
wire cp2_ld;
wire cp3_st_q;
wire cp2_st;
wire cp3_fp_q;
wire cp2_fp;
wire cp3_ap_q;
wire cp2_ap;
wire cp3_spv_q;
wire cp2_spv;
wire cp3_epid_q;
wire cp2_epid;
wire [43:61] cp3_ifar_q;
wire [43:61] cp2_ifar;
wire cp3_np1_flush_q;
wire cp2_np1_flush;
wire cp3_ucode_q;
wire cp3_preissue_q;
wire cp2_ucode;
wire cp2_preissue;
wire cp3_nia_act;
wire [62-`EFF_IFAR_ARCH:61] cp3_nia_q;
wire [62-`EFF_IFAR_ARCH:61] cp2_nia;
wire [62-`EFF_IFAR_ARCH:61] nia_mask;
wire cp3_flush2ucode_q;
wire cp2_flush2ucode;
wire cp3_flush2ucode_type_q;
wire cp2_flush2ucode_type;
wire cp3_flush_nonspec_q;
wire cp2_flush_nonspec;
wire cp3_mispredict_q;
wire cp2_mispredict;
wire cp4_rfi_q;
wire cp3_rfi;
wire cp5_rfi_q;
wire cp6_rfi_q;
wire cp7_rfi_q;
wire cp8_rfi_q;
wire cp4_excvec_val_q;
wire cp4_excvec_val;
wire cp3_excvec_val;
wire cp4_dp_cp_async_flush_q;
wire cp3_dp_cp_async_flush;
wire cp4_dp_cp_async_bus_snoop_flush_q;
wire cp3_dp_cp_async_bus_snoop_flush;
wire cp4_async_np1_q;
wire cp3_async_np1;
wire cp3_async_n;
wire cp4_async_n_q;
wire cp3_mm_iu_exception;
wire cp4_pc_stop_q;
wire cp3_pc_stop;
wire pc_stop_hold_q;
wire pc_stop_hold_d;
wire cp4_mc_int_q;
wire cp3_mc_int;
wire cp4_g_int_q;
wire cp3_g_int;
wire cp4_c_int_q;
wire cp3_c_int;
wire cp4_dbell_int_q;
wire cp3_dbell_int;
wire cp4_cdbell_int_q;
wire cp3_cdbell_int;
wire cp4_gdbell_int_q;
wire cp3_gdbell_int;
wire cp4_gcdbell_int_q;
wire cp3_gcdbell_int;
wire cp4_gmcdbell_int_q;
wire cp3_gmcdbell_int;
wire cp4_dbsr_update_q;
wire cp3_dbsr_update;
wire cp4_eheir_update_q;
wire cp3_eheir_update;
wire [0:18] cp4_dbsr_q;
wire [0:18] cp3_dbsr;
wire cp4_esr_update_q;
wire cp3_esr_update;
wire [0:16] cp4_exc_esr_q;
wire [0:16] cp3_exc_esr;
wire [0:14] cp4_exc_mcsr_q;
wire [0:14] cp3_exc_mcsr;
wire cp4_asyn_irpt_needed_q;
wire cp4_asyn_irpt_needed_d;
wire cp4_asyn_icmp_needed_q;
wire cp4_asyn_icmp_needed_d;
wire [62-`EFF_IFAR_ARCH:61] cp4_exc_nia_q;
wire [62-`EFF_IFAR_ARCH:61] cp3_exc_nia;
wire cp4_mchk_disabled_q;
wire cp3_mchk_disabled;
wire cp4_dear_update_q;
wire cp3_dear_update;
wire [0:1] flush_hold_q;
wire [0:1] flush_hold_d;
wire flush_hold;
wire pc_iu_init_reset_q;
wire dp_cp_async_flush_q;
wire dp_cp_async_flush_d;
wire dp_cp_async_bus_snoop_flush_q;
wire dp_cp_async_bus_snoop_flush_d;
wire np1_async_flush_q;
wire np1_async_flush_d;
wire msr_de_q;
wire msr_pr_q;
wire msr_cm_q;
wire msr_cm_noact_q;
wire msr_gs_q;
wire msr_me_q;
wire dbcr0_edm_q;
wire dbcr0_idm_q;
wire dbcr0_icmp_q;
wire dbcr0_brt_q;
wire dbcr0_irpt_q;
wire dbcr0_trap_q;
wire iac1_en_q;
wire iac2_en_q;
wire iac3_en_q;
wire iac4_en_q;
wire [0:1] dbcr0_dac1_q;
wire [0:1] dbcr0_dac2_q;
wire [0:1] dbcr0_dac3_q;
wire [0:1] dbcr0_dac4_q;
wire dbcr0_ret_q;
wire dbcr1_iac12m_q;
wire dbcr1_iac34m_q;
wire dbcr3_ivc_q;
wire epcr_extgs_q;
wire epcr_dtlbgs_q;
wire epcr_itlbgs_q;
wire epcr_dsigs_q;
wire epcr_isigs_q;
wire epcr_duvd_q;
wire epcr_icm_q;
wire epcr_gicm_q;
wire ccr2_ucode_dis_q;
wire ccr2_mmu_mode_q;
wire xu_iu_xucr4_mmu_mchk_q;
wire pc_iu_ram_active_q;
wire pc_iu_ram_flush_thread_q;
wire xu_iu_msrovride_enab_q;
wire pc_iu_stop_q;
wire pc_iu_step_q;
wire [0:15] spr_perf_mux_ctrls_q;
wire [0:2] pc_iu_dbg_action_q;
wire xu_iu_single_instr_q;
wire spr_single_issue_q;
wire [64-`GPR_WIDTH:51] spr_ivpr_q;
wire [64-`GPR_WIDTH:51] spr_givpr_q;
wire [62-`EFF_IFAR_ARCH:61] spr_iac1_q;
wire [62-`EFF_IFAR_ARCH:61] spr_iac2_q;
wire [62-`EFF_IFAR_ARCH:61] spr_iac3_q;
wire [62-`EFF_IFAR_ARCH:61] spr_iac4_q;
wire iu_pc_step_done_q;
wire iu_pc_step_done_d;
wire uncond_dbg_event_q;
wire external_mchk_q;
wire ext_interrupt_q;
wire dec_interrupt_q;
wire udec_interrupt_q;
wire perf_interrupt_q;
wire fit_interrupt_q;
wire crit_interrupt_q;
wire wdog_interrupt_q;
wire gwdog_interrupt_q;
wire gfit_interrupt_q;
wire gdec_interrupt_q;
wire dbell_interrupt_q;
wire cdbell_interrupt_q;
wire gdbell_interrupt_q;
wire gcdbell_interrupt_q;
wire gmcdbell_interrupt_q;
wire dbsr_interrupt_q;
wire fex_interrupt_q;
wire [0:2] async_delay_cnt_q;
wire [0:2] async_delay_cnt_d;
wire iu_lq_recirc_val_q;
wire iu_lq_recirc_val_d;
wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_q;
wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_d;
wire [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar_q;
wire attn_hold_q;
wire attn_hold_d;
wire [0:1] flush_delay_q;
wire [0:1] flush_delay_d;
wire iu_nonspec_q;
wire iu_nonspec_d;
wire nonspec_release;
wire ierat_pt_fault_q;
wire ierat_pt_fault_d;
wire ierat_lrat_miss_q;
wire ierat_lrat_miss_d;
wire ierat_tlb_inelig_q;
wire ierat_tlb_inelig_d;
wire tlb_multihit_err_q;
wire tlb_multihit_err_d;
wire tlb_par_err_q;
wire tlb_par_err_d;
wire lru_par_err_q;
wire lru_par_err_d;
wire tlb_miss_q;
wire tlb_miss_d;
wire reload_hit_d;
wire reload_hit_q;
wire nonspec_hit_d;
wire nonspec_hit_q;
wire [0:5] cp_mm_except_taken_d;
wire [0:5] cp_mm_except_taken_q;
wire eheir_val_d;
wire eheir_val_q;
wire [0:3] event_bus_out_d;
wire [0:3] event_bus_out_q;
// External Debug
wire ext_dbg_stop_d;
wire ext_dbg_stop_q;
wire ext_dbg_stop_other_d;
wire ext_dbg_stop_other_q;
wire ext_dbg_act_err_d;
wire ext_dbg_act_err_q;
wire ext_dbg_act_ext_d;
wire ext_dbg_act_ext_q;
wire dbg_int_en_d;
wire dbg_int_en_q;
wire dbg_flush_en;
wire dbg_event_en_d;
wire dbg_event_en_q;
// Scanchains
parameter iu6_i0_itag_offset = 0;
parameter iu6_i1_itag_offset = iu6_i0_itag_offset + `ITAG_SIZE_ENC-1;
parameter cp1_i0_itag_offset = iu6_i1_itag_offset + `ITAG_SIZE_ENC-1;
parameter cp1_i0_ptr_offset = cp1_i0_itag_offset + `ITAG_SIZE_ENC;
parameter cp1_i1_itag_offset = cp1_i0_ptr_offset + `CPL_Q_DEPTH;
parameter cp1_i1_ptr_offset = cp1_i1_itag_offset + `ITAG_SIZE_ENC;
parameter cp2_i0_itag_offset = cp1_i1_ptr_offset + `CPL_Q_DEPTH;
parameter cp2_i1_itag_offset = cp2_i0_itag_offset + `ITAG_SIZE_ENC;
parameter cp2_async_int_val_offset = cp2_i1_itag_offset + `ITAG_SIZE_ENC;
parameter cp2_async_int_offset = cp2_async_int_val_offset + 1;
parameter cp2_i0_completed_offset = cp2_async_int_offset + 32;
parameter cp2_i1_completed_offset = cp2_i0_completed_offset + 1;
parameter cp2_i0_np1_flush_offset = cp2_i1_completed_offset + 1;
parameter cp2_i1_np1_flush_offset = cp2_i0_np1_flush_offset + 1;
parameter cp2_i0_n_np1_flush_offset = cp2_i1_np1_flush_offset + 1;
parameter cp2_i1_n_np1_flush_offset = cp2_i0_n_np1_flush_offset + 1;
parameter cp2_i0_bp_pred_offset = cp2_i1_n_np1_flush_offset + 1;
parameter cp2_i1_bp_pred_offset = cp2_i0_bp_pred_offset + 1;
parameter cp2_i0_br_pred_offset = cp2_i1_bp_pred_offset + 1;
parameter cp2_i1_br_pred_offset = cp2_i0_br_pred_offset + 1;
parameter cp2_i0_br_miss_offset = cp2_i1_br_pred_offset + 1;
parameter cp2_i1_br_miss_offset = cp2_i0_br_miss_offset + 1;
parameter cp2_i0_db_val_offset = cp2_i1_br_miss_offset + 1;
parameter cp2_i0_db_events_offset = cp2_i0_db_val_offset + 1;
parameter cp2_i1_db_val_offset = cp2_i0_db_events_offset + 19;
parameter cp2_i1_db_events_offset = cp2_i1_db_val_offset + 1;
parameter cp2_i0_perf_events_offset = cp2_i1_db_events_offset + 19;
parameter cp2_i1_perf_events_offset = cp2_i0_perf_events_offset + 4;
parameter cp2_i0_flush2ucode_offset = cp2_i1_perf_events_offset + 4;
parameter cp2_i0_flush2ucode_type_offset = cp2_i0_flush2ucode_offset + 1;
parameter cp2_i1_flush2ucode_offset = cp2_i0_flush2ucode_type_offset + 1;
parameter cp2_i1_flush2ucode_type_offset = cp2_i1_flush2ucode_offset + 1;
parameter cp2_i_bta_offset = cp2_i1_flush2ucode_type_offset + 1;
parameter cp2_i0_iu_excvec_val_offset = cp2_i_bta_offset + `EFF_IFAR_ARCH;
parameter cp2_i0_iu_excvec_offset = cp2_i0_iu_excvec_val_offset + 1;
parameter cp2_i1_iu_excvec_val_offset = cp2_i0_iu_excvec_offset + 4;
parameter cp2_i1_iu_excvec_offset = cp2_i1_iu_excvec_val_offset + 1;
parameter cp2_i0_lq_excvec_val_offset = cp2_i1_iu_excvec_offset + 4;
parameter cp2_i0_lq_excvec_offset = cp2_i0_lq_excvec_val_offset + 1;
parameter cp2_i1_lq_excvec_val_offset = cp2_i0_lq_excvec_offset + 6;
parameter cp2_i1_lq_excvec_offset = cp2_i1_lq_excvec_val_offset + 1;
parameter cp2_i0_xu_excvec_val_offset = cp2_i1_lq_excvec_offset + 6;
parameter cp2_i0_xu_excvec_offset = cp2_i0_xu_excvec_val_offset + 1;
parameter cp2_i1_xu_excvec_val_offset = cp2_i0_xu_excvec_offset + 5;
parameter cp2_i1_xu_excvec_offset = cp2_i1_xu_excvec_val_offset + 1;
parameter cp2_i0_axu_excvec_val_offset = cp2_i1_xu_excvec_offset + 5;
parameter cp2_i0_axu_excvec_offset = cp2_i0_axu_excvec_val_offset + 1;
parameter cp2_i1_axu_excvec_val_offset = cp2_i0_axu_excvec_offset + 4;
parameter cp2_i1_axu_excvec_offset = cp2_i1_axu_excvec_val_offset + 1;
parameter cp1_executed_offset = cp2_i1_axu_excvec_offset + 4;
parameter cp1_dispatched_offset = cp1_executed_offset + `CPL_Q_DEPTH;
parameter cp1_n_flush_offset = cp1_dispatched_offset + `CPL_Q_DEPTH;
parameter cp1_np1_flush_offset = cp1_n_flush_offset + `CPL_Q_DEPTH;
parameter cp1_n_np1_flush_offset = cp1_np1_flush_offset + `CPL_Q_DEPTH;
parameter cp1_flush2ucode_offset = cp1_n_np1_flush_offset + `CPL_Q_DEPTH;
parameter cp1_flush2ucode_type_offset = cp1_flush2ucode_offset + `CPL_Q_DEPTH;
parameter cp1_perf_events_offset = cp1_flush2ucode_type_offset + `CPL_Q_DEPTH;
parameter cp1_iu_excvec_val_offset = cp1_perf_events_offset + 4 * `CPL_Q_DEPTH;
parameter cp1_iu_excvec_offset = cp1_iu_excvec_val_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_lq_excvec_val_offset = cp1_iu_excvec_offset + 4 * `CPL_Q_DEPTH;
parameter cp1_lq_excvec_offset = cp1_lq_excvec_val_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_xu_excvec_val_offset = cp1_lq_excvec_offset + 6 * `CPL_Q_DEPTH;
parameter cp1_xu_excvec_offset = cp1_xu_excvec_val_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_axu_excvec_val_offset = cp1_xu_excvec_offset + 5 * `CPL_Q_DEPTH;
parameter cp1_axu_excvec_offset = cp1_axu_excvec_val_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_db_events_offset = cp1_axu_excvec_offset + 4 * `CPL_Q_DEPTH;
parameter cp1_recirc_vld_offset = cp1_db_events_offset + 19 * `CPL_Q_DEPTH;
parameter cp1_async_block_offset = cp1_recirc_vld_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_is_br_offset = cp1_async_block_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_br_add_chk_offset = cp1_is_br_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_bp_pred_offset = cp1_br_add_chk_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_br_pred_offset = cp1_bp_pred_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_br_miss_offset = cp1_br_pred_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_br_bta_offset = cp1_br_miss_offset + 1 * `CPL_Q_DEPTH;
parameter cp1_br_bta_v_offset = cp1_br_bta_offset + `EFF_IFAR_ARCH;
parameter cp1_br_bta_itag_offset = cp1_br_bta_v_offset + 1;
parameter cp0_i0_dispatched_offset = cp1_br_bta_itag_offset + `ITAG_SIZE_ENC;
parameter cp0_i1_dispatched_offset = cp0_i0_dispatched_offset + 1;
parameter cp0_i0_ifar_offset = cp0_i1_dispatched_offset + 1;
parameter cp0_i0_ucode_offset = cp0_i0_ifar_offset + `EFF_IFAR_WIDTH;
parameter cp0_i0_fuse_nop_offset = cp0_i0_ucode_offset + 3;
parameter cp0_i0_error_offset = cp0_i0_fuse_nop_offset + 1;
parameter cp0_i0_valop_offset = cp0_i0_error_offset + 3;
parameter cp0_i0_is_rfi_offset = cp0_i0_valop_offset + 1;
parameter cp0_i0_is_rfgi_offset = cp0_i0_is_rfi_offset + 1;
parameter cp0_i0_is_rfci_offset = cp0_i0_is_rfgi_offset + 1;
parameter cp0_i0_is_rfmci_offset = cp0_i0_is_rfci_offset + 1;
parameter cp0_i0_is_isync_offset = cp0_i0_is_rfmci_offset + 1;
parameter cp0_i0_is_sc_offset = cp0_i0_is_isync_offset + 1;
parameter cp0_i0_is_np1_flush_offset = cp0_i0_is_sc_offset + 1;
parameter cp0_i0_is_sc_hyp_offset = cp0_i0_is_np1_flush_offset + 1;
parameter cp0_i0_is_sc_ill_offset = cp0_i0_is_sc_hyp_offset + 1;
parameter cp0_i0_is_dcr_ill_offset = cp0_i0_is_sc_ill_offset + 1;
parameter cp0_i0_is_attn_offset = cp0_i0_is_dcr_ill_offset + 1;
parameter cp0_i0_is_ehpriv_offset = cp0_i0_is_attn_offset + 1;
parameter cp0_i0_is_folded_offset = cp0_i0_is_ehpriv_offset + 1;
parameter cp0_i0_async_block_offset = cp0_i0_is_folded_offset + 1;
parameter cp0_i0_is_br_offset = cp0_i0_async_block_offset + 1;
parameter cp0_i0_br_add_chk_offset = cp0_i0_is_br_offset + 1;
parameter cp0_i0_bp_pred_offset = cp0_i0_br_add_chk_offset + 1;
parameter cp0_i0_rollover_offset = cp0_i0_bp_pred_offset + 1;
parameter cp0_i0_isram_offset = cp0_i0_rollover_offset + 1;
parameter cp0_i0_match_offset = cp0_i0_isram_offset + 1;
parameter cp0_i1_ifar_offset = cp0_i0_match_offset + 1;
parameter cp0_i1_ucode_offset = cp0_i1_ifar_offset + `EFF_IFAR_WIDTH;
parameter cp0_i1_fuse_nop_offset = cp0_i1_ucode_offset + 3;
parameter cp0_i1_error_offset = cp0_i1_fuse_nop_offset + 1;
parameter cp0_i1_valop_offset = cp0_i1_error_offset + 3;
parameter cp0_i1_is_rfi_offset = cp0_i1_valop_offset + 1;
parameter cp0_i1_is_rfgi_offset = cp0_i1_is_rfi_offset + 1;
parameter cp0_i1_is_rfci_offset = cp0_i1_is_rfgi_offset + 1;
parameter cp0_i1_is_rfmci_offset = cp0_i1_is_rfci_offset + 1;
parameter cp0_i1_is_isync_offset = cp0_i1_is_rfmci_offset + 1;
parameter cp0_i1_is_sc_offset = cp0_i1_is_isync_offset + 1;
parameter cp0_i1_is_np1_flush_offset = cp0_i1_is_sc_offset + 1;
parameter cp0_i1_is_sc_hyp_offset = cp0_i1_is_np1_flush_offset + 1;
parameter cp0_i1_is_sc_ill_offset = cp0_i1_is_sc_hyp_offset + 1;
parameter cp0_i1_is_dcr_ill_offset = cp0_i1_is_sc_ill_offset + 1;
parameter cp0_i1_is_attn_offset = cp0_i1_is_dcr_ill_offset + 1;
parameter cp0_i1_is_ehpriv_offset = cp0_i1_is_attn_offset + 1;
parameter cp0_i1_is_folded_offset = cp0_i1_is_ehpriv_offset + 1;
parameter cp0_i1_async_block_offset = cp0_i1_is_folded_offset + 1;
parameter cp0_i1_is_br_offset = cp0_i1_async_block_offset + 1;
parameter cp0_i1_br_add_chk_offset = cp0_i1_is_br_offset + 1;
parameter cp0_i1_bp_pred_offset = cp0_i1_br_add_chk_offset + 1;
parameter cp0_i1_rollover_offset = cp0_i1_bp_pred_offset + 1;
parameter cp0_i1_isram_offset = cp0_i1_rollover_offset + 1;
parameter cp0_i1_match_offset = cp0_i1_isram_offset + 1;
parameter cp0_uc_hold_rollover_offset = cp0_i1_match_offset + 1;
parameter lq0_execute_vld_offset = cp0_uc_hold_rollover_offset + 1;
parameter lq0_itag_offset = lq0_execute_vld_offset + 1;
parameter lq0_n_flush_offset = lq0_itag_offset + `ITAG_SIZE_ENC;
parameter lq0_np1_flush_offset = lq0_n_flush_offset + 1;
parameter lq0_dacr_type_offset = lq0_np1_flush_offset + 1;
parameter lq0_dacrw_offset = lq0_dacr_type_offset + 1;
parameter lq0_instr_offset = lq0_dacrw_offset + 4;
parameter lq0_eff_addr_offset = lq0_instr_offset + 32;
parameter lq0_exception_val_offset = lq0_eff_addr_offset + `GPR_WIDTH;
parameter lq0_exception_offset = lq0_exception_val_offset + 1;
parameter lq0_flush2ucode_offset = lq0_exception_offset + 6;
parameter lq0_flush2ucode_type_offset = lq0_flush2ucode_offset + 1;
parameter lq0_recirc_val_offset = lq0_flush2ucode_type_offset + 1;
parameter lq1_execute_vld_offset = lq0_recirc_val_offset + 1;
parameter lq1_itag_offset = lq1_execute_vld_offset + 1;
parameter lq1_n_flush_offset = lq1_itag_offset + `ITAG_SIZE_ENC;
parameter lq1_np1_flush_offset = lq1_n_flush_offset + 1;
parameter lq1_exception_val_offset = lq1_np1_flush_offset + 1;
parameter lq1_exception_offset = lq1_exception_val_offset + 1;
parameter lq1_dacr_type_offset = lq1_exception_offset + 6;
parameter lq1_dacrw_offset = lq1_dacr_type_offset + 1;
parameter lq1_perf_events_offset = lq1_dacrw_offset + 4;
parameter br_perf_events_offset = lq1_perf_events_offset + 4;
parameter axu0_perf_events_offset = br_perf_events_offset + 4;
parameter axu1_perf_events_offset = axu0_perf_events_offset + 4;
parameter br_execute_vld_offset = axu1_perf_events_offset + 4;
parameter br_itag_offset = br_execute_vld_offset + 1;
parameter br_taken_offset = br_itag_offset + `ITAG_SIZE_ENC;
parameter br_redirect_offset = br_taken_offset + 1;
parameter br_bta_offset = br_redirect_offset + 1;
parameter xu_execute_vld_offset = br_bta_offset + `EFF_IFAR_ARCH;
parameter xu_itag_offset = xu_execute_vld_offset + 1;
parameter xu_n_flush_offset = xu_itag_offset + `ITAG_SIZE_ENC;
parameter xu_np1_flush_offset = xu_n_flush_offset + 1;
parameter xu_flush2ucode_offset = xu_np1_flush_offset + 1;
parameter xu_exception_val_offset = xu_flush2ucode_offset + 1;
parameter xu_exception_offset = xu_exception_val_offset + 1;
parameter xu_mtiar_offset = xu_exception_offset + 5;
parameter xu_bta_offset = xu_mtiar_offset + 1;
parameter xu_perf_events_offset = xu_bta_offset + `EFF_IFAR_ARCH;
parameter xu1_execute_vld_offset = xu_perf_events_offset + 4;
parameter xu1_itag_offset = xu1_execute_vld_offset + 1;
parameter axu0_execute_vld_offset = xu1_itag_offset + `ITAG_SIZE_ENC;
parameter axu0_itag_offset = axu0_execute_vld_offset + 1;
parameter axu0_n_flush_offset = axu0_itag_offset + `ITAG_SIZE_ENC;
parameter axu0_np1_flush_offset = axu0_n_flush_offset + 1;
parameter axu0_n_np1_flush_offset = axu0_np1_flush_offset + 1;
parameter axu0_flush2ucode_offset = axu0_n_np1_flush_offset + 1;
parameter axu0_flush2ucode_type_offset = axu0_flush2ucode_offset + 1;
parameter axu0_exception_val_offset = axu0_flush2ucode_type_offset + 1;
parameter axu0_exception_offset = axu0_exception_val_offset + 1;
parameter axu1_execute_vld_offset = axu0_exception_offset + 4;
parameter axu1_itag_offset = axu1_execute_vld_offset + 1;
parameter axu1_n_flush_offset = axu1_itag_offset + `ITAG_SIZE_ENC;
parameter axu1_np1_flush_offset = axu1_n_flush_offset + 1;
parameter axu1_n_np1_flush_offset = axu1_np1_flush_offset + 1;
parameter axu1_flush2ucode_offset = axu1_n_np1_flush_offset + 1;
parameter axu1_flush2ucode_type_offset = axu1_flush2ucode_offset + 1;
parameter axu1_exception_val_offset = axu1_flush2ucode_type_offset + 1;
parameter axu1_exception_offset = axu1_exception_val_offset + 1;
parameter iu_xu_cp3_rfi_offset = axu1_exception_offset + 4;
parameter iu_xu_cp3_rfgi_offset = iu_xu_cp3_rfi_offset + 1;
parameter iu_xu_cp3_rfci_offset = iu_xu_cp3_rfgi_offset + 1;
parameter iu_xu_cp3_rfmci_offset = iu_xu_cp3_rfci_offset + 1;
parameter iu_xu_cp4_rfi_offset = iu_xu_cp3_rfmci_offset + 1;
parameter iu_xu_cp4_rfgi_offset = iu_xu_cp4_rfi_offset + 1;
parameter iu_xu_cp4_rfci_offset = iu_xu_cp4_rfgi_offset + 1;
parameter iu_xu_cp4_rfmci_offset = iu_xu_cp4_rfci_offset + 1;
parameter cp3_ld_save_offset = iu_xu_cp4_rfmci_offset + 1;
parameter cp3_st_save_offset = cp3_ld_save_offset + 1;
parameter cp3_fp_save_offset = cp3_st_save_offset + 1;
parameter cp3_ap_save_offset = cp3_fp_save_offset + 1;
parameter cp3_spv_save_offset = cp3_ap_save_offset + 1;
parameter cp3_epid_save_offset = cp3_spv_save_offset + 1;
parameter cp3_async_hold_offset = cp3_epid_save_offset + 1;
parameter cp2_flush_offset = cp3_async_hold_offset + 1;
parameter cp3_flush_offset = cp2_flush_offset + 1;
parameter cp4_flush_offset = cp3_flush_offset + 1;
parameter cp3_rfi_offset = cp4_flush_offset + 1;
parameter cp3_attn_offset = cp3_rfi_offset + 1;
parameter cp3_sc_offset = cp3_attn_offset + 1;
parameter cp3_icmp_block_offset = cp3_sc_offset + 1;
parameter cp3_flush2ucode_offset = cp3_icmp_block_offset + 1;
parameter cp3_flush2ucode_type_offset = cp3_flush2ucode_offset + 1;
parameter cp3_flush_nonspec_offset = cp3_flush2ucode_type_offset + 1;
parameter cp3_mispredict_offset = cp3_flush_nonspec_offset + 1;
parameter cp3_async_int_val_offset = cp3_mispredict_offset + 1;
parameter cp3_async_int_offset = cp3_async_int_val_offset + 1;
parameter cp3_iu_excvec_val_offset = cp3_async_int_offset + 32;
parameter cp3_iu_excvec_offset = cp3_iu_excvec_val_offset + 1;
parameter cp3_lq_excvec_val_offset = cp3_iu_excvec_offset + 4;
parameter cp3_lq_excvec_offset = cp3_lq_excvec_val_offset + 1;
parameter cp3_xu_excvec_val_offset = cp3_lq_excvec_offset + 6;
parameter cp3_xu_excvec_offset = cp3_xu_excvec_val_offset + 1;
parameter cp3_axu_excvec_val_offset = cp3_xu_excvec_offset + 5;
parameter cp3_axu_excvec_offset = cp3_axu_excvec_val_offset + 1;
parameter cp3_db_val_offset = cp3_axu_excvec_offset + 4;
parameter cp3_db_events_offset = cp3_db_val_offset + 1;
parameter cp3_ld_offset = cp3_db_events_offset + 19;
parameter cp3_st_offset = cp3_ld_offset + 1;
parameter cp3_fp_offset = cp3_st_offset + 1;
parameter cp3_ap_offset = cp3_fp_offset + 1;
parameter cp3_spv_offset = cp3_ap_offset + 1;
parameter cp3_epid_offset = cp3_spv_offset + 1;
parameter cp3_ifar_offset = cp3_epid_offset + 1;
parameter cp3_np1_flush_offset = cp3_ifar_offset + 19;
parameter cp3_ucode_offset = cp3_np1_flush_offset + 1;
parameter cp3_preissue_offset = cp3_ucode_offset + 1;
parameter cp3_nia_offset = cp3_preissue_offset + 1;
parameter cp4_rfi_offset = cp3_nia_offset + `EFF_IFAR_ARCH;
parameter cp5_rfi_offset = cp4_rfi_offset + 1;
parameter cp6_rfi_offset = cp5_rfi_offset + 1;
parameter cp7_rfi_offset = cp6_rfi_offset + 1;
parameter cp8_rfi_offset = cp7_rfi_offset + 1;
parameter cp4_exc_val_offset = cp8_rfi_offset + 1;
parameter flush_hold_offset = cp4_exc_val_offset + 1;
parameter cp4_dp_cp_async_flush_offset = flush_hold_offset + 2;
parameter cp4_dp_cp_async_bus_snoop_flush_offset = cp4_dp_cp_async_flush_offset + 1;
parameter cp4_async_np1_offset = cp4_dp_cp_async_bus_snoop_flush_offset + 1;
parameter cp4_async_n_offset = cp4_async_np1_offset + 1;
parameter cp4_pc_stop_offset = cp4_async_n_offset + 1;
parameter pc_stop_hold_offset = cp4_pc_stop_offset + 1;
parameter cp4_mc_int_offset = pc_stop_hold_offset + 1;
parameter cp4_mchk_disabled_offset = cp4_mc_int_offset + 1;
parameter cp4_g_int_offset = cp4_mchk_disabled_offset + 1;
parameter cp4_c_int_offset = cp4_g_int_offset + 1;
parameter cp4_dbell_int_offset = cp4_c_int_offset + 1;
parameter cp4_cdbell_int_offset = cp4_dbell_int_offset + 1;
parameter cp4_gdbell_int_offset = cp4_cdbell_int_offset + 1;
parameter cp4_gcdbell_int_offset = cp4_gdbell_int_offset + 1;
parameter cp4_gmcdbell_int_offset = cp4_gcdbell_int_offset + 1;
parameter cp4_dbsr_update_offset = cp4_gmcdbell_int_offset + 1;
parameter cp4_dbsr_offset = cp4_dbsr_update_offset + 1;
parameter cp4_eheir_update_offset = cp4_dbsr_offset + 19;
parameter cp4_esr_update_offset = cp4_eheir_update_offset + 1;
parameter cp4_exc_esr_offset = cp4_esr_update_offset + 1;
parameter cp4_exc_mcsr_offset = cp4_exc_esr_offset + 17;
parameter cp4_asyn_irpt_needed_offset = cp4_exc_mcsr_offset + 15;
parameter cp4_asyn_icmp_needed_offset = cp4_asyn_irpt_needed_offset + 1;
parameter cp4_exc_nia_offset = cp4_asyn_icmp_needed_offset + 1;
parameter cp4_dear_update_offset = cp4_exc_nia_offset + `EFF_IFAR_ARCH;
parameter cp_next_itag_offset = cp4_dear_update_offset + 1;
parameter pc_iu_init_reset_offset = cp_next_itag_offset + `ITAG_SIZE_ENC;
parameter np1_async_flush_offset = pc_iu_init_reset_offset + 1;
parameter dp_cp_async_flush_offset = np1_async_flush_offset + 1;
parameter dp_cp_async_bus_snoop_flush_offset = dp_cp_async_flush_offset + 1;
parameter msr_de_offset = dp_cp_async_bus_snoop_flush_offset + 1;
parameter msr_pr_offset = msr_de_offset + 1;
parameter msr_cm_offset = msr_pr_offset + 1;
parameter msr_cm_noact_offset = msr_cm_offset + 1;
parameter msr_gs_offset = msr_cm_noact_offset + 1;
parameter msr_me_offset = msr_gs_offset + 1;
parameter dbcr0_edm_offset = msr_me_offset + 1;
parameter dbcr0_idm_offset = dbcr0_edm_offset + 1;
parameter dbcr0_icmp_offset = dbcr0_idm_offset + 1;
parameter dbcr0_brt_offset = dbcr0_icmp_offset + 1;
parameter dbcr0_irpt_offset = dbcr0_brt_offset + 1;
parameter dbcr0_trap_offset = dbcr0_irpt_offset + 1;
parameter iac1_en_offset = dbcr0_trap_offset + 1;
parameter iac2_en_offset = iac1_en_offset + 1;
parameter iac3_en_offset = iac2_en_offset + 1;
parameter iac4_en_offset = iac3_en_offset + 1;
parameter dbcr0_dac1_offset = iac4_en_offset + 1;
parameter dbcr0_dac2_offset = dbcr0_dac1_offset + 2;
parameter dbcr0_dac3_offset = dbcr0_dac2_offset + 2;
parameter dbcr0_dac4_offset = dbcr0_dac3_offset + 2;
parameter dbcr0_ret_offset = dbcr0_dac4_offset + 2;
parameter dbcr1_iac12m_offset = dbcr0_ret_offset + 1;
parameter dbcr1_iac34m_offset = dbcr1_iac12m_offset + 1;
parameter dbcr3_ivc_offset = dbcr1_iac34m_offset + 1;
parameter epcr_extgs_offset = dbcr3_ivc_offset + 1;
parameter epcr_dtlbgs_offset = epcr_extgs_offset + 1;
parameter epcr_itlbgs_offset = epcr_dtlbgs_offset + 1;
parameter epcr_dsigs_offset = epcr_itlbgs_offset + 1;
parameter epcr_isigs_offset = epcr_dsigs_offset + 1;
parameter epcr_duvd_offset = epcr_isigs_offset + 1;
parameter epcr_icm_offset = epcr_duvd_offset + 1;
parameter epcr_gicm_offset = epcr_icm_offset + 1;
parameter ccr2_ucode_dis_offset = epcr_gicm_offset + 1;
parameter ccr2_mmu_mode_offset = ccr2_ucode_dis_offset + 1;
parameter pc_iu_ram_active_offset = ccr2_mmu_mode_offset + 1;
parameter xu_iu_xucr4_mmu_mchk_offset = pc_iu_ram_active_offset + 1;
parameter pc_iu_ram_flush_thread_offset = xu_iu_xucr4_mmu_mchk_offset + 1;
parameter xu_iu_msrovride_enab_offset = pc_iu_ram_flush_thread_offset + 1;
parameter pc_iu_stop_offset = xu_iu_msrovride_enab_offset + 1;
parameter pc_iu_step_offset = pc_iu_stop_offset + 1;
parameter xu_iu_single_instr_offset = pc_iu_step_offset + 1;
parameter spr_single_issue_offset = xu_iu_single_instr_offset + 1;
parameter spr_ivpr_offset = spr_single_issue_offset + 1;
parameter spr_givpr_offset = spr_ivpr_offset + `GPR_WIDTH-12;
parameter spr_iac1_offset = spr_givpr_offset + `GPR_WIDTH-12;
parameter spr_iac2_offset = spr_iac1_offset + `EFF_IFAR_ARCH;
parameter spr_iac3_offset = spr_iac2_offset + `EFF_IFAR_ARCH;
parameter spr_iac4_offset = spr_iac3_offset + `EFF_IFAR_ARCH;
parameter spr_perf_mux_ctrls_offset = spr_iac4_offset + `EFF_IFAR_ARCH;
parameter pc_iu_dbg_action_offset = spr_perf_mux_ctrls_offset + 16;
parameter iu_pc_step_done_offset = pc_iu_dbg_action_offset + 3;
parameter uncond_dbg_event_offset = iu_pc_step_done_offset + 1;
parameter external_mchk_offset = uncond_dbg_event_offset + 1;
parameter ext_interrupt_offset = external_mchk_offset + 1;
parameter dec_interrupt_offset = ext_interrupt_offset + 1;
parameter udec_interrupt_offset = dec_interrupt_offset + 1;
parameter perf_interrupt_offset = udec_interrupt_offset + 1;
parameter fit_interrupt_offset = perf_interrupt_offset + 1;
parameter crit_interrupt_offset = fit_interrupt_offset + 1;
parameter wdog_interrupt_offset = crit_interrupt_offset + 1;
parameter gwdog_interrupt_offset = wdog_interrupt_offset + 1;
parameter gfit_interrupt_offset = gwdog_interrupt_offset + 1;
parameter gdec_interrupt_offset = gfit_interrupt_offset + 1;
parameter dbell_interrupt_offset = gdec_interrupt_offset + 1;
parameter cdbell_interrupt_offset = dbell_interrupt_offset + 1;
parameter gdbell_interrupt_offset = cdbell_interrupt_offset + 1;
parameter gcdbell_interrupt_offset = gdbell_interrupt_offset + 1;
parameter gmcdbell_interrupt_offset = gcdbell_interrupt_offset + 1;
parameter dbsr_interrupt_offset = gmcdbell_interrupt_offset + 1;
parameter fex_interrupt_offset = dbsr_interrupt_offset + 1;
parameter async_delay_cnt_offset = fex_interrupt_offset + 1;
parameter iu_lq_recirc_val_offset = async_delay_cnt_offset + 3;
parameter ext_dbg_stop_offset = iu_lq_recirc_val_offset + 1;
parameter ext_dbg_stop_other_offset = ext_dbg_stop_offset + 1;
parameter ext_dbg_act_err_offset = ext_dbg_stop_other_offset + 1;
parameter ext_dbg_act_ext_offset = ext_dbg_act_err_offset + 1;
parameter dbg_int_en_offset = ext_dbg_act_ext_offset + 1;
parameter dbg_event_en_offset = dbg_int_en_offset + 1;
parameter cp1_i0_dispatched_offset = dbg_event_en_offset + 1;
parameter cp1_i1_dispatched_offset = cp1_i0_dispatched_offset + `CPL_Q_DEPTH;
parameter iu7_i0_is_folded_offset = cp1_i1_dispatched_offset + `CPL_Q_DEPTH;
parameter iu7_i1_is_folded_offset = iu7_i0_is_folded_offset + 1;
parameter select_reset_offset = iu7_i1_is_folded_offset + 1;
parameter xu_iu_rest_ifar_offset = select_reset_offset + 1;
parameter attn_hold_offset = xu_iu_rest_ifar_offset + `EFF_IFAR_ARCH;
parameter flush_delay_offset = attn_hold_offset + 1;
parameter iu_nonspec_offset = flush_delay_offset + 2;
parameter ierat_pt_fault_offset = iu_nonspec_offset + 1;
parameter ierat_lrat_miss_offset = ierat_pt_fault_offset + 1;
parameter ierat_tlb_inelig_offset = ierat_lrat_miss_offset + 1;
parameter tlb_multihit_err_offset = ierat_tlb_inelig_offset + 1;
parameter tlb_par_err_offset = tlb_multihit_err_offset + 1;
parameter lru_par_err_offset = tlb_par_err_offset + 1;
parameter tlb_miss_offset = lru_par_err_offset + 1;
parameter reload_hit_offset = tlb_miss_offset + 1;
parameter nonspec_hit_offset = reload_hit_offset + 1;
parameter cp_mm_except_taken_offset = nonspec_hit_offset + 1;
parameter eheir_val_offset = cp_mm_except_taken_offset + 6;
parameter perf_bus_offset = eheir_val_offset + 1;
parameter scan_right = perf_bus_offset + 4;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire tidn;
wire tiup;
wire [0:`CPL_Q_DEPTH-1] lq0_execute_vld;
wire [0:`CPL_Q_DEPTH-1] lq0_recirc_vld;
wire [0:`CPL_Q_DEPTH-1] lq1_execute_vld;
wire [0:`CPL_Q_DEPTH-1] br_execute_vld;
wire [0:`CPL_Q_DEPTH-1] fold_i0_execute_vld;
wire [0:`CPL_Q_DEPTH-1] fold_i1_execute_vld;
wire [0:`CPL_Q_DEPTH-1] xu_execute_vld;
wire [0:`CPL_Q_DEPTH-1] xu1_execute_vld;
wire [0:`CPL_Q_DEPTH-1] axu0_execute_vld;
wire [0:`CPL_Q_DEPTH-1] axu1_execute_vld;
wire excvec_act;
wire [0:`CPL_Q_DEPTH-1] excvec_act_v;
wire [0:`CPL_Q_DEPTH-1] cp1_compl_ready;
wire [0:`CPL_Q_DEPTH-1] iu6_i0_ptr;
wire [0:`CPL_Q_DEPTH-1] iu6_i1_ptr;
wire [0:`CPL_Q_DEPTH-1] cp1_i0_dispatched;
wire [0:`CPL_Q_DEPTH-1] cp1_i1_dispatched;
wire [0:`CPL_Q_DEPTH-1] cp1_i0_completed;
wire [0:`CPL_Q_DEPTH-1] cp1_i1_completed;
wire [0:`CPL_Q_DEPTH-1] cp1_i0_completed_ror;
wire [0:`CPL_Q_DEPTH-1] exx_executed;
wire [0:`CPL_Q_DEPTH-1] cp1_completed;
wire [0:`CPL_Q_DEPTH-1] cp1_flushed;
wire [62-`EFF_IFAR_ARCH:61-`EFF_IFAR_WIDTH] cp3_ifor;
// Reasons to not complete I1
wire cp1_i01_comp_is_br; // Can't complete 2 branches in a cycle due to BHT writes
wire cp1_i0_comp_is_flush; // If you flush I0 don't complete I1
// Signal for NIA selection
wire select_i0_p1;
wire select_i1_p1;
wire select_i0_bta;
wire select_i1_bta;
wire select_i0_bp_bta;
wire select_i1_bp_bta;
wire select_ucode_p1;
wire select_reset;
wire select_reset_q;
wire select_mtiar;
// IU exception calculations
reg iu6_i0_exception_val;
reg iu6_i1_exception_val;
reg [0:3] iu6_i0_exception;
reg [0:3] iu6_i1_exception;
reg iu6_i0_n_flush;
reg iu6_i1_n_flush;
reg iu6_i0_np1_flush;
reg iu6_i1_np1_flush;
// Exception decode outputs
wire cp2_i0_iu_excvec_val;
wire cp2_i1_iu_excvec_val;
wire cp2_i0_lq_excvec_val;
wire cp2_i1_lq_excvec_val;
wire cp2_i0_xu_excvec_val;
wire cp2_i1_xu_excvec_val;
wire cp2_i0_axu_excvec_val;
wire cp2_i1_axu_excvec_val;
wire cp2_i0_db_events_val;
wire cp2_i1_db_events_val;
wire cp2_i0_exc_val;
wire cp2_i1_exc_val;
wire cp2_i0_ram_excvec_val;
wire cp1_async_block;
wire cp2_open_async;
wire iu_flush_cond;
wire flush_cond;
// Instruction Address Compares
wire [62-`EFF_IFAR_ARCH:61] iac2_mask;
wire [62-`EFF_IFAR_ARCH:61] iac4_mask;
wire [0:1] iac1_cmprh;
wire [0:1] iac2_cmprh;
wire [0:1] iac3_cmprh;
wire [0:1] iac4_cmprh;
wire [0:1] iac1_cmprl;
wire [0:1] iac2_cmprl;
wire [0:1] iac3_cmprl;
wire [0:1] iac4_cmprl;
wire [0:1] iac1_cmpr;
wire [0:1] iac2_cmpr;
wire [0:1] iac3_cmpr;
wire [0:1] iac4_cmpr;
wire [0:1] iac1_cmpr_sel;
wire [0:1] iac2_cmpr_sel;
wire [0:1] iac3_cmpr_sel;
wire [0:1] iac4_cmpr_sel;
wire [0:1] ivc_cmpr_sel;
wire ude_dbg_event;
wire [0:1] icmp_dbg_event;
wire [0:1] iac1_dbg_event;
wire [0:1] iac2_dbg_event;
wire [0:1] iac3_dbg_event;
wire [0:1] iac4_dbg_event;
wire [0:1] ret_sel;
wire [0:1] rfi_dbg_event;
wire [0:1] ivc_dbg_event;
wire trap_dbg_event;
wire brt_dbg_event;
wire [0:1] iu_irpt_dbg_event;
wire xu_irpt_dbg_event;
wire axu0_irpt_dbg_event;
wire axu1_irpt_dbg_event;
wire lq0_irpt_dbg_event;
wire lq1_irpt_dbg_event;
wire iac_i0_n_flush;
wire iac_i1_n_flush;
wire dac_lq0_n_flush;
wire dac_lq1_n_flush;
wire [0:1] dac1r_dbg_event;
wire [0:1] dac1w_dbg_event;
wire [0:1] dac2r_dbg_event;
wire [0:1] dac2w_dbg_event;
wire [0:1] dac3r_dbg_event;
wire [0:1] dac3w_dbg_event;
wire [0:1] dac4r_dbg_event;
wire [0:1] dac4w_dbg_event;
wire [0:1] dacr_dbg_event;
wire icmp_enable;
wire irpt_enable;
wire cp3_asyn_irpt_taken;
wire cp3_asyn_irpt_needed;
wire cp3_asyn_icmp_taken;
wire cp3_asyn_icmp_needed;
wire cp3_db_events_masked_reduced;
wire [0:1] iu6_dbg_flush_en;
wire cp2_complete_act;
wire cp2_msr_act;
wire iu6_i0_db_IAC_IVC_event;
wire iu6_i1_db_IAC_IVC_event;
wire [62-`EFF_IFAR_ARCH:61] iu6_ifar[0:1];
wire cp_iu0_flush_2ucode_int;
wire cp_flush_into_uc_int;
wire iu_xu_dbsr_ude_int;
// act signals
wire rn_cp_iu6_i0_act;
wire rn_cp_iu6_i1_act;
// Signals for itag comparison
wire br_older_xu;
wire br_older_lq;
wire br_older_save;
wire xu_older_lq;
wire xu_older_save;
wire lq_older_save;
wire select_br;
wire select_xu;
wire select_lq;
wire [1:32] save_table_pt;
// temp signals
wire iu_pc_i0_comp_temp;
wire iu_pc_i1_comp_temp;
wire cp_mm_itlb_miss;
wire cp_mm_dtlb_miss;
wire cp_mm_isi;
wire cp_mm_dsi;
wire cp_mm_ilrat_miss;
wire cp_mm_dlrat_miss;
wire cp_mm_imchk;
wire cp_mm_dmchk;
wire dis_mm_mchk;
wire eheir_val;
wire [1:`ITAG_SIZE_ENC-1] eheir_itag;
wire [0:31] eheir_instr;
wire cp_events_en;
wire [0:15] cp_events_in;
wire iu_pc_i0_comp, iu_pc_i1_comp, iu_pc_i0_br_miss, iu_pc_i1_br_miss, iu_pc_i0_br_pred, iu_pc_i1_br_pred, pc_iu_stop_d, iu_pc_flush_cnt;
assign tidn = 1'b0;
assign tiup = 1'b1;
function [0:`CPL_Q_DEPTH-1] decode_a;
input [1:`ITAG_SIZE_ENC-1] decode_input;
//(* analysis_not_referenced="true" *)
integer i;
for(i = 0; i < `CPL_Q_DEPTH; i = i + 1)
begin
if({{32-`ITAG_SIZE_ENC+1{1'b0}},decode_input} == i)
decode_a[i] = 1'b1;
else
decode_a[i] = 1'b0;
end
endfunction
//-----------------------------------------------------------------------------
// Temporary
//-----------------------------------------------------------------------------
assign iu_pc_i0_comp = iu_pc_i0_comp_temp;
assign iu_pc_i1_comp = iu_pc_i1_comp_temp;
assign iu_pc_i0_br_miss = iu_pc_i0_comp_temp & cp2_i0_br_miss_q;
assign iu_pc_i1_br_miss = iu_pc_i1_comp_temp & cp2_i1_br_miss_q;
assign iu_pc_i0_br_pred = iu_pc_i0_comp_temp & cp2_i0_bp_pred_q;
assign iu_pc_i1_br_pred = iu_pc_i1_comp_temp & cp2_i1_bp_pred_q;
assign iu_pc_flush_cnt = flush_cond;
//-----------------------------------------------------------------------------
// Status Control
//-----------------------------------------------------------------------------
assign iu6_i0_ptr = decode_a(iu6_i0_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign iu6_i1_ptr = decode_a(iu6_i1_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign cp1_i0_dispatched = iu6_i0_dispatched_q ? iu6_i0_ptr : 0;
assign cp1_i1_dispatched = iu6_i1_dispatched_q ? iu6_i1_ptr : 0;
assign cp1_i0_dispatched_delay_d = {`CPL_Q_DEPTH{~(cp3_flush_q | cp2_flush_q)}} & cp1_i0_dispatched;
assign cp1_i1_dispatched_delay_d = {`CPL_Q_DEPTH{~(cp3_flush_q | cp2_flush_q)}} & cp1_i1_dispatched;
assign cp0_dispatched = ({`CPL_Q_DEPTH{~cp3_flush_q}} & ((cp1_dispatched_q & (~cp1_completed)) | (cp1_i0_dispatched_delay_q | cp1_i1_dispatched_delay_q)));
assign exx_executed = lq0_execute_vld | lq1_execute_vld | br_execute_vld | xu_execute_vld | xu1_execute_vld |
axu0_execute_vld | axu1_execute_vld | fold_i0_execute_vld | fold_i1_execute_vld;
assign cp0_executed = (({`CPL_Q_DEPTH{~cp3_flush_q}}) & ((cp1_executed_q & (~cp1_completed)) | exx_executed));
assign cp1_compl_ready = cp1_dispatched_q & cp1_executed_q;
assign cp1_i0_completed = ({`CPL_Q_DEPTH{~cp2_flush_q & ~cp3_flush_q}} & (cp1_i0_ptr_q & cp1_compl_ready & ~cp1_n_flush_q));
assign cp1_i0_completed_ror = {cp1_i0_completed[`CPL_Q_DEPTH - 1], cp1_i0_completed[0:`CPL_Q_DEPTH - 2]};
assign cp1_i01_comp_is_br = (|(cp1_i0_ptr_q & cp1_is_br_q) & |(cp1_i1_ptr_q & cp1_is_br_q));
assign cp1_i0_comp_is_flush = |(cp1_i0_ptr_q & (cp1_n_flush_q | cp1_np1_flush_q));
assign cp1_i1_completed = ({`CPL_Q_DEPTH{~cp2_flush_q & ~cp3_flush_q & ~cp1_i01_comp_is_br & ~cp1_i0_comp_is_flush}} &
(cp1_i1_ptr_q & cp1_compl_ready & (~cp1_n_flush_q) & cp1_i0_completed_ror));
assign cp1_completed = cp1_i0_completed | cp1_i1_completed | cp1_flushed;
assign cp1_i0_complete = |(cp1_i0_completed) & ~cp1_async_int_val;
assign cp1_i1_complete = |(cp1_i1_completed) & ~cp1_async_int_val;
assign cp1_flushed = (cp1_i0_ptr_q | cp1_i0_completed_ror) & cp1_compl_ready & (cp1_n_flush_q | cp1_np1_flush_q);
assign cp1_flush = (|(cp1_flushed) | cp1_async_int_val) & ~cp2_flush_q & ~cp3_flush_q;
assign cp1_i0_np1_flush = |(cp1_i0_ptr_q & cp1_np1_flush_q) & ~cp1_async_int_val;
assign cp1_i1_np1_flush = |(cp1_i1_ptr_q & cp1_np1_flush_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i0_n_np1_flush = |(cp1_i0_ptr_q & cp1_n_np1_flush_q) & ~cp1_async_int_val;
assign cp1_i1_n_np1_flush = |(cp1_i1_ptr_q & cp1_n_np1_flush_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i0_bp_pred = |(cp1_i0_ptr_q & cp1_bp_pred_q) & ~cp1_async_int_val;
assign cp1_i1_bp_pred = |(cp1_i1_ptr_q & cp1_bp_pred_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i0_br_pred = |(cp1_i0_ptr_q & cp1_br_pred_q) & ~cp1_async_int_val;
assign cp1_i1_br_pred = |(cp1_i1_ptr_q & cp1_br_pred_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i0_br_miss = |(cp1_i0_ptr_q & cp1_br_miss_q) & ~cp1_async_int_val;
assign cp1_i1_br_miss = |(cp1_i1_ptr_q & cp1_br_miss_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i0_flush2ucode = |(cp1_i0_ptr_q & cp1_flush2ucode_q) & ~cp1_async_int_val;
assign cp1_i0_flush2ucode_type = |(cp1_i0_ptr_q & cp1_flush2ucode_type_q) & ~cp1_async_int_val;
assign cp1_i1_flush2ucode = |(cp1_i1_ptr_q & cp1_flush2ucode_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i1_flush2ucode_type = |(cp1_i1_ptr_q & cp1_flush2ucode_type_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val;
assign cp1_i0_iu_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_iu_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i1_iu_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_iu_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i0_lq_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_lq_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i1_lq_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_lq_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i0_xu_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_xu_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i1_xu_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_xu_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i0_axu_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_axu_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i1_axu_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_axu_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i0_db_val = |(cp1_i0_ptr_q & cp1_compl_ready) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i1_db_val = |(cp1_i1_ptr_q & cp1_compl_ready & cp1_i0_completed_ror) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val;
assign cp1_i_bta = cp1_br_bta_q;
// always @(cp1_i0_ptr_q or cp1_i1_ptr_q or cp1_iu_excvec_q or cp1_lq_excvec_q or cp1_xu_excvec_q or cp1_axu_excvec_q or cp1_db_events_q)
always @(*)
begin: cp1_excvec_proc
//(* analysis_not_referenced="true" *)
integer e;
cp1_i0_iu_excvec = 0;
cp1_i1_iu_excvec = 0;
cp1_i0_lq_excvec = 0;
cp1_i1_lq_excvec = 0;
cp1_i0_xu_excvec = 0;
cp1_i1_xu_excvec = 0;
cp1_i0_axu_excvec = 0;
cp1_i1_axu_excvec = 0;
cp1_i0_db_events = 0;
cp1_i1_db_events = 0;
cp1_i0_perf_events = 0;
cp1_i1_perf_events = 0;
for (e = 0; e < `CPL_Q_DEPTH; e = e + 1)
begin
if (cp1_i0_ptr_q[e] == 1'b1)
begin
cp1_i0_iu_excvec = cp1_iu_excvec_q[e];
cp1_i0_lq_excvec = cp1_lq_excvec_q[e];
cp1_i0_xu_excvec = cp1_xu_excvec_q[e];
cp1_i0_axu_excvec = cp1_axu_excvec_q[e];
cp1_i0_db_events = cp1_db_events_q[e];
cp1_i0_perf_events = cp1_perf_events_q[e];
end
if (cp1_i1_ptr_q[e] == 1'b1)
begin
cp1_i1_iu_excvec = cp1_iu_excvec_q[e];
cp1_i1_lq_excvec = cp1_lq_excvec_q[e];
cp1_i1_xu_excvec = cp1_xu_excvec_q[e];
cp1_i1_axu_excvec = cp1_axu_excvec_q[e];
cp1_i1_db_events = cp1_db_events_q[e];
cp1_i1_perf_events = cp1_perf_events_q[e];
end
end
end
// The following table is for the cp2_async_hold and cp2_async_open logic
// cp2_i0_complete_q |
// | cp2_i1_complete_q |
// | | in_ucode_i0 |
// | | | ucode_end_i0 |
// | | | | nop_i0 |
// | | | | | in_ucode_i1 | open
// | | | | | | ucode_end_i1 | | hold
// | | | | | | | nop_i1 | | |
// | | | | | | | | | | |
// -------------------------------------------
// 0 0 - - - - - - | 0 0
// 1 0 0 - 0 - - - | 1 0 -- new
// 1 0 1 0 - - - - | 0 1
// 1 0 1 1 - - - - | 1 0
// 1 0 - - 1 - - - | 0 1
// 1 1 1 0 - 1 0 - | 0 1
// 1 1 1 0 - 1 1 - | 1 0
// 1 1 - - - 0 - 0 | 1 0 -- changed
// 1 1 - - - 0 - 1 | 0 1 -- changed
// 1 1 1 1 - 1 - - | 1 1
assign cp3_async_hold_d = (cp2_async_hold | (cp3_async_hold_q & ~cp2_open_async)) & ~(iu_flush_cond & ~cp_flush_into_uc_int);
assign cp2_async_hold = (cp2_i0_complete_q & ~cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2]) |
(cp2_i0_complete_q & ~cp2_i1_complete_q & cp2_i0_fuse_nop) |
(cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1]) & ~cp2_i1_ucode[2]) |
(cp2_i0_complete_q & cp2_i1_complete_q & ~(cp2_i1_ucode[0] | cp2_i1_ucode[1]) & cp2_i1_fuse_nop) |
(cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1]));
assign cp2_open_async = (cp2_i0_complete_q & ~cp2_i1_complete_q & ~(cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_fuse_nop) |
(cp2_i0_complete_q & ~cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & cp2_i0_ucode[2]) |
(cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1]) & cp2_i1_ucode[2]) |
(cp2_i0_complete_q & cp2_i1_complete_q & ~(cp2_i1_ucode[0] | cp2_i1_ucode[1]) & ~cp2_i1_fuse_nop) |
(cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1]));
assign cp1_async_block = (((|(cp1_i0_ptr_q & cp1_dispatched_q & (cp1_async_block_q | cp1_recirc_vld_q))) | (cp2_async_hold | cp3_async_hold_q)) & ~cp2_open_async) | iu_nonspec_q;
assign cp1_async_int = {( {tlb_miss_q, lru_par_err_q, tlb_par_err_q, tlb_multihit_err_q, ierat_pt_fault_q,
ierat_tlb_inelig_q, ierat_lrat_miss_q}),
({25{~cp1_async_block}} & {cp4_asyn_icmp_needed_q, cp4_asyn_irpt_needed_q, dp_cp_async_flush_q, dp_cp_async_bus_snoop_flush_q,
np1_async_flush_q, pc_iu_stop_q, dbsr_interrupt_q, fex_interrupt_q, external_mchk_q, gmcdbell_interrupt_q,
ude_dbg_event, crit_interrupt_q, wdog_interrupt_q, gwdog_interrupt_q, cdbell_interrupt_q,
gcdbell_interrupt_q, ext_interrupt_q, fit_interrupt_q, gfit_interrupt_q, dec_interrupt_q,
gdec_interrupt_q, dbell_interrupt_q, gdbell_interrupt_q, udec_interrupt_q, perf_interrupt_q})};
assign cp1_async_int_val = |(cp1_async_int) & ~cp2_flush_q & ~cp3_flush_q & (async_delay_cnt_q == 3'b0) & ~flush_hold;
assign iu_lq_recirc_val_d = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_recirc_vld_q);
//-----------------------------------------------------------------------------
// IFAR/ITAG Tracking
//-----------------------------------------------------------------------------
assign iu_xu_cp2_rfi_d = (cp2_i0_complete_q & cp2_i0_rfi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]})));
assign iu_xu_cp2_rfgi_d = (cp2_i0_complete_q & cp2_i0_rfgi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfgi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]})));
assign iu_xu_cp2_rfci_d = (cp2_i0_complete_q & cp2_i0_rfci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]})));
assign iu_xu_cp2_rfmci_d = (cp2_i0_complete_q & cp2_i0_rfmci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfmci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]})));
assign iu_xu_rfi = iu_xu_cp4_rfi_q;
assign iu_xu_rfgi = iu_xu_cp4_rfgi_q;
assign iu_xu_rfci = iu_xu_cp4_rfci_q;
assign iu_xu_rfmci = iu_xu_cp4_rfmci_q;
assign cp2_rfi = (cp2_i0_complete_q & cp2_i0_rfi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))) |
(cp2_i0_complete_q & cp2_i0_rfgi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfgi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))) |
(cp2_i0_complete_q & cp2_i0_rfci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))) |
(cp2_i0_complete_q & cp2_i0_rfmci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_rfmci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]})));
assign cp2_attn = (cp2_i0_complete_q & cp2_i0_attn & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) |
(cp2_i1_complete_q & cp2_i1_attn & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]})));
assign cp2_sc = (cp2_i0_complete_q & cp2_i0_sc) |
(cp2_i1_complete_q & cp2_i1_sc);
iuq_cpl_table iuq_cpl_table(
// NIA table inputs
.i0_complete(cp2_i0_complete_q),
.i0_bp_pred(cp2_i0_bp_pred_q),
.i0_br_miss(cp2_i0_br_miss_q),
.i0_ucode(cp2_i0_ucode),
.i0_isram(cp2_i0_isram),
.i0_mtiar(cp2_i0_mtiar),
.i0_rollover(cp2_i0_rollover),
.i0_rfi(cp6_rfi_q),
.i0_n_np1_flush(cp2_i0_n_np1_flush_q),
.i1_complete(cp2_i1_complete_q),
.i1_bp_pred(cp2_i1_bp_pred_q),
.i1_br_miss(cp2_i1_br_miss_q),
.i1_ucode(cp2_i1_ucode),
.i1_isram(cp2_i1_isram),
.i1_mtiar(cp2_i1_mtiar),
.i1_rollover(cp2_i1_rollover),
.i1_rfi(tidn),
.i1_n_np1_flush(cp2_i1_n_np1_flush_q),
// Temp perf
.iu_pc_i0_comp(iu_pc_i0_comp_temp),
.iu_pc_i1_comp(iu_pc_i1_comp_temp),
.icmp_enable(icmp_enable),
.irpt_enable(irpt_enable),
// NIA output selectors
.select_i0_p1(select_i0_p1),
.select_i1_p1(select_i1_p1),
.select_i0_bta(select_i0_bta),
.select_i1_bta(select_i1_bta),
.select_i0_bp_bta(select_i0_bp_bta),
.select_i1_bp_bta(select_i1_bp_bta),
.select_ucode_p1(select_ucode_p1),
.select_reset(select_reset),
.select_mtiar(select_mtiar), // only used to gate off the branch mispredict
// Async list
.cp3_async_int_val(cp3_async_int_val_q),
.cp3_async_int(cp3_async_int_q),
// IU execption list
.cp3_iu_excvec_val(cp3_iu_excvec_val_q),
.cp3_iu_excvec(cp3_iu_excvec_q),
// LQ execption list
.cp3_lq_excvec_val(cp3_lq_excvec_val_q),
.cp3_lq_excvec(cp3_lq_excvec_q),
// XU execption list
.cp3_xu_excvec_val(cp3_xu_excvec_val_q),
.cp3_xu_excvec(cp3_xu_excvec_q),
// AXU execption list
.cp3_axu_excvec_val(cp3_axu_excvec_val_q),
.cp3_axu_excvec(cp3_axu_excvec_q),
// Debug events
.cp3_db_val(cp3_db_val_q),
.cp3_db_events(cp3_db_events_q),
// Instruction info
.cp3_ld(cp3_ld_q),
.cp3_st(cp3_st_q),
.cp3_fp(cp3_fp_q),
.cp3_ap(cp3_ap_q),
.cp3_spv(cp3_spv_q),
.cp3_epid(cp3_epid_q),
.cp3_rfi(cp3_rfi_q),
.cp3_attn(cp3_attn_q),
.cp3_sc(cp3_sc_q),
.cp3_icmp_block(cp3_icmp_block_q),
// Debug interrupt taken
.cp3_asyn_irpt_taken(cp3_asyn_irpt_taken),
.cp3_asyn_irpt_needed(cp3_asyn_irpt_needed),
.cp3_asyn_icmp_taken(cp3_asyn_icmp_taken),
.cp3_asyn_icmp_needed(cp3_asyn_icmp_needed),
.cp3_db_events_masked_reduced(cp3_db_events_masked_reduced),
// Execption output
.cp3_exc_nia(cp3_exc_nia),
.cp3_mchk_disabled(cp3_mchk_disabled),
// SPR bits
.spr_ivpr(spr_ivpr),
.spr_givpr(spr_givpr),
.msr_gs(msr_gs_q),
.msr_me(msr_me_q),
.dbg_int_en(dbg_int_en_q),
.dbcr0_irpt(dbcr0_irpt_q),
.epcr_duvd(epcr_duvd_q),
.epcr_extgs(epcr_extgs_q),
.epcr_dtlbgs(epcr_dtlbgs_q),
.epcr_itlbgs(epcr_itlbgs_q),
.epcr_dsigs(epcr_dsigs_q),
.epcr_isigs(epcr_isigs_q),
.epcr_icm(epcr_icm_q),
.epcr_gicm(epcr_gicm_q),
// Type of exception
.dp_cp_async_flush(cp3_dp_cp_async_flush),
.dp_cp_async_bus_snoop_flush(cp3_dp_cp_async_bus_snoop_flush),
.async_np1_flush(cp3_async_np1),
.async_n_flush(cp3_async_n),
.mm_iu_exception(cp3_mm_iu_exception),
.pc_iu_stop(cp3_pc_stop),
.mc_int(cp3_mc_int),
.g_int(cp3_g_int),
.c_int(cp3_c_int),
.dbell_taken(cp3_dbell_int),
.cdbell_taken(cp3_cdbell_int),
.gdbell_taken(cp3_gdbell_int),
.gcdbell_taken(cp3_gcdbell_int),
.gmcdbell_taken(cp3_gmcdbell_int),
// Update bits to SPR parititon
.dear_update(cp3_dear_update),
.dbsr_update(cp3_dbsr_update),
.eheir_update(cp3_eheir_update),
.cp3_dbsr(cp3_dbsr),
// ESR bits
.esr_update(cp3_esr_update),
.cp3_exc_esr(cp3_exc_esr),
.cp3_exc_mcsr(cp3_exc_mcsr),
.cp_mm_itlb_miss(cp_mm_itlb_miss),
.cp_mm_dtlb_miss(cp_mm_dtlb_miss),
.cp_mm_isi(cp_mm_isi),
.cp_mm_dsi(cp_mm_dsi),
.cp_mm_ilrat_miss(cp_mm_ilrat_miss),
.cp_mm_dlrat_miss(cp_mm_dlrat_miss),
.cp_mm_imchk(cp_mm_imchk),
.cp_mm_dmchk(cp_mm_dmchk),
.dis_mm_mchk(dis_mm_mchk)
);
assign cp2_ifar = ({19{~cp2_i0_complete_q | cp2_i0_np1_flush_q}} & cp2_i0_ifar[43:61]) |
({19{cp2_i0_complete_q & ~cp2_i0_np1_flush_q}} & cp2_i1_ifar[43:61]);
assign cp2_np1_flush = (cp2_i0_complete_q & cp2_i0_np1_flush_q) |
(~cp2_i0_np1_flush_q & cp2_i1_complete_q & cp2_i1_np1_flush_q);
assign cp2_ucode = (~cp2_i0_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1] | cp2_i0_ucode[2])) |
(cp2_i0_complete_q & ~cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2]);
assign cp2_preissue = (cp2_i0_ucode == 3'b010);
assign iu_pc_step_done_d = (pc_iu_step_q & cp2_flush_q & ~(cp2_flush2ucode | cp2_ucode | cp2_flush_nonspec)) |
(iu_pc_step_done_q & pc_iu_step_q);
assign cp3_flush_d = cp2_flush_q;
assign nia_mask = ~msr_cm_noact_q ? {{`EFF_IFAR_ARCH-30{1'b0}}, {30{1'b1}}} : {`EFF_IFAR_ARCH{1'b1}};
assign cp4_excvec_val = ((~(cp4_async_np1_q | cp4_async_n_q | cp4_pc_stop_q | cp4_dp_cp_async_flush_q | cp4_dp_cp_async_bus_snoop_flush_q)) & cp4_excvec_val_q);
assign cp2_nia = ({`EFF_IFAR_ARCH{select_i0_p1}} & (nia_mask & ({cp3_ifor, cp2_i0_ifar} + 1))) |
({`EFF_IFAR_ARCH{select_i1_p1}} & (nia_mask & ({cp3_ifor, cp2_i1_ifar} + 1))) |
({`EFF_IFAR_ARCH{select_i0_bta}} & (nia_mask & cp2_i_bta_q)) |
({`EFF_IFAR_ARCH{select_i1_bta}} & (nia_mask & cp2_i_bta_q)) |
({`EFF_IFAR_ARCH{select_i0_bp_bta}} & (nia_mask & {cp3_ifor, cp2_i0_bp_bta})) |
({`EFF_IFAR_ARCH{select_i1_bp_bta}} & (nia_mask & {cp3_ifor, cp2_i1_bp_bta})) |
({`EFF_IFAR_ARCH{select_ucode_p1}} & (nia_mask & (cp3_nia_q + 1))) |
({`EFF_IFAR_ARCH{select_reset_q}} & xu_iu_rest_ifar_q) |
({`EFF_IFAR_ARCH{cp4_excvec_val}} & cp4_exc_nia_q);
assign cp3_nia_act = (select_i0_p1 | select_i1_p1 | select_i0_bta | select_i1_bta | select_i0_bp_bta | select_i1_bp_bta | select_ucode_p1 | select_reset_q | cp4_excvec_val);
assign cp3_ifor = cp3_nia_q[62-`EFF_IFAR_ARCH:61-`EFF_IFAR_WIDTH];
//-----------------------------------------------------------------------------
// Exception Handler (Work in progress)
//-----------------------------------------------------------------------------
assign cp2_i0_iu_excvec_val = cp2_i0_iu_excvec_val_q & (~(cp2_i0_isram));
assign cp2_i1_iu_excvec_val = cp2_i1_iu_excvec_val_q & (~(cp2_i1_isram));
assign cp2_i0_lq_excvec_val = cp2_i0_lq_excvec_val_q & (~(cp2_i0_isram));
assign cp2_i1_lq_excvec_val = cp2_i1_lq_excvec_val_q & (~(cp2_i1_isram));
assign cp2_i0_xu_excvec_val = cp2_i0_xu_excvec_val_q & (~(cp2_i0_isram));
assign cp2_i1_xu_excvec_val = cp2_i1_xu_excvec_val_q & (~(cp2_i1_isram));
assign cp2_i0_axu_excvec_val = cp2_i0_axu_excvec_val_q & (~(cp2_i0_isram));
assign cp2_i1_axu_excvec_val = cp2_i1_axu_excvec_val_q & (~(cp2_i1_isram));
assign cp2_i0_db_events_val = cp2_i0_db_val_q & (~(cp2_i0_isram));
assign cp2_i1_db_events_val = cp2_i1_db_val_q & (~(cp2_i1_isram));
assign cp2_i0_exc_val = cp2_i0_iu_excvec_val | cp2_i0_lq_excvec_val | cp2_i0_xu_excvec_val | cp2_i0_axu_excvec_val;
assign cp2_i1_exc_val = cp2_i1_iu_excvec_val | cp2_i1_lq_excvec_val | cp2_i1_xu_excvec_val | cp2_i1_axu_excvec_val;
assign cp2_i0_ram_excvec_val = cp2_i0_iu_excvec_val_q | cp2_i0_lq_excvec_val_q | cp2_i0_xu_excvec_val_q | cp2_i0_axu_excvec_val_q;
assign cp2_iu_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_iu_excvec_val) |
((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_iu_excvec_val);
assign cp2_iu_excvec = ({4{cp2_i0_iu_excvec_val_q}} & cp2_i0_iu_excvec_q) |
({4{~cp2_i0_iu_excvec_val_q & cp2_i1_iu_excvec_val_q}} & cp2_i1_iu_excvec_q);
assign cp2_lq_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_lq_excvec_val) |
((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_lq_excvec_val);
assign cp2_lq_excvec = ({6{cp2_i0_lq_excvec_val_q}} & cp2_i0_lq_excvec_q) |
({6{~cp2_i0_lq_excvec_val_q & cp2_i1_lq_excvec_val_q}} & cp2_i1_lq_excvec_q);
assign cp2_xu_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_xu_excvec_val) |
((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_xu_excvec_val);
assign cp2_xu_excvec = ({5{cp2_i0_xu_excvec_val_q}} & cp2_i0_xu_excvec_q) |
({5{~cp2_i0_xu_excvec_val_q & cp2_i1_xu_excvec_val_q}} & cp2_i1_xu_excvec_q);
assign cp2_axu_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_axu_excvec_val) |
((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_axu_excvec_val);
assign cp2_axu_excvec = ({4{cp2_i0_axu_excvec_val_q}} & cp2_i0_axu_excvec_q) |
({4{~cp2_i0_axu_excvec_val_q & cp2_i1_axu_excvec_val_q}} & cp2_i1_axu_excvec_q);
assign cp2_i0_axu_exception_val = cp2_i0_axu_excvec_val & cp2_i0_complete_q;
assign cp2_i0_axu_exception = cp2_i0_axu_excvec_q;
assign cp2_i1_axu_exception_val = cp2_i1_axu_excvec_val & cp2_i1_complete_q;
assign cp2_i1_axu_exception = cp2_i1_axu_excvec_q;
assign cp2_db_val = (((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_db_events_val) |
((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_db_events_val)) & msr_de_q;
assign cp2_db_events = ({19{cp2_i0_db_events_val}} & cp2_i0_db_events_q) |
({19{cp2_i1_db_events_val}} & cp2_i1_db_events_q);
// Hold ucode values
assign cp3_ld_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 :
((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_ld :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_ld :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 :
((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 :
cp3_ld_save_q;
assign cp3_st_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 :
((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? (cp2_i1_st | cp2_i1_type_st) :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? (cp2_i0_st | cp2_i0_type_st) :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 :
((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 :
cp3_st_save_q;
assign cp3_fp_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 :
((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_type_fp :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_type_fp :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 :
((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 :
cp3_fp_save_q;
assign cp3_ap_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 :
((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_type_ap :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_type_ap :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 :
((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 :
cp3_ap_save_q;
assign cp3_spv_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 :
((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_type_spv :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_type_spv :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 :
((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 :
cp3_spv_save_q;
assign cp3_epid_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 :
((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_epid :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_epid :
((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 :
((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 :
cp3_epid_save_q;
assign cp2_ld = (cp2_i0_exc_val & (cp3_ld_save_q | cp2_i0_ld)) |
((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_ld_save_q) |
((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_ld);
assign cp2_st = (cp2_i0_exc_val & (cp3_st_save_q | cp2_i0_st | cp2_i0_type_st)) |
((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_st_save_q) |
((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & (cp2_i1_st | cp2_i1_type_st));
assign cp2_fp = (cp2_i0_exc_val & (cp3_fp_save_q | cp2_i0_type_fp)) |
((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_fp_save_q) |
((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_type_fp);
assign cp2_ap = (cp2_i0_exc_val & (cp3_ap_save_q | cp2_i0_type_ap)) |
((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_ap_save_q) |
((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_type_ap);
assign cp2_spv = (cp2_i0_exc_val & (cp3_spv_save_q | cp2_i0_type_spv)) |
((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_spv_save_q) |
((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_type_spv);
assign cp2_epid = (cp2_i0_exc_val & (cp3_epid_save_q | cp2_i0_epid)) |
((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_epid_save_q) |
((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_epid);
assign cp2_icmp_block = (cp2_i0_db_events_val & cp2_i0_icmp_block) | (cp2_i1_db_events_val & cp2_i1_icmp_block);
assign cp2_flush2ucode = ((cp2_i0_flush2ucode_q) | (cp2_i0_complete_q & ~cp2_i0_np1_flush_q & cp2_i1_flush2ucode_q)) & cp2_flush_q;
assign cp2_flush2ucode_type = ((cp2_i0_flush2ucode_type_q) | (cp2_i0_complete_q & ~cp2_i0_np1_flush_q & cp2_i1_flush2ucode_type_q)) & cp2_flush_q;
assign cp2_flush_nonspec = ((cp2_i0_nonspec) | (cp2_i0_complete_q & ~cp2_i0_np1_flush_q & cp2_i1_nonspec)) & cp2_flush_q;
assign cp2_mispredict = (select_i0_bta | select_i1_bta) & (~(select_mtiar));
// Async debug interrupt
assign cp4_asyn_irpt_needed_d = (cp4_asyn_irpt_needed_q & dbg_event_en_q & (~(cp3_asyn_irpt_taken))) | cp3_asyn_irpt_needed;
assign cp4_asyn_icmp_needed_d = (cp4_asyn_icmp_needed_q & (~(cp3_asyn_icmp_taken))) | cp3_asyn_icmp_needed;
// Delayed for table lookups
assign cp3_excvec_val = (cp3_iu_excvec_val_q | cp3_lq_excvec_val_q | cp3_xu_excvec_val_q |
cp3_axu_excvec_val_q | (cp3_db_val_q & cp3_db_events_masked_reduced) | cp3_async_int_val_q) & ~cp3_mchk_disabled;
// Just or all exceptions here
assign cp3_rfi = cp3_rfi_q; // need to check if we are in the right state someday
assign flush_hold_d[0] = cp4_excvec_val_q | attn_hold_q; // Need to hold exceptions longer to make sure updates have occured.
assign flush_hold_d[1] = flush_hold_q[0]; // Need to hold exceptions longer to make sure updates have occured.
assign flush_hold = |flush_hold_q;
assign np1_async_flush_d = (np1_async_flush_q & (~(cp4_async_np1_q))) | xu_iu_np1_async_flush;
assign pc_iu_stop_d = (pc_iu_stop_q & (~(cp4_pc_stop_q | pc_stop_hold_q))) | (pc_iu_stop & ~pc_stop_hold_q);
assign pc_stop_hold_d = (pc_stop_hold_q & pc_iu_stop) | cp4_pc_stop_q;
assign dp_cp_async_flush_d = (dp_cp_async_flush_q & (~(cp4_dp_cp_async_flush_q))) | dp_cp_hold_req;
assign dp_cp_async_bus_snoop_flush_d = (dp_cp_async_bus_snoop_flush_q & (~(cp4_dp_cp_async_bus_snoop_flush_q))) | dp_cp_bus_snoop_hold_req;
assign iu_xu_int = cp4_excvec_val_q & (~(cp4_g_int_q | cp4_c_int_q | cp4_mc_int_q | cp4_async_np1_q | cp4_async_n_q | cp4_pc_stop_q | cp4_dp_cp_async_flush_q | cp4_dp_cp_async_bus_snoop_flush_q));
assign iu_xu_async_complete = cp4_async_np1_q;
assign iu_mm_hold_ack = cp4_dp_cp_async_flush_q;
assign iu_mm_bus_snoop_hold_ack = cp4_dp_cp_async_bus_snoop_flush_q;
assign iu_xu_gint = cp4_g_int_q;
assign iu_xu_cint = cp4_c_int_q;
assign iu_xu_mcint = cp4_mc_int_q;
assign iu_xu_nia = cp3_nia_q;
assign iu_xu_esr_update = cp4_esr_update_q;
assign iu_xu_esr = cp4_exc_esr_q;
assign iu_xu_mcsr = cp4_exc_mcsr_q;
assign iu_xu_dbsr_update = cp4_dbsr_update_q;
assign iu_xu_dbsr = cp4_dbsr_q;
assign iu_xu_dear_update = cp4_dear_update_q;
assign iu_xu_dear = lq0_eff_addr_q;
assign iu_xu_stop = cp4_pc_stop_q | pc_stop_hold_q;
assign iu_xu_quiesce = ~|cp1_dispatched_q;
assign iu_xu_act = cp4_excvec_val_q | cp4_dbsr_update_q;
assign iu_xu_dbell_taken = cp4_dbell_int_q;
assign iu_xu_cdbell_taken = cp4_cdbell_int_q;
assign iu_xu_gdbell_taken = cp4_gdbell_int_q;
assign iu_xu_gcdbell_taken = cp4_gcdbell_int_q;
assign iu_xu_gmcdbell_taken = cp4_gmcdbell_int_q;
assign iu_xu_instr_cpl = iu_pc_i0_comp_temp | iu_pc_i1_comp_temp;
assign iu_spr_eheir_update = cp4_eheir_update_q;
assign iu_spr_eheir = cp1_br_bta_q[30:61];
assign iu_pc_step_done = iu_pc_step_done_q;
assign iu_pc_attention_instr = (cp2_i0_complete_q & cp2_i0_attn) | (cp2_i1_complete_q & cp2_i1_attn);
assign iu_pc_err_mchk_disabled = cp4_mchk_disabled_q;
assign attn_hold_d = (cp2_i0_complete_q & cp2_i0_attn) | (cp2_i1_complete_q & cp2_i1_attn) | (attn_hold_q & (~(pc_iu_stop_q)));
assign async_delay_cnt_d = (cp3_excvec_val == 1'b1 | cp3_rfi_q == 1'b1 | async_delay_cnt_q != 3'b0) ? async_delay_cnt_q + 3'b001 : async_delay_cnt_q;
`ifdef THREADS1
assign iu_pc_stop_dbg_event = ext_dbg_stop_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int);
`endif
`ifndef THREADS1
assign iu_pc_stop_dbg_event = {(ext_dbg_stop_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int)),
(ext_dbg_stop_other_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int))};
`endif
assign iu_pc_err_debug_event = ext_dbg_act_err_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int);
assign ac_an_debug_trigger = ext_dbg_act_ext_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int);
assign iu_pc_ram_done = (cp2_i0_complete_q | cp2_i0_ram_excvec_val | (cp2_flush_q & cp2_flush2ucode)) & cp2_i0_isram;
assign iu_pc_ram_interrupt = cp2_i0_ram_excvec_val & ~&cp2_iu_excvec & cp2_i0_isram;
assign iu_pc_ram_unsupported = ((cp2_i0_ram_excvec_val & (&cp2_iu_excvec)) | (cp2_flush_q & cp2_flush2ucode)) & cp2_i0_isram;
assign cp_async_block = cp3_async_hold_q;
//-----------------------------------------------------------------------------
// ACT
//-----------------------------------------------------------------------------
assign cp2_complete_act = cp2_i0_complete_q | cp2_i1_complete_q | flush_cond | flush_delay_q[0];
assign cp2_msr_act = xu_iu_msrovride_enab_q | cp2_complete_act;
//-----------------------------------------------------------------------------
// Next ITAG to complete
//-----------------------------------------------------------------------------
assign cp_next_itag_d = ~(cp2_flush_q | cp3_flush_q) ? cp2_i0_itag_q : {`ITAG_SIZE_ENC{1'b1}}; // Had to match this time with the flush time for mispredict to a cp_next
assign cp_next_itag = cp_next_itag_q;
assign iu_lq_i0_completed = cp2_i0_complete_q;
assign iu_lq_i0_completed_itag = cp2_i0_itag_q;
assign iu_lq_i1_completed = cp2_i1_complete_q;
assign iu_lq_i1_completed_itag = cp2_i1_itag_q;
//-----------------------------------------------------------------------------
// Flush
//-----------------------------------------------------------------------------
assign flush_cond = cp3_flush_q | pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | iu_pc_step_done_q | pc_iu_ram_flush_thread_q | flush_hold;
assign iu_flush_cond = (cp3_flush_q & ~cp3_mispredict_q) | pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | iu_pc_step_done_q | pc_iu_ram_flush_thread_q | flush_hold;
assign iu_flush = iu_flush_cond;
assign cp_flush_into_uc_int = cp3_flush_q & (~(cp3_flush2ucode_q)) & cp3_ucode_q & (~(cp3_preissue_q));
assign cp_flush_into_uc = cp_flush_into_uc_int;
assign cp_uc_flush_ifar = cp3_ifar_q[43:61];
assign cp_uc_np1_flush = cp3_np1_flush_q;
assign cp_flush = flush_cond;
assign cp_flush_itag = cp1_i0_itag_q;
assign cp_flush_ifar = ({cp8_rfi_q, cp4_excvec_val_q} == 2'b10) ? cp3_nia_q :
({cp8_rfi_q, cp4_excvec_val_q} == 2'b00) ? cp3_nia_q :
cp4_exc_nia_q;
assign cp_iu0_flush_2ucode = cp_iu0_flush_2ucode_int;
assign cp_iu0_flush_2ucode_int = cp3_flush2ucode_q & ~(pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | pc_iu_ram_flush_thread_q);
assign cp_iu0_flush_2ucode_type = cp3_flush2ucode_type_q & ~(pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | pc_iu_ram_flush_thread_q);
assign cp_iu0_flush_nonspec = iu_flush_cond & cp3_flush_nonspec_q & ~(pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | pc_iu_ram_flush_thread_q);
// Have a hole today for a few cycles from rename till when dispatched is set
assign cp_rn_empty = ~|cp1_dispatched_q;
assign nonspec_release = (nonspec_hit_d | reload_hit_q | ierat_pt_fault_q | ierat_lrat_miss_q | ierat_tlb_inelig_q |
tlb_multihit_err_q | tlb_par_err_q | lru_par_err_q | tlb_miss_q);
assign iu_nonspec_d = ((iu_flush_cond & cp3_flush_nonspec_q) | (~iu_flush_cond & iu_nonspec_q)) & ~nonspec_release;
assign ierat_pt_fault_d = (mm_iu_ierat_rel_val & mm_iu_ierat_pt_fault) | (ierat_pt_fault_q & ~cp3_mm_iu_exception) ;
assign ierat_lrat_miss_d = (mm_iu_ierat_rel_val & mm_iu_ierat_lrat_miss) | (ierat_lrat_miss_q & ~cp3_mm_iu_exception);
assign ierat_tlb_inelig_d = (mm_iu_ierat_rel_val & mm_iu_ierat_tlb_inelig) | (ierat_tlb_inelig_q & ~cp3_mm_iu_exception);
assign tlb_multihit_err_d = (mm_iu_ierat_rel_val & mm_iu_tlb_multihit_err) | (tlb_multihit_err_q & ~cp3_mm_iu_exception);
assign tlb_par_err_d = (mm_iu_ierat_rel_val & mm_iu_tlb_par_err) | (tlb_par_err_q & ~cp3_mm_iu_exception);
assign lru_par_err_d = (mm_iu_ierat_rel_val & mm_iu_lru_par_err) | (lru_par_err_q & ~cp3_mm_iu_exception);
assign tlb_miss_d = (mm_iu_ierat_rel_val & mm_iu_tlb_miss) | (tlb_miss_q & ~cp3_mm_iu_exception);
assign reload_hit_d = mm_iu_reload_hit;
assign nonspec_hit_d = ic_cp_nonspec_hit;
assign lq0_execute_vld_d = lq0_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
assign lq1_execute_vld_d = lq1_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
assign br_execute_vld_d = br_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
assign xu_execute_vld_d = xu_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
assign xu1_execute_vld_d = xu1_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
assign axu0_execute_vld_d = axu0_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
assign axu1_execute_vld_d = axu1_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q);
//-----------------------------------------------------------------------------
// ITAG Decode
//-----------------------------------------------------------------------------
assign lq0_execute_vld = {`CPL_Q_DEPTH{lq0_execute_vld_q}} & decode_a(lq0_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign lq0_recirc_vld = {`CPL_Q_DEPTH{lq0_recirc_val_q}} & decode_a(lq0_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign lq1_execute_vld = {`CPL_Q_DEPTH{lq1_execute_vld_q}} & decode_a(lq1_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign br_execute_vld = {`CPL_Q_DEPTH{br_execute_vld_q}} & decode_a(br_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign xu_execute_vld = {`CPL_Q_DEPTH{xu_execute_vld_q}} & decode_a(xu_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign xu1_execute_vld = {`CPL_Q_DEPTH{xu1_execute_vld_q}} & decode_a(xu1_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign axu0_execute_vld = {`CPL_Q_DEPTH{axu0_execute_vld_q}} & decode_a(axu0_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign axu1_execute_vld = {`CPL_Q_DEPTH{axu1_execute_vld_q}} & decode_a(axu1_itag_q[1:`ITAG_SIZE_ENC - 1]);
assign fold_i0_execute_vld = {`CPL_Q_DEPTH{iu7_i0_is_folded_q}} & cp1_i0_dispatched_delay_q;
assign fold_i1_execute_vld = {`CPL_Q_DEPTH{iu7_i1_is_folded_q}} & cp1_i1_dispatched_delay_q;
assign excvec_act = lq0_execute_vld_q | lq0_recirc_val_q | lq1_execute_vld_q | br_execute_vld_q | xu_execute_vld_q |
xu1_execute_vld_q | axu0_execute_vld_q | axu1_execute_vld_q | iu6_i0_dispatched_q | iu6_i1_dispatched_q;
//-----------------------------------------------------------------------------
// Update Fields on Dispatch
//-----------------------------------------------------------------------------
generate
begin : xhdl0
genvar e;
for (e = 0; e < `CPL_Q_DEPTH ; e = e + 1)
begin : dispatch_update_gen
assign cp0_iu_excvec_val[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_exception_val :
({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_exception_val :
cp1_iu_excvec_val_q[e];
assign cp0_iu_excvec[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_exception :
({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_exception :
cp1_iu_excvec_q[e];
assign cp0_async_block[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_async_block_q :
({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_async_block_q :
cp1_async_block_q[e];
assign cp0_is_br[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_is_br_q :
({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_is_br_q :
cp1_is_br_q[e];
assign cp0_br_add_chk[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_br_add_chk_q :
({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_br_add_chk_q :
cp1_br_add_chk_q[e];
assign cp0_bp_pred[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_bp_pred_q :
({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_bp_pred_q :
cp1_bp_pred_q[e];
end
end
endgenerate
// Debug is special because it is updates on dispatch and completion
// 0 - Unconditional implemented
// 1 - Instruction Complete RTX
// 2 - Branch Taken implemented
// 3 - Interrupt Taken RTX
// 4 - Trap Instruction implemented
// 5:8 - IAC1-4 implemented
// 9:10 - DAC1R, DAC1W implemented
// 11:12- DAC2R, DAC2W implemented
// 13 - Return implemented
// 14:15 - DAC3R, DAC3W implemented
// 16:17- DAC4R, DAC4W implemented
// 18 - Instr Value Comp implemented
assign iu6_i0_db_IAC_IVC_event = iac1_dbg_event[0] | iac2_dbg_event[0] | iac3_dbg_event[0] | iac4_dbg_event[0] | ivc_dbg_event[0];
assign iu6_i1_db_IAC_IVC_event = iac1_dbg_event[1] | iac2_dbg_event[1] | iac3_dbg_event[1] | iac4_dbg_event[1] | ivc_dbg_event[1];
generate
begin : xhdl1
genvar e;
for (e = 0; e < `CPL_Q_DEPTH; e = e + 1)
begin : db_event_cp_gen
assign cp1_db_IAC_IVC_event[e] = cp1_db_events_q[e][5] | cp1_db_events_q[e][6] | cp1_db_events_q[e][7] | cp1_db_events_q[e][8] | cp1_db_events_q[e][18];
assign cp0_db_events[e][0] = 1'b0;
assign cp0_db_events[e][1] = cp1_i0_dispatched[e] ? (icmp_dbg_event[0] & ~iu6_i0_n_flush & ~iu6_i0_db_IAC_IVC_event) :
cp1_i1_dispatched[e] ? (icmp_dbg_event[1] & ~iu6_i1_n_flush & ~iu6_i1_db_IAC_IVC_event) :
lq0_execute_vld[e] ? (cp1_db_events_q[e][1] & ~lq0_n_flush_q & ~cp1_db_IAC_IVC_event[e]) :
lq1_execute_vld[e] ? (cp1_db_events_q[e][1] & ~lq1_n_flush_q & ~cp1_db_IAC_IVC_event[e]) :
xu_execute_vld[e] ? (cp1_db_events_q[e][1] & ~xu_n_flush_q & ~cp1_db_IAC_IVC_event[e]) :
xu1_execute_vld[e] ? (cp1_db_events_q[e][1] & ~cp1_db_IAC_IVC_event[e]) :
axu0_execute_vld[e] ? (cp1_db_events_q[e][1] & ~axu0_n_flush_q & ~cp1_db_IAC_IVC_event[e]) :
axu1_execute_vld[e] ? (cp1_db_events_q[e][1] & ~axu1_n_flush_q & ~cp1_db_IAC_IVC_event[e]) :
br_execute_vld[e] ? (cp1_db_events_q[e][1] & ~cp1_db_IAC_IVC_event[e] & ~brt_dbg_event) :
cp1_db_events_q[e][1];
assign cp0_db_events[e][2] = cp1_i0_dispatched[e] ? 1'b0 :
cp1_i1_dispatched[e] ? 1'b0 :
br_execute_vld[e] ?