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726 lines
28 KiB
Verilog
726 lines
28 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: Pervasive Repower Logic
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(* recursive_synthesis="0" *)
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module c_perv_rp(
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// Include model build parameters
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`include "tri_a2o.vh"
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// inout vdd,
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// inout gnd,
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input clk,
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input rst,
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//CLOCK CONTROLS
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//Top level clock controls
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input an_ac_ccflush_dc,
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input rtim_sl_thold_8,
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input func_sl_thold_8,
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input func_nsl_thold_8,
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input ary_nsl_thold_8,
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input sg_8,
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input fce_8,
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output rtim_sl_thold_7,
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output func_sl_thold_7,
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output func_nsl_thold_7,
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output ary_nsl_thold_7,
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output sg_7,
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output fce_7,
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//Thold inputs from pcq clock controls
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input pc_rp_ccflush_out_dc,
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input pc_rp_gptr_sl_thold_4,
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input pc_rp_time_sl_thold_4,
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input pc_rp_repr_sl_thold_4,
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input pc_rp_abst_sl_thold_4,
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input pc_rp_abst_slp_sl_thold_4,
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input pc_rp_regf_sl_thold_4,
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input pc_rp_regf_slp_sl_thold_4,
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input pc_rp_func_sl_thold_4,
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input pc_rp_func_slp_sl_thold_4,
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input pc_rp_cfg_sl_thold_4,
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input pc_rp_cfg_slp_sl_thold_4,
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input pc_rp_func_nsl_thold_4,
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input pc_rp_func_slp_nsl_thold_4,
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input pc_rp_ary_nsl_thold_4,
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input pc_rp_ary_slp_nsl_thold_4,
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input pc_rp_rtim_sl_thold_4,
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input pc_rp_sg_4,
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input pc_rp_fce_4,
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//Thold outputs to the units
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output rp_iu_ccflush_dc,
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output rp_iu_gptr_sl_thold_3,
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output rp_iu_time_sl_thold_3,
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output rp_iu_repr_sl_thold_3,
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output rp_iu_abst_sl_thold_3,
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output rp_iu_abst_slp_sl_thold_3,
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output rp_iu_regf_slp_sl_thold_3,
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output rp_iu_func_sl_thold_3,
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output rp_iu_func_slp_sl_thold_3,
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output rp_iu_cfg_sl_thold_3,
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output rp_iu_cfg_slp_sl_thold_3,
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output rp_iu_func_nsl_thold_3,
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output rp_iu_func_slp_nsl_thold_3,
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output rp_iu_ary_nsl_thold_3,
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output rp_iu_ary_slp_nsl_thold_3,
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output rp_iu_sg_3,
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output rp_iu_fce_3,
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//
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output rp_rv_ccflush_dc,
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output rp_rv_gptr_sl_thold_3,
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output rp_rv_time_sl_thold_3,
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output rp_rv_repr_sl_thold_3,
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output rp_rv_abst_sl_thold_3,
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output rp_rv_abst_slp_sl_thold_3,
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output rp_rv_func_sl_thold_3,
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output rp_rv_func_slp_sl_thold_3,
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output rp_rv_cfg_sl_thold_3,
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output rp_rv_cfg_slp_sl_thold_3,
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output rp_rv_func_nsl_thold_3,
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output rp_rv_func_slp_nsl_thold_3,
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output rp_rv_ary_nsl_thold_3,
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output rp_rv_ary_slp_nsl_thold_3,
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output rp_rv_sg_3,
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output rp_rv_fce_3,
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//
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output rp_xu_ccflush_dc,
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output rp_xu_gptr_sl_thold_3,
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output rp_xu_time_sl_thold_3,
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output rp_xu_repr_sl_thold_3,
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output rp_xu_abst_sl_thold_3,
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output rp_xu_abst_slp_sl_thold_3,
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output rp_xu_regf_slp_sl_thold_3,
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output rp_xu_func_sl_thold_3,
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output rp_xu_func_slp_sl_thold_3,
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output rp_xu_cfg_sl_thold_3,
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output rp_xu_cfg_slp_sl_thold_3,
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output rp_xu_func_nsl_thold_3,
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output rp_xu_func_slp_nsl_thold_3,
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output rp_xu_ary_nsl_thold_3,
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output rp_xu_ary_slp_nsl_thold_3,
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output rp_xu_sg_3,
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output rp_xu_fce_3,
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//
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output rp_lq_ccflush_dc,
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output rp_lq_gptr_sl_thold_3,
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output rp_lq_time_sl_thold_3,
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output rp_lq_repr_sl_thold_3,
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output rp_lq_abst_sl_thold_3,
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output rp_lq_abst_slp_sl_thold_3,
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output rp_lq_regf_slp_sl_thold_3,
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output rp_lq_func_sl_thold_3,
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output rp_lq_func_slp_sl_thold_3,
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output rp_lq_cfg_sl_thold_3,
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output rp_lq_cfg_slp_sl_thold_3,
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output rp_lq_func_nsl_thold_3,
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output rp_lq_func_slp_nsl_thold_3,
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output rp_lq_ary_nsl_thold_3,
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output rp_lq_ary_slp_nsl_thold_3,
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output rp_lq_sg_3,
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output rp_lq_fce_3,
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//
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output rp_mm_ccflush_dc,
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output rp_mm_gptr_sl_thold_3,
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output rp_mm_time_sl_thold_3,
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output rp_mm_repr_sl_thold_3,
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output rp_mm_abst_sl_thold_3,
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output rp_mm_abst_slp_sl_thold_3,
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output rp_mm_func_sl_thold_3,
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output rp_mm_func_slp_sl_thold_3,
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output rp_mm_cfg_sl_thold_3,
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output rp_mm_cfg_slp_sl_thold_3,
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output rp_mm_func_nsl_thold_3,
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output rp_mm_func_slp_nsl_thold_3,
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output rp_mm_ary_nsl_thold_3,
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output rp_mm_ary_slp_nsl_thold_3,
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output rp_mm_sg_3,
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output rp_mm_fce_3,
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//SCANRING REPOWERING
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input pc_bcfg_scan_in,
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output pc_bcfg_scan_in_q,
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input pc_dcfg_scan_in,
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output pc_dcfg_scan_in_q,
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input pc_bcfg_scan_out,
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output pc_bcfg_scan_out_q,
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input pc_ccfg_scan_out,
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output pc_ccfg_scan_out_q,
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input pc_dcfg_scan_out,
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output pc_dcfg_scan_out_q,
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input [0:1] pc_func_scan_in,
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output [0:1] pc_func_scan_in_q,
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input [0:1] pc_func_scan_out,
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output [0:1] pc_func_scan_out_q,
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//
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input fu_abst_scan_in,
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output fu_abst_scan_in_q,
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input fu_abst_scan_out,
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output fu_abst_scan_out_q,
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input fu_ccfg_scan_out,
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output fu_ccfg_scan_out_q,
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input fu_bcfg_scan_out,
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output fu_bcfg_scan_out_q,
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input fu_dcfg_scan_out,
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output fu_dcfg_scan_out_q,
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input [0:3] fu_func_scan_in,
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output [0:3] fu_func_scan_in_q,
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input [0:3] fu_func_scan_out,
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output [0:3] fu_func_scan_out_q,
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//MISCELLANEOUS FUNCTIONAL SIGNALS
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// node inputs going to pcq
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input an_ac_scom_dch,
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input an_ac_scom_cch,
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input an_ac_checkstop,
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input an_ac_debug_stop,
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input [0:`THREADS-1] an_ac_pm_thread_stop,
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input [0:`THREADS-1] an_ac_pm_fetch_halt,
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//
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output rp_pc_scom_dch_q,
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output rp_pc_scom_cch_q,
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output rp_pc_checkstop_q,
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output rp_pc_debug_stop_q,
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output [0:`THREADS-1] rp_pc_pm_thread_stop_q,
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output [0:`THREADS-1] rp_pc_pm_fetch_halt_q,
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// pcq outputs going to node
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input pc_rp_scom_dch,
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input pc_rp_scom_cch,
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input [0:`THREADS-1] pc_rp_special_attn,
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input [0:2] pc_rp_checkstop,
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input [0:2] pc_rp_local_checkstop,
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input [0:2] pc_rp_recov_err,
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input pc_rp_trace_error,
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input [0:`THREADS-1] pc_rp_pm_thread_running,
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input pc_rp_power_managed,
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input pc_rp_rvwinkle_mode,
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input pc_rp_livelock_active,
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//
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output ac_an_scom_dch_q,
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output ac_an_scom_cch_q,
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output [0:`THREADS-1] ac_an_special_attn_q,
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output [0:2] ac_an_checkstop_q,
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output [0:2] ac_an_local_checkstop_q,
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output [0:2] ac_an_recov_err_q,
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output ac_an_trace_error_q,
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output [0:`THREADS-1] ac_an_pm_thread_running_q,
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output ac_an_power_managed_q,
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output ac_an_rvwinkle_mode_q,
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output ac_an_livelock_active_q,
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// SCAN CHAINS
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input scan_diag_dc,
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input scan_dis_dc_b,
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input func_scan_in,
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input gptr_scan_in,
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output func_scan_out,
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output gptr_scan_out
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);
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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// FUNC Scan Ring
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parameter FUNC2_T0_SIZE = 23;
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parameter FUNC2_T1_SIZE = 4 * (`THREADS - 1);
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// start of func scan chain ordering
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parameter FUNC2_T0_OFFSET = 0;
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parameter FUNC2_T1_OFFSET = FUNC2_T0_OFFSET + FUNC2_T0_SIZE;
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parameter FUNC_RIGHT = FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1;
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// end of func scan chain ordering
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// Power signals
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wire vdd;
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wire gnd;
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assign vdd = 1'b1;
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assign gnd = 1'b0;
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// Clock and Scan Signals
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wire [0:FUNC_RIGHT] func_siv;
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wire [0:FUNC_RIGHT] func_sov;
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//
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wire slat_force;
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wire func_slat_thold_b;
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wire func_slat_d2clk;
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//wire [0:`NCLK_WIDTH-1] func_slat_lclk;
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wire abst_slat_thold_b;
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wire abst_slat_d2clk;
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//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
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wire cfg_slat_thold_b;
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wire cfg_slat_d2clk;
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//wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
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//
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wire sg_3_int;
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wire func_sl_thold_3_int;
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wire func_slp_sl_thold_3_int;
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wire abst_sl_thold_3_int;
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wire gptr_sl_thold_3_int;
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wire cfg_sl_thold_3_int;
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wire sg_2;
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wire func_sl_thold_2;
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wire func_slp_sl_thold_2;
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wire abst_sl_thold_2;
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wire gptr_sl_thold_2;
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wire cfg_sl_thold_2;
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wire sg_1;
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wire func_sl_thold_1;
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wire func_slp_sl_thold_1;
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wire gptr_sl_thold_1;
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wire abst_sl_thold_1;
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wire cfg_sl_thold_1;
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wire sg_0;
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wire func_sl_thold_0;
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wire func_sl_thold_0_b;
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wire force_func;
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wire func_slp_sl_thold_0;
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wire func_slp_sl_thold_0_b;
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wire force_func_slp;
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wire gptr_sl_thold_0;
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wire abst_sl_thold_0;
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wire abst_sl_thold_0_b;
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wire force_abst;
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wire cfg_sl_thold_0;
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//
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wire clkoff_b;
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wire act_dis;
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wire d_mode;
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wire [0:4] delay_lclkr;
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wire [0:4] mpw1_b;
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wire mpw2_b;
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// Get rid of sinkless net messages
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(* analysis_not_referenced="true" *)
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wire unused;
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assign unused = pc_rp_regf_sl_thold_4 | pc_rp_rtim_sl_thold_4 | d_mode | (|delay_lclkr[1:4]) | (|mpw1_b[1:4]);
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// *****************************************************************************
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// INTERNALLY USED CLOCK CONTROLS
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// *****************************************************************************
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// Thold/Sg Staging latches
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tri_plat #(.WIDTH(6)) perv_4to3_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(pc_rp_ccflush_out_dc),
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.din({pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_gptr_sl_thold_4,
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pc_rp_abst_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_sg_4 }),
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.q( {func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int,
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abst_sl_thold_3_int, cfg_sl_thold_3_int, sg_3_int })
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);
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tri_plat #(.WIDTH(6)) perv_3to2_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(pc_rp_ccflush_out_dc),
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.din({func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int,
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abst_sl_thold_3_int, cfg_sl_thold_3_int, sg_3_int }),
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.q( {func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2,
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abst_sl_thold_2, cfg_sl_thold_2, sg_2 })
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);
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tri_plat #(.WIDTH(6)) perv_2to1_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(pc_rp_ccflush_out_dc),
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.din({func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2,
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abst_sl_thold_2, cfg_sl_thold_2, sg_2 }),
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.q( {func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1,
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abst_sl_thold_1, cfg_sl_thold_1, sg_1 })
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);
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tri_plat #(.WIDTH(6)) perv_1to0_reg(
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.vd(vdd),
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.gd(gnd),
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.clk(clk),
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.rst(rst),
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.flush(pc_rp_ccflush_out_dc),
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.din({func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1,
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abst_sl_thold_1, cfg_sl_thold_1, sg_1 }),
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.q( {func_sl_thold_0, func_slp_sl_thold_0, gptr_sl_thold_0,
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abst_sl_thold_0, cfg_sl_thold_0, sg_0 })
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);
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// LCBCNTRL Macro
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tri_lcbcntl_mac perv_lcbcntl(
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.vdd(vdd),
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.gnd(gnd),
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.sg(sg_0),
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.clk(clk),
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.rst(rst),
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.scan_in(gptr_scan_in),
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.scan_diag_dc(scan_diag_dc),
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.thold(gptr_sl_thold_0),
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.clkoff_dc_b(clkoff_b),
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.delay_lclkr_dc(delay_lclkr[0:4]),
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.act_dis_dc(act_dis),
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.d_mode_dc(d_mode),
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.mpw1_dc_b(mpw1_b[0:4]),
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.mpw2_dc_b(mpw2_b),
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.scan_out(gptr_scan_out)
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);
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// LCBORs
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tri_lcbor abst_lcbor(
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.clkoff_b(clkoff_b),
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.thold(abst_sl_thold_0),
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.sg(sg_0),
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.act_dis(act_dis),
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.force_t(force_abst),
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.thold_b(abst_sl_thold_0_b)
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);
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tri_lcbor func_lcbor(
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.clkoff_b(clkoff_b),
|
|
.thold(func_sl_thold_0),
|
|
.sg(sg_0),
|
|
.act_dis(act_dis),
|
|
.force_t(force_func),
|
|
.thold_b(func_sl_thold_0_b)
|
|
);
|
|
|
|
tri_lcbor func_slp_lcbor(
|
|
.clkoff_b(clkoff_b),
|
|
.thold(func_slp_sl_thold_0),
|
|
.sg(sg_0),
|
|
.act_dis(act_dis),
|
|
.force_t(force_func_slp),
|
|
.thold_b(func_slp_sl_thold_0_b)
|
|
);
|
|
|
|
// LCBs for scan only staging latches
|
|
assign slat_force = sg_0;
|
|
assign func_slat_thold_b = (~func_sl_thold_0);
|
|
assign abst_slat_thold_b = (~abst_sl_thold_0);
|
|
assign cfg_slat_thold_b = (~cfg_sl_thold_0);
|
|
|
|
/*
|
|
tri_lcbs lcbs_func(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.delay_lclkr(delay_lclkr[0]),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.force_t(slat_force),
|
|
.thold_b(func_slat_thold_b),
|
|
.dclk(func_slat_d2clk),
|
|
.lclk(func_slat_lclk)
|
|
);
|
|
|
|
tri_lcbs lcbs_abst(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.delay_lclkr(delay_lclkr[0]),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.force_t(slat_force),
|
|
.thold_b(abst_slat_thold_b),
|
|
.dclk(abst_slat_d2clk),
|
|
.lclk(abst_slat_lclk)
|
|
);
|
|
|
|
tri_lcbs lcbs_cfg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.delay_lclkr(delay_lclkr[0]),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.force_t(slat_force),
|
|
.thold_b(cfg_slat_thold_b),
|
|
.dclk(cfg_slat_d2clk),
|
|
.lclk(cfg_slat_lclk)
|
|
);
|
|
*/
|
|
// tri_lcbs dclk=thold lclk=clk,rst
|
|
wire func_slat_lclk, abst_slat_lclk, cfg_slat_lclk;
|
|
assign func_slat_d2clk = 0;
|
|
assign func_slat_lclk = 0;
|
|
assign abst_slat_d2clk = 0;
|
|
assign abst_slat_lclk = 0;
|
|
assign cfg_slat_d2clk = 0;
|
|
assign cfg_slat_lclk = 0;
|
|
|
|
// *****************************************************************************
|
|
// CLOCK REPOWERING LOGIC
|
|
// *****************************************************************************
|
|
// Stages pcq clock control inputs
|
|
tri_plat #(.WIDTH(6)) pcq_lvl8to7(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.flush(an_ac_ccflush_dc),
|
|
.din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8,
|
|
ary_nsl_thold_8, sg_8, fce_8 }),
|
|
|
|
.q( {rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7,
|
|
ary_nsl_thold_7, sg_7, fce_7 })
|
|
);
|
|
|
|
// Other units use the ccflush signal after being gated for power-savings operation
|
|
assign rp_iu_ccflush_dc = pc_rp_ccflush_out_dc;
|
|
assign rp_rv_ccflush_dc = pc_rp_ccflush_out_dc;
|
|
assign rp_xu_ccflush_dc = pc_rp_ccflush_out_dc;
|
|
assign rp_lq_ccflush_dc = pc_rp_ccflush_out_dc;
|
|
assign rp_mm_ccflush_dc = pc_rp_ccflush_out_dc;
|
|
|
|
// Clock control 4to3 output staging
|
|
tri_plat #(.WIDTH(16)) iu_clkstg_4to3(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.flush(pc_rp_ccflush_out_dc),
|
|
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
|
|
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
|
|
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
|
|
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
|
|
pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
|
|
|
|
.q( {rp_iu_gptr_sl_thold_3, rp_iu_time_sl_thold_3, rp_iu_repr_sl_thold_3,
|
|
rp_iu_abst_sl_thold_3, rp_iu_abst_slp_sl_thold_3, rp_iu_regf_slp_sl_thold_3,
|
|
rp_iu_func_sl_thold_3, rp_iu_func_slp_sl_thold_3, rp_iu_cfg_sl_thold_3,
|
|
rp_iu_cfg_slp_sl_thold_3, rp_iu_func_nsl_thold_3, rp_iu_func_slp_nsl_thold_3,
|
|
rp_iu_ary_nsl_thold_3, rp_iu_ary_slp_nsl_thold_3, rp_iu_sg_3, rp_iu_fce_3 })
|
|
);
|
|
|
|
tri_plat #(.WIDTH(15)) rv_clkstg_4to3(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.flush(pc_rp_ccflush_out_dc),
|
|
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
|
|
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
|
|
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,
|
|
pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, pc_rp_ary_nsl_thold_4,
|
|
pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
|
|
|
|
.q( {rp_rv_gptr_sl_thold_3, rp_rv_time_sl_thold_3, rp_rv_repr_sl_thold_3,
|
|
rp_rv_abst_sl_thold_3, rp_rv_abst_slp_sl_thold_3, rp_rv_func_sl_thold_3,
|
|
rp_rv_func_slp_sl_thold_3, rp_rv_cfg_sl_thold_3, rp_rv_cfg_slp_sl_thold_3,
|
|
rp_rv_func_nsl_thold_3, rp_rv_func_slp_nsl_thold_3, rp_rv_ary_nsl_thold_3,
|
|
rp_rv_ary_slp_nsl_thold_3, rp_rv_sg_3, rp_rv_fce_3 })
|
|
);
|
|
|
|
tri_plat #(.WIDTH(16)) xu_clkstg_4to3(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.flush(pc_rp_ccflush_out_dc),
|
|
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
|
|
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
|
|
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
|
|
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
|
|
pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
|
|
|
|
.q( {rp_xu_gptr_sl_thold_3, rp_xu_time_sl_thold_3, rp_xu_repr_sl_thold_3,
|
|
rp_xu_abst_sl_thold_3, rp_xu_abst_slp_sl_thold_3, rp_xu_regf_slp_sl_thold_3,
|
|
rp_xu_func_sl_thold_3, rp_xu_func_slp_sl_thold_3, rp_xu_cfg_sl_thold_3,
|
|
rp_xu_cfg_slp_sl_thold_3, rp_xu_func_nsl_thold_3, rp_xu_func_slp_nsl_thold_3,
|
|
rp_xu_ary_nsl_thold_3, rp_xu_ary_slp_nsl_thold_3, rp_xu_sg_3, rp_xu_fce_3 })
|
|
);
|
|
|
|
tri_plat #(.WIDTH(16)) lq_clkstg_4to3(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.flush(pc_rp_ccflush_out_dc),
|
|
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
|
|
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
|
|
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
|
|
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
|
|
pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
|
|
|
|
.q( {rp_lq_gptr_sl_thold_3, rp_lq_time_sl_thold_3, rp_lq_repr_sl_thold_3,
|
|
rp_lq_abst_sl_thold_3, rp_lq_abst_slp_sl_thold_3, rp_lq_regf_slp_sl_thold_3,
|
|
rp_lq_func_sl_thold_3, rp_lq_func_slp_sl_thold_3, rp_lq_cfg_sl_thold_3,
|
|
rp_lq_cfg_slp_sl_thold_3, rp_lq_func_nsl_thold_3, rp_lq_func_slp_nsl_thold_3,
|
|
rp_lq_ary_nsl_thold_3, rp_lq_ary_slp_nsl_thold_3, rp_lq_sg_3, rp_lq_fce_3 })
|
|
);
|
|
|
|
tri_plat #(.WIDTH(15)) mm_clkstg_4to3(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.flush(pc_rp_ccflush_out_dc),
|
|
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
|
|
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
|
|
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,
|
|
pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, pc_rp_ary_nsl_thold_4,
|
|
pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }),
|
|
|
|
.q( {rp_mm_gptr_sl_thold_3, rp_mm_time_sl_thold_3, rp_mm_repr_sl_thold_3,
|
|
rp_mm_abst_sl_thold_3, rp_mm_abst_slp_sl_thold_3, rp_mm_func_sl_thold_3,
|
|
rp_mm_func_slp_sl_thold_3, rp_mm_cfg_sl_thold_3, rp_mm_cfg_slp_sl_thold_3,
|
|
rp_mm_func_nsl_thold_3, rp_mm_func_slp_nsl_thold_3, rp_mm_ary_nsl_thold_3,
|
|
rp_mm_ary_slp_nsl_thold_3, rp_mm_sg_3, rp_mm_fce_3 })
|
|
);
|
|
|
|
// *****************************************************************************
|
|
// SCANRING REPOWERING
|
|
// *****************************************************************************
|
|
// Staging latches for scan_in/out signals on abist rings
|
|
tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) fu_abst_stg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.dclk(abst_slat_d2clk),
|
|
.lclk(abst_slat_lclk),
|
|
.scan_in( {fu_abst_scan_in, fu_abst_scan_out }),
|
|
.scan_out({fu_abst_scan_in_q, fu_abst_scan_out_q })
|
|
);
|
|
|
|
// Staging latches for scan_in/out signals on func rings
|
|
tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) pc_func_stg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.dclk(func_slat_d2clk),
|
|
.lclk(func_slat_lclk),
|
|
.scan_in( {pc_func_scan_in[0:1], pc_func_scan_out[0:1] }),
|
|
.scan_out({pc_func_scan_in_q[0:1], pc_func_scan_out_q[0:1] })
|
|
);
|
|
|
|
tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) fu_func_stg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.dclk(func_slat_d2clk),
|
|
.lclk(func_slat_lclk),
|
|
.scan_in( {fu_func_scan_in[0:3], fu_func_scan_out[0:3] }),
|
|
.scan_out({fu_func_scan_in_q[0:3], fu_func_scan_out_q[0:3] })
|
|
);
|
|
|
|
// Staging latches for scan_in/out signals on config rings
|
|
tri_slat_scan #(.WIDTH(5), .INIT(5'b00000)) pc_cfg_stg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.dclk(cfg_slat_d2clk),
|
|
.lclk(cfg_slat_lclk),
|
|
|
|
.scan_in( {pc_bcfg_scan_in, pc_dcfg_scan_in, pc_bcfg_scan_out,
|
|
pc_ccfg_scan_out, pc_dcfg_scan_out }),
|
|
|
|
.scan_out({pc_bcfg_scan_in_q, pc_dcfg_scan_in_q, pc_bcfg_scan_out_q,
|
|
pc_ccfg_scan_out_q, pc_dcfg_scan_out_q })
|
|
);
|
|
|
|
tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) fu_cfg_stg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.dclk(cfg_slat_d2clk),
|
|
.lclk(cfg_slat_lclk),
|
|
.scan_in( {fu_bcfg_scan_out, fu_ccfg_scan_out, fu_dcfg_scan_out }),
|
|
.scan_out({fu_bcfg_scan_out_q, fu_ccfg_scan_out_q, fu_dcfg_scan_out_q })
|
|
);
|
|
|
|
// *****************************************************************************
|
|
// MISCELLANEOUS FUNCTIONAL SIGNALS
|
|
// *****************************************************************************
|
|
tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.act(1'b1),
|
|
.thold_b(func_slp_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.force_t(force_func_slp),
|
|
.delay_lclkr(delay_lclkr[0]),
|
|
.mpw1_b(mpw1_b[0]),
|
|
.mpw2_b(mpw2_b),
|
|
.scin(func_siv[ FUNC2_T0_OFFSET:FUNC2_T0_OFFSET + FUNC2_T0_SIZE - 1]),
|
|
.scout(func_sov[FUNC2_T0_OFFSET:FUNC2_T0_OFFSET + FUNC2_T0_SIZE - 1]),
|
|
|
|
.din( {an_ac_scom_dch, an_ac_scom_cch, an_ac_checkstop,
|
|
an_ac_debug_stop, pc_rp_scom_dch, pc_rp_scom_cch,
|
|
pc_rp_checkstop, pc_rp_local_checkstop, pc_rp_recov_err,
|
|
pc_rp_power_managed, pc_rp_rvwinkle_mode, pc_rp_trace_error,
|
|
pc_rp_livelock_active, an_ac_pm_thread_stop[0], pc_rp_pm_thread_running[0],
|
|
pc_rp_special_attn[0], an_ac_pm_fetch_halt[0] }),
|
|
|
|
.dout({rp_pc_scom_dch_q, rp_pc_scom_cch_q, rp_pc_checkstop_q,
|
|
rp_pc_debug_stop_q, ac_an_scom_dch_q, ac_an_scom_cch_q,
|
|
ac_an_checkstop_q, ac_an_local_checkstop_q, ac_an_recov_err_q,
|
|
ac_an_power_managed_q, ac_an_rvwinkle_mode_q, ac_an_trace_error_q,
|
|
ac_an_livelock_active_q, rp_pc_pm_thread_stop_q[0], ac_an_pm_thread_running_q[0],
|
|
ac_an_special_attn_q[0], rp_pc_pm_fetch_halt_q[0] })
|
|
);
|
|
|
|
generate
|
|
if (`THREADS == 2)
|
|
begin : t1_rp
|
|
tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.act(1'b1),
|
|
.thold_b(func_slp_sl_thold_0_b),
|
|
.sg(sg_0),
|
|
.force_t(force_func_slp),
|
|
.delay_lclkr(delay_lclkr[0]),
|
|
.mpw1_b(mpw1_b[0]),
|
|
.mpw2_b(mpw2_b),
|
|
.scin(func_siv[ FUNC2_T1_OFFSET:FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1]),
|
|
.scout(func_sov[FUNC2_T1_OFFSET:FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1]),
|
|
|
|
.din( {an_ac_pm_thread_stop[1], pc_rp_pm_thread_running[1], pc_rp_special_attn[1],
|
|
an_ac_pm_fetch_halt[1] }),
|
|
.dout({rp_pc_pm_thread_stop_q[1], ac_an_pm_thread_running_q[1], ac_an_special_attn_q[1],
|
|
rp_pc_pm_fetch_halt_q[1] })
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
// *****************************************************************************
|
|
// SCAN RING CONNECTIONS
|
|
// *****************************************************************************
|
|
//func ring
|
|
assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]};
|
|
assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b;
|
|
|
|
|
|
endmodule
|