//--------------------------------------------------------------------------------
// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H

#ifndef ROM_BASE
#define ROM_BASE 0x00000000L
#define ROM_SIZE 0x00010000
#endif

#ifndef SRAM_BASE
#define SRAM_BASE 0x00010000L
#define SRAM_SIZE 0x00010000
#endif

#ifndef MAIN_RAM_BASE
#define MAIN_RAM_BASE 0x01000000L
#define MAIN_RAM_SIZE 0x01000000
#endif

#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#define CSR_SIZE 0x00010000
#endif

#ifndef MEM_REGIONS
#define MEM_REGIONS "ROM       0x00000000 0x10000 \nSRAM      0x00010000 0x10000 \nMAIN_RAM  0x01000000 0x1000000 \nCSR       0xfff00000 0x10000 "
#endif
#endif