diff --git a/dev/synth/yosys-0.16+63.txt b/dev/synth/yosys-0.16+63.txt new file mode 100644 index 0000000..919a6c6 --- /dev/null +++ b/dev/synth/yosys-0.16+63.txt @@ -0,0 +1,160840 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2020 Claire Xenia Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.16+63 (git sha1 UNKNOWN, gcc 9.4.0-1ubuntu1~20.04.1 -fPIC -Os) + + +-- Executing script file `synth.yo' -- + +1. Executing Verilog-2005 frontend: ../verilog/unisims_synth +Parsing Verilog input from `../verilog/unisims_synth' to AST representation. +Successfully finished Verilog frontend. + +2. Executing Verilog-2005 frontend: ../verilog/trilib/tri.vh +Parsing Verilog input from `../verilog/trilib/tri.vh' to AST representation. +Successfully finished Verilog frontend. + +3. Executing Verilog-2005 frontend: ../verilog/trilib/tri_128x168_1w_0.v +Parsing Verilog input from `../verilog/trilib/tri_128x168_1w_0.v' to AST representation. +Generating RTLIL representation for module `\tri_128x168_1w_0'. +Successfully finished Verilog frontend. + +4. Executing Verilog-2005 frontend: ../verilog/trilib/tri_128x16_1r1w_1.v +Parsing Verilog input from `../verilog/trilib/tri_128x16_1r1w_1.v' to AST representation. +Generating RTLIL representation for module `\tri_128x16_1r1w_1'. +Successfully finished Verilog frontend. + +5. Executing Verilog-2005 frontend: ../verilog/trilib/tri_128x34_4w_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_128x34_4w_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_128x34_4w_1r1w'. +Successfully finished Verilog frontend. + +6. Executing Verilog-2005 frontend: ../verilog/trilib/tri_144x78_2r4w.v +Parsing Verilog input from `../verilog/trilib/tri_144x78_2r4w.v' to AST representation. +Generating RTLIL representation for module `\tri_144x78_2r4w'. +Successfully finished Verilog frontend. + +7. Executing Verilog-2005 frontend: ../verilog/trilib/tri_256x144_8w_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_256x144_8w_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_256x144_8w_1r1w'. +Successfully finished Verilog frontend. + +8. Executing Verilog-2005 frontend: ../verilog/trilib/tri_32x70_2w_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_32x70_2w_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_32x70_2w_1r1w'. +Successfully finished Verilog frontend. + +9. Executing Verilog-2005 frontend: ../verilog/trilib/tri_512x162_4w_0.v +Parsing Verilog input from `../verilog/trilib/tri_512x162_4w_0.v' to AST representation. +Generating RTLIL representation for module `\tri_512x162_4w_0'. +Successfully finished Verilog frontend. + +10. Executing Verilog-2005 frontend: ../verilog/trilib/tri_512x16_1r1w_1.v +Parsing Verilog input from `../verilog/trilib/tri_512x16_1r1w_1.v' to AST representation. +Generating RTLIL representation for module `\tri_512x16_1r1w_1'. +Successfully finished Verilog frontend. + +11. Executing Verilog-2005 frontend: ../verilog/trilib/tri_64x144_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_64x144_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_64x144_1r1w'. +Successfully finished Verilog frontend. + +12. Executing Verilog-2005 frontend: ../verilog/trilib/tri_64x34_8w_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_64x34_8w_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_64x34_8w_1r1w'. +Successfully finished Verilog frontend. + +13. Executing Verilog-2005 frontend: ../verilog/trilib/tri_64x72_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_64x72_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_64x72_1r1w'. +Successfully finished Verilog frontend. + +14. Executing Verilog-2005 frontend: ../verilog/trilib/tri_a2o.vh +Parsing Verilog input from `../verilog/trilib/tri_a2o.vh' to AST representation. +Successfully finished Verilog frontend. + +15. Executing Verilog-2005 frontend: ../verilog/trilib/tri_addrcmp.v +Parsing Verilog input from `../verilog/trilib/tri_addrcmp.v' to AST representation. +Generating RTLIL representation for module `\tri_addrcmp'. +Successfully finished Verilog frontend. + +16. Executing Verilog-2005 frontend: ../verilog/trilib/tri_agecmp.v +Parsing Verilog input from `../verilog/trilib/tri_agecmp.v' to AST representation. +Generating RTLIL representation for module `\tri_agecmp'. +Successfully finished Verilog frontend. + +17. Executing Verilog-2005 frontend: ../verilog/trilib/tri_aoi21.v +Parsing Verilog input from `../verilog/trilib/tri_aoi21.v' to AST representation. +Generating RTLIL representation for module `\tri_aoi21'. +Successfully finished Verilog frontend. + +18. Executing Verilog-2005 frontend: ../verilog/trilib/tri_aoi22.v +Parsing Verilog input from `../verilog/trilib/tri_aoi22.v' to AST representation. +Generating RTLIL representation for module `\tri_aoi22'. +Successfully finished Verilog frontend. + +19. Executing Verilog-2005 frontend: ../verilog/trilib/tri_aoi22_nlats_wlcb.v +Parsing Verilog input from `../verilog/trilib/tri_aoi22_nlats_wlcb.v' to AST representation. +Generating RTLIL representation for module `\tri_aoi22_nlats_wlcb'. +Successfully finished Verilog frontend. + +20. Executing Verilog-2005 frontend: ../verilog/trilib/tri_bht_1024x8_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_bht_1024x8_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_bht_1024x8_1r1w'. +Successfully finished Verilog frontend. + +21. Executing Verilog-2005 frontend: ../verilog/trilib/tri_bht_512x4_1r1w.v +Parsing Verilog input from `../verilog/trilib/tri_bht_512x4_1r1w.v' to AST representation. +Generating RTLIL representation for module `\tri_bht_512x4_1r1w'. +Successfully finished Verilog frontend. + +22. Executing Verilog-2005 frontend: ../verilog/trilib/tri_bthmx.v +Parsing Verilog input from `../verilog/trilib/tri_bthmx.v' to AST representation. +Generating RTLIL representation for module `\tri_bthmx'. +Successfully finished Verilog frontend. + +23. Executing Verilog-2005 frontend: ../verilog/trilib/tri_cam_16x143_1r1w1c.v +Parsing Verilog input from `../verilog/trilib/tri_cam_16x143_1r1w1c.v' to AST representation. +Generating RTLIL representation for module `\tri_cam_16x143_1r1w1c'. +Successfully finished Verilog frontend. + +24. Executing Verilog-2005 frontend: ../verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v +Parsing Verilog input from `../verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v' to AST representation. +Generating RTLIL representation for module `\tri_cam_16x143_1r1w1c_matchline'. +Successfully finished Verilog frontend. + +25. Executing Verilog-2005 frontend: ../verilog/trilib/tri_cam_32x143_1r1w1c.v +Parsing Verilog input from `../verilog/trilib/tri_cam_32x143_1r1w1c.v' to AST representation. +Generating RTLIL representation for module `\tri_cam_32x143_1r1w1c'. +Successfully finished Verilog frontend. + +26. Executing Verilog-2005 frontend: ../verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v +Parsing Verilog input from `../verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v' to AST representation. +Generating RTLIL representation for module `\tri_cam_32x143_1r1w1c_matchline'. +Successfully finished Verilog frontend. + +27. Executing Verilog-2005 frontend: ../verilog/trilib/tri_csa22.v +Parsing Verilog input from `../verilog/trilib/tri_csa22.v' to AST representation. +Generating RTLIL representation for module `\tri_csa22'. +Successfully finished Verilog frontend. + +28. Executing Verilog-2005 frontend: ../verilog/trilib/tri_csa32.v +Parsing Verilog input from `../verilog/trilib/tri_csa32.v' to AST representation. +Generating RTLIL representation for module `\tri_csa32'. +Successfully finished Verilog frontend. + +29. Executing Verilog-2005 frontend: ../verilog/trilib/tri_csa42.v +Parsing Verilog input from `../verilog/trilib/tri_csa42.v' to AST representation. +Generating RTLIL representation for module `\tri_csa42'. +Successfully finished Verilog frontend. + +30. Executing Verilog-2005 frontend: ../verilog/trilib/tri_debug_mux16.v +Parsing Verilog input from `../verilog/trilib/tri_debug_mux16.v' to AST representation. +Generating RTLIL representation for module `\tri_debug_mux16'. +Successfully finished Verilog frontend. + +31. Executing Verilog-2005 frontend: ../verilog/trilib/tri_debug_mux32.v +Parsing Verilog input from `../verilog/trilib/tri_debug_mux32.v' to AST representation. +Generating RTLIL representation for module `\tri_debug_mux32'. +Successfully finished Verilog frontend. + +32. Executing Verilog-2005 frontend: ../verilog/trilib/tri_debug_mux4.v +Parsing Verilog input from `../verilog/trilib/tri_debug_mux4.v' to AST representation. +Generating RTLIL representation for module `\tri_debug_mux4'. +Successfully finished Verilog frontend. + +33. Executing Verilog-2005 frontend: ../verilog/trilib/tri_debug_mux8.v +Parsing Verilog input from `../verilog/trilib/tri_debug_mux8.v' to AST representation. +Generating RTLIL representation for module `\tri_debug_mux8'. +Successfully finished Verilog frontend. + +34. Executing Verilog-2005 frontend: ../verilog/trilib/tri_direct_err_rpt.v +Parsing Verilog input from `../verilog/trilib/tri_direct_err_rpt.v' to AST representation. +Generating RTLIL representation for module `\tri_direct_err_rpt'. +Successfully finished Verilog frontend. + +35. Executing Verilog-2005 frontend: ../verilog/trilib/tri_eccchk.v +Parsing Verilog input from `../verilog/trilib/tri_eccchk.v' to AST representation. +Generating RTLIL representation for module `\tri_eccchk'. +Successfully finished Verilog frontend. + +36. Executing Verilog-2005 frontend: ../verilog/trilib/tri_eccgen.v +Parsing Verilog input from `../verilog/trilib/tri_eccgen.v' to AST representation. +Generating RTLIL representation for module `\tri_eccgen'. +Successfully finished Verilog frontend. + +37. Executing Verilog-2005 frontend: ../verilog/trilib/tri_err_rpt.v +Parsing Verilog input from `../verilog/trilib/tri_err_rpt.v' to AST representation. +Generating RTLIL representation for module `\tri_err_rpt'. +Successfully finished Verilog frontend. + +38. Executing Verilog-2005 frontend: ../verilog/trilib/tri_event_mux1t.v +Parsing Verilog input from `../verilog/trilib/tri_event_mux1t.v' to AST representation. +Generating RTLIL representation for module `\tri_event_mux1t'. +Successfully finished Verilog frontend. + +39. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_csa22_h2.v +Parsing Verilog input from `../verilog/trilib/tri_fu_csa22_h2.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_csa22_h2'. +Successfully finished Verilog frontend. + +40. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_mul.v +Parsing Verilog input from `../verilog/trilib/tri_fu_mul.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_mul'. +Successfully finished Verilog frontend. + +41. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_mul_62.v +Parsing Verilog input from `../verilog/trilib/tri_fu_mul_62.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_mul_62'. +Successfully finished Verilog frontend. + +42. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_mul_92.v +Parsing Verilog input from `../verilog/trilib/tri_fu_mul_92.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_mul_92'. +Successfully finished Verilog frontend. + +43. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_mul_bthdcd.v +Parsing Verilog input from `../verilog/trilib/tri_fu_mul_bthdcd.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_mul_bthdcd'. +Successfully finished Verilog frontend. + +44. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_mul_bthmux.v +Parsing Verilog input from `../verilog/trilib/tri_fu_mul_bthmux.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_mul_bthmux'. +Successfully finished Verilog frontend. + +45. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_mul_bthrow.v +Parsing Verilog input from `../verilog/trilib/tri_fu_mul_bthrow.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_mul_bthrow'. +Successfully finished Verilog frontend. + +46. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_tblmul.v +Parsing Verilog input from `../verilog/trilib/tri_fu_tblmul.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_tblmul'. +Successfully finished Verilog frontend. + +47. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_tblmul_bthdcd.v +Parsing Verilog input from `../verilog/trilib/tri_fu_tblmul_bthdcd.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_tblmul_bthdcd'. +Successfully finished Verilog frontend. + +48. Executing Verilog-2005 frontend: ../verilog/trilib/tri_fu_tblmul_bthrow.v +Parsing Verilog input from `../verilog/trilib/tri_fu_tblmul_bthrow.v' to AST representation. +Generating RTLIL representation for module `\tri_fu_tblmul_bthrow'. +Successfully finished Verilog frontend. + +49. Executing Verilog-2005 frontend: ../verilog/trilib/tri_inv.v +Parsing Verilog input from `../verilog/trilib/tri_inv.v' to AST representation. +Generating RTLIL representation for module `\tri_inv'. +Successfully finished Verilog frontend. + +50. Executing Verilog-2005 frontend: ../verilog/trilib/tri_inv_nlats.v +Parsing Verilog input from `../verilog/trilib/tri_inv_nlats.v' to AST representation. +Generating RTLIL representation for module `\tri_inv_nlats'. +Successfully finished Verilog frontend. + +51. Executing Verilog-2005 frontend: ../verilog/trilib/tri_iuq_cpl_arr.v +Parsing Verilog input from `../verilog/trilib/tri_iuq_cpl_arr.v' to AST representation. +Generating RTLIL representation for module `\tri_iuq_cpl_arr'. +Successfully finished Verilog frontend. + +52. Executing Verilog-2005 frontend: ../verilog/trilib/tri_lcbcntl_array_mac.v +Parsing Verilog input from `../verilog/trilib/tri_lcbcntl_array_mac.v' to AST representation. +Generating RTLIL representation for module `\tri_lcbcntl_array_mac'. +Successfully finished Verilog frontend. + +53. Executing Verilog-2005 frontend: ../verilog/trilib/tri_lcbcntl_mac.v +Parsing Verilog input from `../verilog/trilib/tri_lcbcntl_mac.v' to AST representation. +Generating RTLIL representation for module `\tri_lcbcntl_mac'. +Successfully finished Verilog frontend. + +54. Executing Verilog-2005 frontend: ../verilog/trilib/tri_lcbnd.v +Parsing Verilog input from `../verilog/trilib/tri_lcbnd.v' to AST representation. +Generating RTLIL representation for module `\tri_lcbnd'. +Successfully finished Verilog frontend. + +55. Executing Verilog-2005 frontend: ../verilog/trilib/tri_lcbor.v +Parsing Verilog input from `../verilog/trilib/tri_lcbor.v' to AST representation. +Generating RTLIL representation for module `\tri_lcbor'. +Successfully finished Verilog frontend. + +56. Executing Verilog-2005 frontend: ../verilog/trilib/tri_lcbs.v +Parsing Verilog input from `../verilog/trilib/tri_lcbs.v' to AST representation. +Generating RTLIL representation for module `\tri_lcbs'. +Successfully finished Verilog frontend. + +57. Executing Verilog-2005 frontend: ../verilog/trilib/tri_lq_rmw.v +Parsing Verilog input from `../verilog/trilib/tri_lq_rmw.v' to AST representation. +Generating RTLIL representation for module `\tri_lq_rmw'. +Successfully finished Verilog frontend. + +58. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nand2.v +Parsing Verilog input from `../verilog/trilib/tri_nand2.v' to AST representation. +Generating RTLIL representation for module `\tri_nand2'. +Successfully finished Verilog frontend. + +59. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nand2_nlats.v +Parsing Verilog input from `../verilog/trilib/tri_nand2_nlats.v' to AST representation. +Generating RTLIL representation for module `\tri_nand2_nlats'. +Successfully finished Verilog frontend. + +60. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nand3.v +Parsing Verilog input from `../verilog/trilib/tri_nand3.v' to AST representation. +Generating RTLIL representation for module `\tri_nand3'. +Successfully finished Verilog frontend. + +61. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nand4.v +Parsing Verilog input from `../verilog/trilib/tri_nand4.v' to AST representation. +Generating RTLIL representation for module `\tri_nand4'. +Successfully finished Verilog frontend. + +62. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nlat.v +Parsing Verilog input from `../verilog/trilib/tri_nlat.v' to AST representation. +Generating RTLIL representation for module `\tri_nlat'. +Successfully finished Verilog frontend. + +63. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nlat_scan.v +Parsing Verilog input from `../verilog/trilib/tri_nlat_scan.v' to AST representation. +Generating RTLIL representation for module `\tri_nlat_scan'. +Successfully finished Verilog frontend. + +64. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nor2.v +Parsing Verilog input from `../verilog/trilib/tri_nor2.v' to AST representation. +Generating RTLIL representation for module `\tri_nor2'. +Successfully finished Verilog frontend. + +65. Executing Verilog-2005 frontend: ../verilog/trilib/tri_nor3.v +Parsing Verilog input from `../verilog/trilib/tri_nor3.v' to AST representation. +Generating RTLIL representation for module `\tri_nor3'. +Successfully finished Verilog frontend. + +66. Executing Verilog-2005 frontend: ../verilog/trilib/tri_oai21.v +Parsing Verilog input from `../verilog/trilib/tri_oai21.v' to AST representation. +Generating RTLIL representation for module `\tri_oai21'. +Successfully finished Verilog frontend. + +67. Executing Verilog-2005 frontend: ../verilog/trilib/tri_parity_recovery.v +Parsing Verilog input from `../verilog/trilib/tri_parity_recovery.v' to AST representation. +Generating RTLIL representation for module `\tri_parity_recovery'. +Successfully finished Verilog frontend. + +68. Executing Verilog-2005 frontend: ../verilog/trilib/tri_plat.v +Parsing Verilog input from `../verilog/trilib/tri_plat.v' to AST representation. +Generating RTLIL representation for module `\tri_plat'. +Successfully finished Verilog frontend. + +69. Executing Verilog-2005 frontend: ../verilog/trilib/tri_pri.v +Parsing Verilog input from `../verilog/trilib/tri_pri.v' to AST representation. +Generating RTLIL representation for module `\tri_pri'. +Successfully finished Verilog frontend. + +70. Executing Verilog-2005 frontend: ../verilog/trilib/tri_regk.v +Parsing Verilog input from `../verilog/trilib/tri_regk.v' to AST representation. +Generating RTLIL representation for module `\tri_regk'. +Successfully finished Verilog frontend. + +71. Executing Verilog-2005 frontend: ../verilog/trilib/tri_regs.v +Parsing Verilog input from `../verilog/trilib/tri_regs.v' to AST representation. +Generating RTLIL representation for module `\tri_regs'. +Successfully finished Verilog frontend. + +72. Executing Verilog-2005 frontend: ../verilog/trilib/tri_rlmlatch_p.v +Parsing Verilog input from `../verilog/trilib/tri_rlmlatch_p.v' to AST representation. +Generating RTLIL representation for module `\tri_rlmlatch_p'. +Successfully finished Verilog frontend. + +73. Executing Verilog-2005 frontend: ../verilog/trilib/tri_rlmreg_p.v +Parsing Verilog input from `../verilog/trilib/tri_rlmreg_p.v' to AST representation. +Generating RTLIL representation for module `\tri_rlmreg_p'. +Successfully finished Verilog frontend. + +74. Executing Verilog-2005 frontend: ../verilog/trilib/tri_rot16_lu.v +Parsing Verilog input from `../verilog/trilib/tri_rot16_lu.v' to AST representation. +Generating RTLIL representation for module `\tri_rot16_lu'. +Successfully finished Verilog frontend. + +75. Executing Verilog-2005 frontend: ../verilog/trilib/tri_rot16_ru.v +Parsing Verilog input from `../verilog/trilib/tri_rot16_ru.v' to AST representation. +Generating RTLIL representation for module `\tri_rot16_ru'. +Successfully finished Verilog frontend. + +76. Executing Verilog-2005 frontend: ../verilog/trilib/tri_rot16s_ru.v +Parsing Verilog input from `../verilog/trilib/tri_rot16s_ru.v' to AST representation. +Generating RTLIL representation for module `\tri_rot16s_ru'. +Successfully finished Verilog frontend. + +77. Executing Verilog-2005 frontend: ../verilog/trilib/tri_scom_addr_decode.v +Parsing Verilog input from `../verilog/trilib/tri_scom_addr_decode.v' to AST representation. +Generating RTLIL representation for module `\tri_scom_addr_decode'. +Successfully finished Verilog frontend. + +78. Executing Verilog-2005 frontend: ../verilog/trilib/tri_ser_rlmreg_p.v +Parsing Verilog input from `../verilog/trilib/tri_ser_rlmreg_p.v' to AST representation. +Generating RTLIL representation for module `\tri_ser_rlmreg_p'. +Successfully finished Verilog frontend. + +79. Executing Verilog-2005 frontend: ../verilog/trilib/tri_serial_scom2.v +Parsing Verilog input from `../verilog/trilib/tri_serial_scom2.v' to AST representation. +Generating RTLIL representation for module `\tri_serial_scom2'. +Successfully finished Verilog frontend. + +80. Executing Verilog-2005 frontend: ../verilog/trilib/tri_slat_scan.v +Parsing Verilog input from `../verilog/trilib/tri_slat_scan.v' to AST representation. +Generating RTLIL representation for module `\tri_slat_scan'. +Successfully finished Verilog frontend. + +81. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_add.v +Parsing Verilog input from `../verilog/trilib/tri_st_add.v' to AST representation. +Generating RTLIL representation for module `\tri_st_add'. +Successfully finished Verilog frontend. + +82. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_add_csmux.v +Parsing Verilog input from `../verilog/trilib/tri_st_add_csmux.v' to AST representation. +Generating RTLIL representation for module `\tri_st_add_csmux'. +Successfully finished Verilog frontend. + +83. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_add_glbglbci.v +Parsing Verilog input from `../verilog/trilib/tri_st_add_glbglbci.v' to AST representation. +Generating RTLIL representation for module `\tri_st_add_glbglbci'. +Successfully finished Verilog frontend. + +84. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_add_glbloc.v +Parsing Verilog input from `../verilog/trilib/tri_st_add_glbloc.v' to AST representation. +Generating RTLIL representation for module `\tri_st_add_glbloc'. +Successfully finished Verilog frontend. + +85. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_add_loc.v +Parsing Verilog input from `../verilog/trilib/tri_st_add_loc.v' to AST representation. +Generating RTLIL representation for module `\tri_st_add_loc'. +Successfully finished Verilog frontend. + +86. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_cntlz.v +Parsing Verilog input from `../verilog/trilib/tri_st_cntlz.v' to AST representation. +Generating RTLIL representation for module `\tri_st_cntlz'. +Successfully finished Verilog frontend. + +87. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_cntlz_8b.v +Parsing Verilog input from `../verilog/trilib/tri_st_cntlz_8b.v' to AST representation. +Generating RTLIL representation for module `\tri_st_cntlz_8b'. +Successfully finished Verilog frontend. + +88. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_mult.v +Parsing Verilog input from `../verilog/trilib/tri_st_mult.v' to AST representation. +Generating RTLIL representation for module `\tri_st_mult'. +Successfully finished Verilog frontend. + +89. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_mult_boothdcd.v +Parsing Verilog input from `../verilog/trilib/tri_st_mult_boothdcd.v' to AST representation. +Generating RTLIL representation for module `\tri_st_mult_boothdcd'. +Successfully finished Verilog frontend. + +90. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_mult_boothrow.v +Parsing Verilog input from `../verilog/trilib/tri_st_mult_boothrow.v' to AST representation. +Generating RTLIL representation for module `\tri_st_mult_boothrow'. +Successfully finished Verilog frontend. + +91. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_mult_core.v +Parsing Verilog input from `../verilog/trilib/tri_st_mult_core.v' to AST representation. +Generating RTLIL representation for module `\tri_st_mult_core'. +Successfully finished Verilog frontend. + +92. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_or3232.v +Parsing Verilog input from `../verilog/trilib/tri_st_or3232.v' to AST representation. +Generating RTLIL representation for module `\tri_st_or3232'. +Successfully finished Verilog frontend. + +93. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_or3232_b.v +Parsing Verilog input from `../verilog/trilib/tri_st_or3232_b.v' to AST representation. +Generating RTLIL representation for module `\tri_st_or3232_b'. +Successfully finished Verilog frontend. + +94. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_popcnt.v +Parsing Verilog input from `../verilog/trilib/tri_st_popcnt.v' to AST representation. +Generating RTLIL representation for module `\tri_st_popcnt'. +Successfully finished Verilog frontend. + +95. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_popcnt_byte.v +Parsing Verilog input from `../verilog/trilib/tri_st_popcnt_byte.v' to AST representation. +Generating RTLIL representation for module `\tri_st_popcnt_byte'. +Successfully finished Verilog frontend. + +96. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_popcnt_word.v +Parsing Verilog input from `../verilog/trilib/tri_st_popcnt_word.v' to AST representation. +Generating RTLIL representation for module `\tri_st_popcnt_word'. +Successfully finished Verilog frontend. + +97. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_rot.v +Parsing Verilog input from `../verilog/trilib/tri_st_rot.v' to AST representation. +Generating RTLIL representation for module `\tri_st_rot'. +Successfully finished Verilog frontend. + +98. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_rot_dec.v +Parsing Verilog input from `../verilog/trilib/tri_st_rot_dec.v' to AST representation. +Generating RTLIL representation for module `\tri_st_rot_dec'. +Successfully finished Verilog frontend. + +99. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_rot_ins.v +Parsing Verilog input from `../verilog/trilib/tri_st_rot_ins.v' to AST representation. +Generating RTLIL representation for module `\tri_st_rot_ins'. +Successfully finished Verilog frontend. + +100. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_rot_mask.v +Parsing Verilog input from `../verilog/trilib/tri_st_rot_mask.v' to AST representation. +Generating RTLIL representation for module `\tri_st_rot_mask'. +Successfully finished Verilog frontend. + +101. Executing Verilog-2005 frontend: ../verilog/trilib/tri_st_rot_rol64.v +Parsing Verilog input from `../verilog/trilib/tri_st_rot_rol64.v' to AST representation. +Generating RTLIL representation for module `\tri_st_rot_rol64'. +Successfully finished Verilog frontend. + +102. Executing Verilog-2005 frontend: ../verilog/trilib/tri_xnor2.v +Parsing Verilog input from `../verilog/trilib/tri_xnor2.v' to AST representation. +Generating RTLIL representation for module `\tri_xnor2'. +Successfully finished Verilog frontend. + +103. Executing Verilog-2005 frontend: ../verilog/trilib/tri_xor2.v +Parsing Verilog input from `../verilog/trilib/tri_xor2.v' to AST representation. +Generating RTLIL representation for module `\tri_xor2'. +Successfully finished Verilog frontend. + +104. Executing Verilog-2005 frontend: ../verilog/trilib/tri_xor3.v +Parsing Verilog input from `../verilog/trilib/tri_xor3.v' to AST representation. +Generating RTLIL representation for module `\tri_xor3'. +Successfully finished Verilog frontend. + +105. Executing Verilog-2005 frontend: ../verilog/work/c.v +Parsing Verilog input from `../verilog/work/c.v' to AST representation. +Generating RTLIL representation for module `\c'. +Successfully finished Verilog frontend. + +106. Executing Verilog-2005 frontend: ../verilog/work/c_fu_pc.v +Parsing Verilog input from `../verilog/work/c_fu_pc.v' to AST representation. +Generating RTLIL representation for module `\c_fu_pc'. +Successfully finished Verilog frontend. + +107. Executing Verilog-2005 frontend: ../verilog/work/c_perv_rp.v +Parsing Verilog input from `../verilog/work/c_perv_rp.v' to AST representation. +Generating RTLIL representation for module `\c_perv_rp'. +Successfully finished Verilog frontend. + +108. Executing Verilog-2005 frontend: ../verilog/work/c_wrapper.v +Parsing Verilog input from `../verilog/work/c_wrapper.v' to AST representation. +Generating RTLIL representation for module `\c_wrapper'. +Successfully finished Verilog frontend. + +109. Executing Verilog-2005 frontend: ../verilog/work/fu.v +Parsing Verilog input from `../verilog/work/fu.v' to AST representation. +Generating RTLIL representation for module `\fu'. +Successfully finished Verilog frontend. + +110. Executing Verilog-2005 frontend: ../verilog/work/fu_add.v +Parsing Verilog input from `../verilog/work/fu_add.v' to AST representation. +Generating RTLIL representation for module `\fu_add'. +Successfully finished Verilog frontend. + +111. Executing Verilog-2005 frontend: ../verilog/work/fu_add_all1.v +Parsing Verilog input from `../verilog/work/fu_add_all1.v' to AST representation. +Generating RTLIL representation for module `\fu_add_all1'. +Successfully finished Verilog frontend. + +112. Executing Verilog-2005 frontend: ../verilog/work/fu_add_glbc.v +Parsing Verilog input from `../verilog/work/fu_add_glbc.v' to AST representation. +Generating RTLIL representation for module `\fu_add_glbc'. +Successfully finished Verilog frontend. + +113. Executing Verilog-2005 frontend: ../verilog/work/fu_alg.v +Parsing Verilog input from `../verilog/work/fu_alg.v' to AST representation. +Generating RTLIL representation for module `\fu_alg'. +Successfully finished Verilog frontend. + +114. Executing Verilog-2005 frontend: ../verilog/work/fu_alg_add.v +Parsing Verilog input from `../verilog/work/fu_alg_add.v' to AST representation. +Generating RTLIL representation for module `\fu_alg_add'. +Successfully finished Verilog frontend. + +115. Executing Verilog-2005 frontend: ../verilog/work/fu_alg_bypmux.v +Parsing Verilog input from `../verilog/work/fu_alg_bypmux.v' to AST representation. +Generating RTLIL representation for module `\fu_alg_bypmux'. +Successfully finished Verilog frontend. + +116. Executing Verilog-2005 frontend: ../verilog/work/fu_alg_or16.v +Parsing Verilog input from `../verilog/work/fu_alg_or16.v' to AST representation. +Generating RTLIL representation for module `\fu_alg_or16'. +Successfully finished Verilog frontend. + +117. Executing Verilog-2005 frontend: ../verilog/work/fu_alg_sh16.v +Parsing Verilog input from `../verilog/work/fu_alg_sh16.v' to AST representation. +Generating RTLIL representation for module `\fu_alg_sh16'. +Successfully finished Verilog frontend. + +118. Executing Verilog-2005 frontend: ../verilog/work/fu_alg_sh4.v +Parsing Verilog input from `../verilog/work/fu_alg_sh4.v' to AST representation. +Generating RTLIL representation for module `\fu_alg_sh4'. +Successfully finished Verilog frontend. + +119. Executing Verilog-2005 frontend: ../verilog/work/fu_byp.v +Parsing Verilog input from `../verilog/work/fu_byp.v' to AST representation. +Generating RTLIL representation for module `\fu_byp'. +Successfully finished Verilog frontend. + +120. Executing Verilog-2005 frontend: ../verilog/work/fu_cr2.v +Parsing Verilog input from `../verilog/work/fu_cr2.v' to AST representation. +Generating RTLIL representation for module `\fu_cr2'. +Successfully finished Verilog frontend. + +121. Executing Verilog-2005 frontend: ../verilog/work/fu_dcd.v +Parsing Verilog input from `../verilog/work/fu_dcd.v' to AST representation. +Generating RTLIL representation for module `\fu_dcd'. +Successfully finished Verilog frontend. + +122. Executing Verilog-2005 frontend: ../verilog/work/fu_divsqrt.v +Parsing Verilog input from `../verilog/work/fu_divsqrt.v' to AST representation. +Generating RTLIL representation for module `\fu_divsqrt'. +Successfully finished Verilog frontend. + +123. Executing Verilog-2005 frontend: ../verilog/work/fu_divsqrt_add4.v +Parsing Verilog input from `../verilog/work/fu_divsqrt_add4.v' to AST representation. +Generating RTLIL representation for module `\fu_divsqrt_add4'. +Successfully finished Verilog frontend. + +124. Executing Verilog-2005 frontend: ../verilog/work/fu_divsqrt_nq_table.v +Parsing Verilog input from `../verilog/work/fu_divsqrt_nq_table.v' to AST representation. +Generating RTLIL representation for module `\fu_divsqrt_nq_table'. +Successfully finished Verilog frontend. + +125. Executing Verilog-2005 frontend: ../verilog/work/fu_divsqrt_q_table.v +Parsing Verilog input from `../verilog/work/fu_divsqrt_q_table.v' to AST representation. +Generating RTLIL representation for module `\fu_divsqrt_q_table'. +Successfully finished Verilog frontend. + +126. Executing Verilog-2005 frontend: ../verilog/work/fu_eie.v +Parsing Verilog input from `../verilog/work/fu_eie.v' to AST representation. +Generating RTLIL representation for module `\fu_eie'. +Successfully finished Verilog frontend. + +127. Executing Verilog-2005 frontend: ../verilog/work/fu_eov.v +Parsing Verilog input from `../verilog/work/fu_eov.v' to AST representation. +Generating RTLIL representation for module `\fu_eov'. +Successfully finished Verilog frontend. + +128. Executing Verilog-2005 frontend: ../verilog/work/fu_fmt.v +Parsing Verilog input from `../verilog/work/fu_fmt.v' to AST representation. +Generating RTLIL representation for module `\fu_fmt'. +Successfully finished Verilog frontend. + +129. Executing Verilog-2005 frontend: ../verilog/work/fu_fpr.v +Parsing Verilog input from `../verilog/work/fu_fpr.v' to AST representation. +Generating RTLIL representation for module `\fu_fpr'. +Successfully finished Verilog frontend. + +130. Executing Verilog-2005 frontend: ../verilog/work/fu_gst.v +Parsing Verilog input from `../verilog/work/fu_gst.v' to AST representation. +Generating RTLIL representation for module `\fu_gst'. +Successfully finished Verilog frontend. + +131. Executing Verilog-2005 frontend: ../verilog/work/fu_gst_add11.v +Parsing Verilog input from `../verilog/work/fu_gst_add11.v' to AST representation. +Generating RTLIL representation for module `\fu_gst_add11'. +Successfully finished Verilog frontend. + +132. Executing Verilog-2005 frontend: ../verilog/work/fu_gst_inc19.v +Parsing Verilog input from `../verilog/work/fu_gst_inc19.v' to AST representation. +Generating RTLIL representation for module `\fu_gst_inc19'. +Successfully finished Verilog frontend. + +133. Executing Verilog-2005 frontend: ../verilog/work/fu_gst_loa.v +Parsing Verilog input from `../verilog/work/fu_gst_loa.v' to AST representation. +Generating RTLIL representation for module `\fu_gst_loa'. +Successfully finished Verilog frontend. + +134. Executing Verilog-2005 frontend: ../verilog/work/fu_hc16pp.v +Parsing Verilog input from `../verilog/work/fu_hc16pp.v' to AST representation. +Generating RTLIL representation for module `\fu_hc16pp'. +Successfully finished Verilog frontend. + +135. Executing Verilog-2005 frontend: ../verilog/work/fu_hc16pp_lsb.v +Parsing Verilog input from `../verilog/work/fu_hc16pp_lsb.v' to AST representation. +Generating RTLIL representation for module `\fu_hc16pp_lsb'. +Successfully finished Verilog frontend. + +136. Executing Verilog-2005 frontend: ../verilog/work/fu_hc16pp_msb.v +Parsing Verilog input from `../verilog/work/fu_hc16pp_msb.v' to AST representation. +Generating RTLIL representation for module `\fu_hc16pp_msb'. +Successfully finished Verilog frontend. + +137. Executing Verilog-2005 frontend: ../verilog/work/fu_loc8inc.v +Parsing Verilog input from `../verilog/work/fu_loc8inc.v' to AST representation. +Generating RTLIL representation for module `\fu_loc8inc'. +Successfully finished Verilog frontend. + +138. Executing Verilog-2005 frontend: ../verilog/work/fu_loc8inc_lsb.v +Parsing Verilog input from `../verilog/work/fu_loc8inc_lsb.v' to AST representation. +Generating RTLIL representation for module `\fu_loc8inc_lsb'. +Successfully finished Verilog frontend. + +139. Executing Verilog-2005 frontend: ../verilog/work/fu_lza.v +Parsing Verilog input from `../verilog/work/fu_lza.v' to AST representation. +Generating RTLIL representation for module `\fu_lza'. +Successfully finished Verilog frontend. + +140. Executing Verilog-2005 frontend: ../verilog/work/fu_lza_clz.v +Parsing Verilog input from `../verilog/work/fu_lza_clz.v' to AST representation. +Generating RTLIL representation for module `\fu_lza_clz'. +Successfully finished Verilog frontend. + +141. Executing Verilog-2005 frontend: ../verilog/work/fu_lza_ej.v +Parsing Verilog input from `../verilog/work/fu_lza_ej.v' to AST representation. +Generating RTLIL representation for module `\fu_lza_ej'. +Successfully finished Verilog frontend. + +142. Executing Verilog-2005 frontend: ../verilog/work/fu_lze.v +Parsing Verilog input from `../verilog/work/fu_lze.v' to AST representation. +Generating RTLIL representation for module `\fu_lze'. +Successfully finished Verilog frontend. + +143. Executing Verilog-2005 frontend: ../verilog/work/fu_mad.v +Parsing Verilog input from `../verilog/work/fu_mad.v' to AST representation. +Generating RTLIL representation for module `\fu_mad'. +Successfully finished Verilog frontend. + +144. Executing Verilog-2005 frontend: ../verilog/work/fu_nrm.v +Parsing Verilog input from `../verilog/work/fu_nrm.v' to AST representation. +Generating RTLIL representation for module `\fu_nrm'. +Successfully finished Verilog frontend. + +145. Executing Verilog-2005 frontend: ../verilog/work/fu_nrm_or16.v +Parsing Verilog input from `../verilog/work/fu_nrm_or16.v' to AST representation. +Generating RTLIL representation for module `\fu_nrm_or16'. +Successfully finished Verilog frontend. + +146. Executing Verilog-2005 frontend: ../verilog/work/fu_nrm_sh.v +Parsing Verilog input from `../verilog/work/fu_nrm_sh.v' to AST representation. +Generating RTLIL representation for module `\fu_nrm_sh'. +Successfully finished Verilog frontend. + +147. Executing Verilog-2005 frontend: ../verilog/work/fu_oscr.v +Parsing Verilog input from `../verilog/work/fu_oscr.v' to AST representation. +Generating RTLIL representation for module `\fu_oscr'. +Successfully finished Verilog frontend. + +148. Executing Verilog-2005 frontend: ../verilog/work/fu_perv.v +Parsing Verilog input from `../verilog/work/fu_perv.v' to AST representation. +Generating RTLIL representation for module `\fu_perv'. +Successfully finished Verilog frontend. + +149. Executing Verilog-2005 frontend: ../verilog/work/fu_pic.v +Parsing Verilog input from `../verilog/work/fu_pic.v' to AST representation. +Generating RTLIL representation for module `\fu_pic'. +Successfully finished Verilog frontend. + +150. Executing Verilog-2005 frontend: ../verilog/work/fu_rnd.v +Parsing Verilog input from `../verilog/work/fu_rnd.v' to AST representation. +Generating RTLIL representation for module `\fu_rnd'. +Successfully finished Verilog frontend. + +151. Executing Verilog-2005 frontend: ../verilog/work/fu_sa3.v +Parsing Verilog input from `../verilog/work/fu_sa3.v' to AST representation. +Generating RTLIL representation for module `\fu_sa3'. +Successfully finished Verilog frontend. + +152. Executing Verilog-2005 frontend: ../verilog/work/fu_sto.v +Parsing Verilog input from `../verilog/work/fu_sto.v' to AST representation. +Generating RTLIL representation for module `\fu_sto'. +Successfully finished Verilog frontend. + +153. Executing Verilog-2005 frontend: ../verilog/work/fu_tblexp.v +Parsing Verilog input from `../verilog/work/fu_tblexp.v' to AST representation. +Generating RTLIL representation for module `\fu_tblexp'. +Successfully finished Verilog frontend. + +154. Executing Verilog-2005 frontend: ../verilog/work/fu_tbllut.v +Parsing Verilog input from `../verilog/work/fu_tbllut.v' to AST representation. +Generating RTLIL representation for module `\fu_tbllut'. +Successfully finished Verilog frontend. + +155. Executing Verilog-2005 frontend: ../verilog/work/fu_tblres.v +Parsing Verilog input from `../verilog/work/fu_tblres.v' to AST representation. +Generating RTLIL representation for module `\fu_tblres'. +Successfully finished Verilog frontend. + +156. Executing Verilog-2005 frontend: ../verilog/work/fu_tblsqe.v +Parsing Verilog input from `../verilog/work/fu_tblsqe.v' to AST representation. +Generating RTLIL representation for module `\fu_tblsqe'. +Successfully finished Verilog frontend. + +157. Executing Verilog-2005 frontend: ../verilog/work/fu_tblsqo.v +Parsing Verilog input from `../verilog/work/fu_tblsqo.v' to AST representation. +Generating RTLIL representation for module `\fu_tblsqo'. +Successfully finished Verilog frontend. + +158. Executing Verilog-2005 frontend: ../verilog/work/iuq.v +Parsing Verilog input from `../verilog/work/iuq.v' to AST representation. +Generating RTLIL representation for module `\iuq'. +Successfully finished Verilog frontend. + +159. Executing Verilog-2005 frontend: ../verilog/work/iuq_axu_fu_dec.v +Parsing Verilog input from `../verilog/work/iuq_axu_fu_dec.v' to AST representation. +Generating RTLIL representation for module `\iuq_axu_fu_dec'. +Successfully finished Verilog frontend. + +160. Executing Verilog-2005 frontend: ../verilog/work/iuq_axu_fu_rn.v +Parsing Verilog input from `../verilog/work/iuq_axu_fu_rn.v' to AST representation. +Generating RTLIL representation for module `\iuq_axu_fu_rn'. +Successfully finished Verilog frontend. + +161. Executing Verilog-2005 frontend: ../verilog/work/iuq_bd.v +Parsing Verilog input from `../verilog/work/iuq_bd.v' to AST representation. +Generating RTLIL representation for module `\iuq_bd'. +Successfully finished Verilog frontend. + +162. Executing Verilog-2005 frontend: ../verilog/work/iuq_bp.v +Parsing Verilog input from `../verilog/work/iuq_bp.v' to AST representation. +Generating RTLIL representation for module `\iuq_bp'. +Successfully finished Verilog frontend. + +163. Executing Verilog-2005 frontend: ../verilog/work/iuq_btb.v +Parsing Verilog input from `../verilog/work/iuq_btb.v' to AST representation. +Generating RTLIL representation for module `\iuq_btb'. +Successfully finished Verilog frontend. + +164. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl.v +Parsing Verilog input from `../verilog/work/iuq_cpl.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl'. +Successfully finished Verilog frontend. + +165. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl_ctrl.v +Parsing Verilog input from `../verilog/work/iuq_cpl_ctrl.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl_ctrl'. +Successfully finished Verilog frontend. + +166. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl_ctrl_inc.v +Parsing Verilog input from `../verilog/work/iuq_cpl_ctrl_inc.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl_ctrl_inc'. +Successfully finished Verilog frontend. + +167. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl_dec.v +Parsing Verilog input from `../verilog/work/iuq_cpl_dec.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl_dec'. +Successfully finished Verilog frontend. + +168. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl_itag.v +Parsing Verilog input from `../verilog/work/iuq_cpl_itag.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl_itag'. +Successfully finished Verilog frontend. + +169. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl_table.v +Parsing Verilog input from `../verilog/work/iuq_cpl_table.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl_table'. +Successfully finished Verilog frontend. + +170. Executing Verilog-2005 frontend: ../verilog/work/iuq_cpl_top.v +Parsing Verilog input from `../verilog/work/iuq_cpl_top.v' to AST representation. +Generating RTLIL representation for module `\iuq_cpl_top'. +Successfully finished Verilog frontend. + +171. Executing Verilog-2005 frontend: ../verilog/work/iuq_dbg.v +Parsing Verilog input from `../verilog/work/iuq_dbg.v' to AST representation. +Generating RTLIL representation for module `\iuq_dbg'. +Successfully finished Verilog frontend. + +172. Executing Verilog-2005 frontend: ../verilog/work/iuq_dec_top.v +Parsing Verilog input from `../verilog/work/iuq_dec_top.v' to AST representation. +Generating RTLIL representation for module `\iuq_dec_top'. +Successfully finished Verilog frontend. + +173. Executing Verilog-2005 frontend: ../verilog/work/iuq_dispatch.v +Parsing Verilog input from `../verilog/work/iuq_dispatch.v' to AST representation. +Generating RTLIL representation for module `\iuq_dispatch'. +Warning: Replacing memory \fu1_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2289 +Warning: Replacing memory \fu1_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2288 +Warning: Replacing memory \fu0_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2257 +Warning: Replacing memory \fu0_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2256 +Warning: Replacing memory \sq_cmdq_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2225 +Warning: Replacing memory \sq_cmdq_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2224 +Warning: Replacing memory \lq_cmdq_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2193 +Warning: Replacing memory \lq_cmdq_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2192 +Warning: Replacing memory \fx1_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2160 +Warning: Replacing memory \fx1_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2159 +Warning: Replacing memory \fx0_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2128 +Warning: Replacing memory \fx0_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2127 +Successfully finished Verilog frontend. + +174. Executing Verilog-2005 frontend: ../verilog/work/iuq_ibuf.v +Parsing Verilog input from `../verilog/work/iuq_ibuf.v' to AST representation. +Generating RTLIL representation for module `\iuq_ibuf'. +Warning: Replacing memory \buffer1_data_muxed with list of registers. See ../verilog/work/iuq_ibuf.v:555, ../verilog/work/iuq_ibuf.v:551 +Warning: Replacing memory \buffer0_data_muxed with list of registers. See ../verilog/work/iuq_ibuf.v:534, ../verilog/work/iuq_ibuf.v:530 +Warning: Replacing memory \buffer_data_q with list of registers. See ../verilog/work/iuq_ibuf.v:510 +Warning: Replacing memory \buffer_data_d with list of registers. See ../verilog/work/iuq_ibuf.v:509, ../verilog/work/iuq_ibuf.v:507 +Warning: Replacing memory \buffer_data_din with list of registers. See ../verilog/work/iuq_ibuf.v:492, ../verilog/work/iuq_ibuf.v:478, ../verilog/work/iuq_ibuf.v:464, ../verilog/work/iuq_ibuf.v:450, ../verilog/work/iuq_ibuf.v:507, ../verilog/work/iuq_ibuf.v:436 +Successfully finished Verilog frontend. + +175. Executing Verilog-2005 frontend: ../verilog/work/iuq_ic.v +Parsing Verilog input from `../verilog/work/iuq_ic.v' to AST representation. +Generating RTLIL representation for module `\iuq_ic'. +Successfully finished Verilog frontend. + +176. Executing Verilog-2005 frontend: ../verilog/work/iuq_ic_dir.v +Parsing Verilog input from `../verilog/work/iuq_ic_dir.v' to AST representation. +Generating RTLIL representation for module `\iuq_ic_dir'. +Warning: Replacing memory \dir_lru_write with list of registers. See ../verilog/work/iuq_ic_dir.v:1129 +Warning: Replacing memory \dir_lru_read with list of registers. See ../verilog/work/iuq_ic_dir.v:1128 +Successfully finished Verilog frontend. + +177. Executing Verilog-2005 frontend: ../verilog/work/iuq_ic_ierat.v +Parsing Verilog input from `../verilog/work/iuq_ic_ierat.v' to AST representation. +Generating RTLIL representation for module `\iuq_ic_ierat'. +Successfully finished Verilog frontend. + +178. Executing Verilog-2005 frontend: ../verilog/work/iuq_ic_miss.v +Parsing Verilog input from `../verilog/work/iuq_ic_miss.v' to AST representation. +Generating RTLIL representation for module `\iuq_ic_miss'. +Successfully finished Verilog frontend. + +179. Executing Verilog-2005 frontend: ../verilog/work/iuq_ic_miss_table.v +Parsing Verilog input from `../verilog/work/iuq_ic_miss_table.v' to AST representation. +Generating RTLIL representation for module `\iuq_ic_miss_table'. +Successfully finished Verilog frontend. + +180. Executing Verilog-2005 frontend: ../verilog/work/iuq_ic_select.v +Parsing Verilog input from `../verilog/work/iuq_ic_select.v' to AST representation. +Generating RTLIL representation for module `\iuq_ic_select'. +Warning: Replacing memory \iu0_ifar_temp with list of registers. See ../verilog/work/iuq_ic_select.v:712 +Warning: Replacing memory \iu0_sent_d with list of registers. See ../verilog/work/iuq_ic_select.v:619 +Warning: Replacing memory \sent_proc.any_sent with list of registers. See ../verilog/work/iuq_ic_select.v:612, ../verilog/work/iuq_ic_select.v:609 +Warning: Replacing memory \shift2_sent with list of registers. See ../verilog/work/iuq_ic_select.v:607, ../verilog/work/iuq_ic_select.v:606 +Warning: Replacing memory \shift1_sent with list of registers. See ../verilog/work/iuq_ic_select.v:603, ../verilog/work/iuq_ic_select.v:602 +Warning: Replacing memory \next_fetch with list of registers. See ../verilog/work/iuq_ic_select.v:602, ../verilog/work/iuq_ic_select.v:588 +Warning: Replacing memory \need_fetch with list of registers. See ../verilog/work/iuq_ic_select.v:588, ../verilog/work/iuq_ic_select.v:586 +Successfully finished Verilog frontend. + +181. Executing Verilog-2005 frontend: ../verilog/work/iuq_idec.v +Parsing Verilog input from `../verilog/work/iuq_idec.v' to AST representation. +Generating RTLIL representation for module `\iuq_idec'. +Successfully finished Verilog frontend. + +182. Executing Verilog-2005 frontend: ../verilog/work/iuq_ifetch.v +Parsing Verilog input from `../verilog/work/iuq_ifetch.v' to AST representation. +Generating RTLIL representation for module `\iuq_ifetch'. +Successfully finished Verilog frontend. + +183. Executing Verilog-2005 frontend: ../verilog/work/iuq_ram.v +Parsing Verilog input from `../verilog/work/iuq_ram.v' to AST representation. +Generating RTLIL representation for module `\iuq_ram'. +Successfully finished Verilog frontend. + +184. Executing Verilog-2005 frontend: ../verilog/work/iuq_rn.v +Parsing Verilog input from `../verilog/work/iuq_rn.v' to AST representation. +Generating RTLIL representation for module `\iuq_rn'. +Successfully finished Verilog frontend. + +185. Executing Verilog-2005 frontend: ../verilog/work/iuq_rn_map.v +Parsing Verilog input from `../verilog/work/iuq_rn_map.v' to AST representation. +Generating RTLIL representation for module `\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Successfully finished Verilog frontend. + +186. Executing Verilog-2005 frontend: ../verilog/work/iuq_rn_map_inc.v +Parsing Verilog input from `../verilog/work/iuq_rn_map_inc.v' to AST representation. +Generating RTLIL representation for module `\iuq_rn_map_inc'. +Successfully finished Verilog frontend. + +187. Executing Verilog-2005 frontend: ../verilog/work/iuq_rn_top.v +Parsing Verilog input from `../verilog/work/iuq_rn_top.v' to AST representation. +Generating RTLIL representation for module `\iuq_rn_top'. +Successfully finished Verilog frontend. + +188. Executing Verilog-2005 frontend: ../verilog/work/iuq_slice.v +Parsing Verilog input from `../verilog/work/iuq_slice.v' to AST representation. +Generating RTLIL representation for module `\iuq_slice'. +Successfully finished Verilog frontend. + +189. Executing Verilog-2005 frontend: ../verilog/work/iuq_slice_top.v +Parsing Verilog input from `../verilog/work/iuq_slice_top.v' to AST representation. +Generating RTLIL representation for module `\iuq_slice_top'. +Successfully finished Verilog frontend. + +190. Executing Verilog-2005 frontend: ../verilog/work/iuq_spr.v +Parsing Verilog input from `../verilog/work/iuq_spr.v' to AST representation. +Generating RTLIL representation for module `\iuq_spr'. +Successfully finished Verilog frontend. + +191. Executing Verilog-2005 frontend: ../verilog/work/iuq_uc.v +Parsing Verilog input from `../verilog/work/iuq_uc.v' to AST representation. +Generating RTLIL representation for module `\iuq_uc'. +Successfully finished Verilog frontend. + +192. Executing Verilog-2005 frontend: ../verilog/work/iuq_uc_buffer.v +Parsing Verilog input from `../verilog/work/iuq_uc_buffer.v' to AST representation. +Generating RTLIL representation for module `\iuq_uc_buffer'. +Successfully finished Verilog frontend. + +193. Executing Verilog-2005 frontend: ../verilog/work/iuq_uc_control.v +Parsing Verilog input from `../verilog/work/iuq_uc_control.v' to AST representation. +Generating RTLIL representation for module `\iuq_uc_control'. +Successfully finished Verilog frontend. + +194. Executing Verilog-2005 frontend: ../verilog/work/iuq_uc_cplbuffer.v +Parsing Verilog input from `../verilog/work/iuq_uc_cplbuffer.v' to AST representation. +Generating RTLIL representation for module `\iuq_uc_cplbuffer'. +Warning: Replacing memory \xer_d with list of registers. See ../verilog/work/iuq_uc_cplbuffer.v:182 +Warning: Replacing memory \buffer_d with list of registers. See ../verilog/work/iuq_uc_cplbuffer.v:180 +Successfully finished Verilog frontend. + +195. Executing Verilog-2005 frontend: ../verilog/work/iuq_uc_rom_even.v +Parsing Verilog input from `../verilog/work/iuq_uc_rom_even.v' to AST representation. +Generating RTLIL representation for module `\iuq_uc_rom_even'. +Successfully finished Verilog frontend. + +196. Executing Verilog-2005 frontend: ../verilog/work/iuq_uc_rom_odd.v +Parsing Verilog input from `../verilog/work/iuq_uc_rom_odd.v' to AST representation. +Generating RTLIL representation for module `\iuq_uc_rom_odd'. +Successfully finished Verilog frontend. + +197. Executing Verilog-2005 frontend: ../verilog/work/lq.v +Parsing Verilog input from `../verilog/work/lq.v' to AST representation. +Generating RTLIL representation for module `\lq'. +Successfully finished Verilog frontend. + +198. Executing Verilog-2005 frontend: ../verilog/work/lq_agen.v +Parsing Verilog input from `../verilog/work/lq_agen.v' to AST representation. +Generating RTLIL representation for module `\lq_agen'. +Successfully finished Verilog frontend. + +199. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_csmux.v +Parsing Verilog input from `../verilog/work/lq_agen_csmux.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_csmux'. +Successfully finished Verilog frontend. + +200. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_csmuxe.v +Parsing Verilog input from `../verilog/work/lq_agen_csmuxe.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_csmuxe'. +Successfully finished Verilog frontend. + +201. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_glbglb.v +Parsing Verilog input from `../verilog/work/lq_agen_glbglb.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_glbglb'. +Successfully finished Verilog frontend. + +202. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_glbloc.v +Parsing Verilog input from `../verilog/work/lq_agen_glbloc.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_glbloc'. +Successfully finished Verilog frontend. + +203. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_glbloc_lsb.v +Parsing Verilog input from `../verilog/work/lq_agen_glbloc_lsb.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_glbloc_lsb'. +Successfully finished Verilog frontend. + +204. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_lo.v +Parsing Verilog input from `../verilog/work/lq_agen_lo.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_lo'. +Successfully finished Verilog frontend. + +205. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_loca.v +Parsing Verilog input from `../verilog/work/lq_agen_loca.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_loca'. +Successfully finished Verilog frontend. + +206. Executing Verilog-2005 frontend: ../verilog/work/lq_agen_locae.v +Parsing Verilog input from `../verilog/work/lq_agen_locae.v' to AST representation. +Generating RTLIL representation for module `\lq_agen_locae'. +Successfully finished Verilog frontend. + +207. Executing Verilog-2005 frontend: ../verilog/work/lq_arb.v +Parsing Verilog input from `../verilog/work/lq_arb.v' to AST representation. +Generating RTLIL representation for module `\lq_arb'. +Successfully finished Verilog frontend. + +208. Executing Verilog-2005 frontend: ../verilog/work/lq_axu_dec.v +Parsing Verilog input from `../verilog/work/lq_axu_dec.v' to AST representation. +Generating RTLIL representation for module `\lq_axu_dec'. +Successfully finished Verilog frontend. + +209. Executing Verilog-2005 frontend: ../verilog/work/lq_byp.v +Parsing Verilog input from `../verilog/work/lq_byp.v' to AST representation. +Generating RTLIL representation for module `\lq_byp'. +Successfully finished Verilog frontend. + +210. Executing Verilog-2005 frontend: ../verilog/work/lq_ctl.v +Parsing Verilog input from `../verilog/work/lq_ctl.v' to AST representation. +Generating RTLIL representation for module `\lq_ctl'. +Successfully finished Verilog frontend. + +211. Executing Verilog-2005 frontend: ../verilog/work/lq_data.v +Parsing Verilog input from `../verilog/work/lq_data.v' to AST representation. +Generating RTLIL representation for module `\lq_data'. +Successfully finished Verilog frontend. + +212. Executing Verilog-2005 frontend: ../verilog/work/lq_data_ld.v +Parsing Verilog input from `../verilog/work/lq_data_ld.v' to AST representation. +Generating RTLIL representation for module `\lq_data_ld'. +Successfully finished Verilog frontend. + +213. Executing Verilog-2005 frontend: ../verilog/work/lq_data_st.v +Parsing Verilog input from `../verilog/work/lq_data_st.v' to AST representation. +Generating RTLIL representation for module `\lq_data_st'. +Successfully finished Verilog frontend. + +214. Executing Verilog-2005 frontend: ../verilog/work/lq_dcc.v +Parsing Verilog input from `../verilog/work/lq_dcc.v' to AST representation. +Generating RTLIL representation for module `\lq_dcc'. +Successfully finished Verilog frontend. + +215. Executing Verilog-2005 frontend: ../verilog/work/lq_dec.v +Parsing Verilog input from `../verilog/work/lq_dec.v' to AST representation. +Generating RTLIL representation for module `\lq_dec'. +Successfully finished Verilog frontend. + +216. Executing Verilog-2005 frontend: ../verilog/work/lq_derat.v +Parsing Verilog input from `../verilog/work/lq_derat.v' to AST representation. +Generating RTLIL representation for module `\lq_derat'. +Warning: Replacing memory \eratm_entry_nxt_state with list of registers. See ../verilog/work/lq_derat.v:4485 +Successfully finished Verilog frontend. + +217. Executing Verilog-2005 frontend: ../verilog/work/lq_dir.v +Parsing Verilog input from `../verilog/work/lq_dir.v' to AST representation. +Generating RTLIL representation for module `\lq_dir'. +Successfully finished Verilog frontend. + +218. Executing Verilog-2005 frontend: ../verilog/work/lq_dir_lru.v +Parsing Verilog input from `../verilog/work/lq_dir_lru.v' to AST representation. +Generating RTLIL representation for module `\lq_dir_lru'. +Successfully finished Verilog frontend. + +219. Executing Verilog-2005 frontend: ../verilog/work/lq_dir_tag.v +Parsing Verilog input from `../verilog/work/lq_dir_tag.v' to AST representation. +Generating RTLIL representation for module `\lq_dir_tag'. +Successfully finished Verilog frontend. + +220. Executing Verilog-2005 frontend: ../verilog/work/lq_dir_tag_arr.v +Parsing Verilog input from `../verilog/work/lq_dir_tag_arr.v' to AST representation. +Generating RTLIL representation for module `\lq_dir_tag_arr'. +Successfully finished Verilog frontend. + +221. Executing Verilog-2005 frontend: ../verilog/work/lq_dir_val.v +Parsing Verilog input from `../verilog/work/lq_dir_val.v' to AST representation. +Generating RTLIL representation for module `\lq_dir_val'. +Warning: Replacing memory \p1_arr_way_rd with list of registers. See ../verilog/work/lq_dir_val.v:1889 +Warning: Replacing memory \p0_arr_way_rd with list of registers. See ../verilog/work/lq_dir_val.v:1378 +Successfully finished Verilog frontend. + +222. Executing Verilog-2005 frontend: ../verilog/work/lq_fgen.v +Parsing Verilog input from `../verilog/work/lq_fgen.v' to AST representation. +Generating RTLIL representation for module `\lq_fgen'. +Successfully finished Verilog frontend. + +223. Executing Verilog-2005 frontend: ../verilog/work/lq_imq.v +Parsing Verilog input from `../verilog/work/lq_imq.v' to AST representation. +Generating RTLIL representation for module `\lq_imq'. +Successfully finished Verilog frontend. + +224. Executing Verilog-2005 frontend: ../verilog/work/lq_ldq.v +Parsing Verilog input from `../verilog/work/lq_ldq.v' to AST representation. +Generating RTLIL representation for module `\lq_ldq'. +Warning: Replacing memory \cpl_grpEntry_pEvents with list of registers. See ../verilog/work/lq_ldq.v:3652 +Warning: Replacing memory \cpl_grpEntry_tid with list of registers. See ../verilog/work/lq_ldq.v:3649 +Warning: Replacing memory \cpl_grpEntry_dacrw with list of registers. See ../verilog/work/lq_ldq.v:3648 +Warning: Replacing memory \cpl_grpEntry_dvc with list of registers. See ../verilog/work/lq_ldq.v:3647 +Warning: Replacing memory \cpl_grpEntry_iTag with list of registers. See ../verilog/work/lq_ldq.v:3644 +Warning: Replacing memory \ldqe_nxt_state with list of registers. See ../verilog/work/lq_ldq.v:1926 +Successfully finished Verilog frontend. + +225. Executing Verilog-2005 frontend: ../verilog/work/lq_ldq_relq.v +Parsing Verilog input from `../verilog/work/lq_ldq_relq.v' to AST representation. +Generating RTLIL representation for module `\lq_ldq_relq'. +Warning: Replacing memory \rel_grpEntry_qw with list of registers. See ../verilog/work/lq_ldq_relq.v:507 +Warning: Replacing memory \ldqe_relBeats with list of registers. See ../verilog/work/lq_ldq_relq.v:425 +Successfully finished Verilog frontend. + +226. Executing Verilog-2005 frontend: ../verilog/work/lq_ldq_rot.v +Parsing Verilog input from `../verilog/work/lq_ldq_rot.v' to AST representation. +Generating RTLIL representation for module `\lq_ldq_rot'. +Successfully finished Verilog frontend. + +227. Executing Verilog-2005 frontend: ../verilog/work/lq_lsq.v +Parsing Verilog input from `../verilog/work/lq_lsq.v' to AST representation. +Generating RTLIL representation for module `\lq_lsq'. +Successfully finished Verilog frontend. + +228. Executing Verilog-2005 frontend: ../verilog/work/lq_odq.v +Parsing Verilog input from `../verilog/work/lq_odq.v' to AST representation. +Generating RTLIL representation for module `\lq_odq'. +Warning: Replacing memory \addrq_entry_bytemask_d with list of registers. See ../verilog/work/lq_odq.v:1682 +Warning: Replacing memory \addrq_entry_address_d with list of registers. See ../verilog/work/lq_odq.v:1681 +Warning: Replacing memory \addrq_entry_itag_d with list of registers. See ../verilog/work/lq_odq.v:1680 +Warning: Replacing memory \addrq_entry_tid_d with list of registers. See ../verilog/work/lq_odq.v:1679 +Warning: Replacing memory \addrq_entry_val_d with list of registers. See ../verilog/work/lq_odq.v:1678 +Warning: Replacing memory \addrq_entry_inuse_d with list of registers. See ../verilog/work/lq_odq.v:1677 +Warning: Replacing memory \orderq_entry_itag_d with list of registers. See ../verilog/work/lq_odq.v:1393 +Warning: Replacing memory \orderq_entry_update_pulse_d with list of registers. See ../verilog/work/lq_odq.v:1392 +Warning: Replacing memory \orderq_entry_np1_flush_d with list of registers. See ../verilog/work/lq_odq.v:1391 +Warning: Replacing memory \orderq_entry_n_flush_d with list of registers. See ../verilog/work/lq_odq.v:1390 +Warning: Replacing memory \orderq_entry_val2_d with list of registers. See ../verilog/work/lq_odq.v:1389 +Warning: Replacing memory \orderq_entry_bi_flush_d with list of registers. See ../verilog/work/lq_odq.v:1388 +Warning: Replacing memory \orderq_entry_bi_flag_d with list of registers. See ../verilog/work/lq_odq.v:1387 +Warning: Replacing memory \orderq_entry_cmmt_d with list of registers. See ../verilog/work/lq_odq.v:1386 +Warning: Replacing memory \orderq_entry_stTag_d with list of registers. See ../verilog/work/lq_odq.v:1385 +Warning: Replacing memory \orderq_entry_ld_chk_d with list of registers. See ../verilog/work/lq_odq.v:1384 +Warning: Replacing memory \orderq_entry_myflush_d with list of registers. See ../verilog/work/lq_odq.v:1383 +Warning: Replacing memory \orderq_entry_flushed_d with list of registers. See ../verilog/work/lq_odq.v:1382 +Warning: Replacing memory \orderq_entry_instq_d with list of registers. See ../verilog/work/lq_odq.v:1381 +Warning: Replacing memory \orderq_entry_pre_d with list of registers. See ../verilog/work/lq_odq.v:1380 +Warning: Replacing memory \orderq_entry_pEvents_d with list of registers. See ../verilog/work/lq_odq.v:1379 +Warning: Replacing memory \orderq_entry_eccue_d with list of registers. See ../verilog/work/lq_odq.v:1378 +Warning: Replacing memory \orderq_entry_dacrw_d with list of registers. See ../verilog/work/lq_odq.v:1377 +Warning: Replacing memory \orderq_entry_cls_op_d with list of registers. See ../verilog/work/lq_odq.v:1376 +Warning: Replacing memory \orderq_entry_fwd_d with list of registers. See ../verilog/work/lq_odq.v:1375 +Warning: Replacing memory \orderq_entry_hit_d with list of registers. See ../verilog/work/lq_odq.v:1374 +Warning: Replacing memory \orderq_entry_i_d with list of registers. See ../verilog/work/lq_odq.v:1373 +Warning: Replacing memory \orderq_entry_efs_d with list of registers. See ../verilog/work/lq_odq.v:1372 +Warning: Replacing memory \orderq_entry_ld_d with list of registers. See ../verilog/work/lq_odq.v:1371 +Warning: Replacing memory \orderq_entry_val_d with list of registers. See ../verilog/work/lq_odq.v:1370 +Warning: Replacing memory \orderq_entry_tid_d with list of registers. See ../verilog/work/lq_odq.v:1369 +Warning: Replacing memory \orderq_entry_inuse_d with list of registers. See ../verilog/work/lq_odq.v:1368 +Warning: Replacing memory \oderq_entry_i1_comp_itag with list of registers. See ../verilog/work/lq_odq.v:1015 +Warning: Replacing memory \oderq_entry_i0_comp_itag with list of registers. See ../verilog/work/lq_odq.v:1014 +Warning: Replacing memory \addrq_entry_bytemask_next with list of registers. See ../verilog/work/lq_odq.v:1615, ../verilog/work/lq_odq.v:1594 +Warning: Replacing memory \addrq_entry_address_next with list of registers. See ../verilog/work/lq_odq.v:1614, ../verilog/work/lq_odq.v:1593 +Warning: Replacing memory \addrq_entry_itag_next with list of registers. See ../verilog/work/lq_odq.v:1613, ../verilog/work/lq_odq.v:1592 +Warning: Replacing memory \addrq_entry_tid_next with list of registers. See ../verilog/work/lq_odq.v:1612, ../verilog/work/lq_odq.v:1591 +Warning: Replacing memory \addrq_entry_val_next with list of registers. See ../verilog/work/lq_odq.v:1611, ../verilog/work/lq_odq.v:1590 +Warning: Replacing memory \addrq_entry_inuse_next with list of registers. See ../verilog/work/lq_odq.v:1610, ../verilog/work/lq_odq.v:1589 +Warning: Replacing memory \orderq_entry_itag_next with list of registers. See ../verilog/work/lq_odq.v:1052, ../verilog/work/lq_odq.v:971 +Warning: Replacing memory \orderq_entry_update_pulse_next with list of registers. See ../verilog/work/lq_odq.v:1051, ../verilog/work/lq_odq.v:970 +Warning: Replacing memory \orderq_entry_np1_flush_next with list of registers. See ../verilog/work/lq_odq.v:1050, ../verilog/work/lq_odq.v:969 +Warning: Replacing memory \orderq_entry_n_flush_next with list of registers. See ../verilog/work/lq_odq.v:1049, ../verilog/work/lq_odq.v:968 +Warning: Replacing memory \orderq_entry_val2_next with list of registers. See ../verilog/work/lq_odq.v:1048, ../verilog/work/lq_odq.v:967 +Warning: Replacing memory \orderq_entry_bi_flush_next with list of registers. See ../verilog/work/lq_odq.v:1047, ../verilog/work/lq_odq.v:966 +Warning: Replacing memory \orderq_entry_bi_flag_next with list of registers. See ../verilog/work/lq_odq.v:1046, ../verilog/work/lq_odq.v:965 +Warning: Replacing memory \orderq_entry_cmmt_next with list of registers. See ../verilog/work/lq_odq.v:1045, ../verilog/work/lq_odq.v:964 +Warning: Replacing memory \orderq_entry_stTag_next with list of registers. See ../verilog/work/lq_odq.v:1044, ../verilog/work/lq_odq.v:963 +Warning: Replacing memory \orderq_entry_ld_chk_next with list of registers. See ../verilog/work/lq_odq.v:1043, ../verilog/work/lq_odq.v:962 +Warning: Replacing memory \orderq_entry_myflush_next with list of registers. See ../verilog/work/lq_odq.v:1042, ../verilog/work/lq_odq.v:961 +Warning: Replacing memory \orderq_entry_flushed_next with list of registers. See ../verilog/work/lq_odq.v:1041, ../verilog/work/lq_odq.v:960 +Warning: Replacing memory \orderq_entry_instq_next with list of registers. See ../verilog/work/lq_odq.v:1040, ../verilog/work/lq_odq.v:959 +Warning: Replacing memory \orderq_entry_pre_next with list of registers. See ../verilog/work/lq_odq.v:1039, ../verilog/work/lq_odq.v:958 +Warning: Replacing memory \orderq_entry_pEvents_next with list of registers. See ../verilog/work/lq_odq.v:1038, ../verilog/work/lq_odq.v:957 +Warning: Replacing memory \orderq_entry_eccue_next with list of registers. See ../verilog/work/lq_odq.v:1037, ../verilog/work/lq_odq.v:956 +Warning: Replacing memory \orderq_entry_dacrw_next with list of registers. See ../verilog/work/lq_odq.v:1036, ../verilog/work/lq_odq.v:955 +Warning: Replacing memory \orderq_entry_cls_op_next with list of registers. See ../verilog/work/lq_odq.v:1035, ../verilog/work/lq_odq.v:954 +Warning: Replacing memory \orderq_entry_fwd_next with list of registers. See ../verilog/work/lq_odq.v:1034, ../verilog/work/lq_odq.v:953 +Warning: Replacing memory \orderq_entry_hit_next with list of registers. See ../verilog/work/lq_odq.v:1033, ../verilog/work/lq_odq.v:952 +Warning: Replacing memory \orderq_entry_i_next with list of registers. See ../verilog/work/lq_odq.v:1032, ../verilog/work/lq_odq.v:951 +Warning: Replacing memory \orderq_entry_efs_next with list of registers. See ../verilog/work/lq_odq.v:1031, ../verilog/work/lq_odq.v:950 +Warning: Replacing memory \orderq_entry_ld_next with list of registers. See ../verilog/work/lq_odq.v:1030, ../verilog/work/lq_odq.v:949 +Warning: Replacing memory \orderq_entry_val_next with list of registers. See ../verilog/work/lq_odq.v:1029, ../verilog/work/lq_odq.v:948 +Warning: Replacing memory \orderq_entry_tid_next with list of registers. See ../verilog/work/lq_odq.v:1028, ../verilog/work/lq_odq.v:947 +Warning: Replacing memory \orderq_entry_inuse_next with list of registers. See ../verilog/work/lq_odq.v:1027, ../verilog/work/lq_odq.v:946 +Successfully finished Verilog frontend. + +229. Executing Verilog-2005 frontend: ../verilog/work/lq_perv.v +Parsing Verilog input from `../verilog/work/lq_perv.v' to AST representation. +Generating RTLIL representation for module `\lq_perv'. +Successfully finished Verilog frontend. + +230. Executing Verilog-2005 frontend: ../verilog/work/lq_pfetch.v +Parsing Verilog input from `../verilog/work/lq_pfetch.v' to AST representation. +Generating RTLIL representation for module `\lq_pfetch'. +Successfully finished Verilog frontend. + +231. Executing Verilog-2005 frontend: ../verilog/work/lq_spr.v +Parsing Verilog input from `../verilog/work/lq_spr.v' to AST representation. +Generating RTLIL representation for module `\lq_spr'. +Successfully finished Verilog frontend. + +232. Executing Verilog-2005 frontend: ../verilog/work/lq_spr_cspr.v +Parsing Verilog input from `../verilog/work/lq_spr_cspr.v' to AST representation. +Generating RTLIL representation for module `\lq_spr_cspr'. +Successfully finished Verilog frontend. + +233. Executing Verilog-2005 frontend: ../verilog/work/lq_spr_dacen.v +Parsing Verilog input from `../verilog/work/lq_spr_dacen.v' to AST representation. +Generating RTLIL representation for module `\lq_spr_dacen'. +Successfully finished Verilog frontend. + +234. Executing Verilog-2005 frontend: ../verilog/work/lq_spr_dvccmp.v +Parsing Verilog input from `../verilog/work/lq_spr_dvccmp.v' to AST representation. +Generating RTLIL representation for module `\lq_spr_dvccmp'. +Successfully finished Verilog frontend. + +235. Executing Verilog-2005 frontend: ../verilog/work/lq_spr_tspr.v +Parsing Verilog input from `../verilog/work/lq_spr_tspr.v' to AST representation. +Generating RTLIL representation for module `\lq_spr_tspr'. +Successfully finished Verilog frontend. + +236. Executing Verilog-2005 frontend: ../verilog/work/lq_stq.v +Parsing Verilog input from `../verilog/work/lq_stq.v' to AST representation. +Generating RTLIL representation for module `\lq_stq'. +Warning: Replacing memory \stq_i1_comp_itag with list of registers. See ../verilog/work/lq_stq.v:2598 +Warning: Replacing memory \stq_i0_comp_itag with list of registers. See ../verilog/work/lq_stq.v:2597 +Warning: Replacing memory \stq_cp_next_itag with list of registers. See ../verilog/work/lq_stq.v:2466, ../verilog/work/lq_stq.v:2371 +Successfully finished Verilog frontend. + +237. Executing Verilog-2005 frontend: ../verilog/work/lq_stq_rot.v +Parsing Verilog input from `../verilog/work/lq_stq_rot.v' to AST representation. +Generating RTLIL representation for module `\lq_stq_rot'. +Successfully finished Verilog frontend. + +238. Executing Verilog-2005 frontend: ../verilog/work/mmq.v +Parsing Verilog input from `../verilog/work/mmq.v' to AST representation. +Generating RTLIL representation for module `\mmq'. +Successfully finished Verilog frontend. + +239. Executing Verilog-2005 frontend: ../verilog/work/mmq_dbg.v +Parsing Verilog input from `../verilog/work/mmq_dbg.v' to AST representation. +Generating RTLIL representation for module `\mmq_dbg'. +Successfully finished Verilog frontend. + +240. Executing Verilog-2005 frontend: ../verilog/work/mmq_htw.v +Parsing Verilog input from `../verilog/work/mmq_htw.v' to AST representation. +Generating RTLIL representation for module `\mmq_htw'. +Successfully finished Verilog frontend. + +241. Executing Verilog-2005 frontend: ../verilog/work/mmq_inval.v +Parsing Verilog input from `../verilog/work/mmq_inval.v' to AST representation. +Generating RTLIL representation for module `\mmq_inval'. +Successfully finished Verilog frontend. + +242. Executing Verilog-2005 frontend: ../verilog/work/mmq_perf.v +Parsing Verilog input from `../verilog/work/mmq_perf.v' to AST representation. +Generating RTLIL representation for module `\mmq_perf'. +Successfully finished Verilog frontend. + +243. Executing Verilog-2005 frontend: ../verilog/work/mmq_perv.v +Parsing Verilog input from `../verilog/work/mmq_perv.v' to AST representation. +Generating RTLIL representation for module `\mmq_perv'. +Successfully finished Verilog frontend. + +244. Executing Verilog-2005 frontend: ../verilog/work/mmq_spr.v +Parsing Verilog input from `../verilog/work/mmq_spr.v' to AST representation. +Generating RTLIL representation for module `\mmq_spr'. +Successfully finished Verilog frontend. + +245. Executing Verilog-2005 frontend: ../verilog/work/mmq_tlb_cmp.v +Parsing Verilog input from `../verilog/work/mmq_tlb_cmp.v' to AST representation. +Generating RTLIL representation for module `\mmq_tlb_cmp'. +Successfully finished Verilog frontend. + +246. Executing Verilog-2005 frontend: ../verilog/work/mmq_tlb_ctl.v +Parsing Verilog input from `../verilog/work/mmq_tlb_ctl.v' to AST representation. +Generating RTLIL representation for module `\mmq_tlb_ctl'. +Successfully finished Verilog frontend. + +247. Executing Verilog-2005 frontend: ../verilog/work/mmq_tlb_lrat.v +Parsing Verilog input from `../verilog/work/mmq_tlb_lrat.v' to AST representation. +Generating RTLIL representation for module `\mmq_tlb_lrat'. +Successfully finished Verilog frontend. + +248. Executing Verilog-2005 frontend: ../verilog/work/mmq_tlb_lrat_matchline.v +Parsing Verilog input from `../verilog/work/mmq_tlb_lrat_matchline.v' to AST representation. +Generating RTLIL representation for module `\mmq_tlb_lrat_matchline'. +Successfully finished Verilog frontend. + +249. Executing Verilog-2005 frontend: ../verilog/work/mmq_tlb_matchline.v +Parsing Verilog input from `../verilog/work/mmq_tlb_matchline.v' to AST representation. +Generating RTLIL representation for module `\mmq_tlb_matchline'. +Successfully finished Verilog frontend. + +250. Executing Verilog-2005 frontend: ../verilog/work/mmq_tlb_req.v +Parsing Verilog input from `../verilog/work/mmq_tlb_req.v' to AST representation. +Generating RTLIL representation for module `\mmq_tlb_req'. +Successfully finished Verilog frontend. + +251. Executing Verilog-2005 frontend: ../verilog/work/mmu_a2o.vh +Parsing Verilog input from `../verilog/work/mmu_a2o.vh' to AST representation. +Successfully finished Verilog frontend. + +252. Executing Verilog-2005 frontend: ../verilog/work/pcq.v +Parsing Verilog input from `../verilog/work/pcq.v' to AST representation. +Generating RTLIL representation for module `\pcq'. +Successfully finished Verilog frontend. + +253. Executing Verilog-2005 frontend: ../verilog/work/pcq_clks.v +Parsing Verilog input from `../verilog/work/pcq_clks.v' to AST representation. +Generating RTLIL representation for module `\pcq_clks'. +Successfully finished Verilog frontend. + +254. Executing Verilog-2005 frontend: ../verilog/work/pcq_clks_ctrl.v +Parsing Verilog input from `../verilog/work/pcq_clks_ctrl.v' to AST representation. +Generating RTLIL representation for module `\pcq_clks_ctrl'. +Successfully finished Verilog frontend. + +255. Executing Verilog-2005 frontend: ../verilog/work/pcq_clks_stg.v +Parsing Verilog input from `../verilog/work/pcq_clks_stg.v' to AST representation. +Generating RTLIL representation for module `\pcq_clks_stg'. +Successfully finished Verilog frontend. + +256. Executing Verilog-2005 frontend: ../verilog/work/pcq_ctrl.v +Parsing Verilog input from `../verilog/work/pcq_ctrl.v' to AST representation. +Generating RTLIL representation for module `\pcq_ctrl'. +Successfully finished Verilog frontend. + +257. Executing Verilog-2005 frontend: ../verilog/work/pcq_dbg.v +Parsing Verilog input from `../verilog/work/pcq_dbg.v' to AST representation. +Generating RTLIL representation for module `\pcq_dbg'. +Successfully finished Verilog frontend. + +258. Executing Verilog-2005 frontend: ../verilog/work/pcq_local_fir2.v +Parsing Verilog input from `../verilog/work/pcq_local_fir2.v' to AST representation. +Generating RTLIL representation for module `\pcq_local_fir2'. +Successfully finished Verilog frontend. + +259. Executing Verilog-2005 frontend: ../verilog/work/pcq_regs.v +Parsing Verilog input from `../verilog/work/pcq_regs.v' to AST representation. +Generating RTLIL representation for module `\pcq_regs'. +Successfully finished Verilog frontend. + +260. Executing Verilog-2005 frontend: ../verilog/work/pcq_regs_fir.v +Parsing Verilog input from `../verilog/work/pcq_regs_fir.v' to AST representation. +Generating RTLIL representation for module `\pcq_regs_fir'. +Successfully finished Verilog frontend. + +261. Executing Verilog-2005 frontend: ../verilog/work/pcq_spr.v +Parsing Verilog input from `../verilog/work/pcq_spr.v' to AST representation. +Generating RTLIL representation for module `\pcq_spr'. +Successfully finished Verilog frontend. + +262. Executing Verilog-2005 frontend: ../verilog/work/rv.v +Parsing Verilog input from `../verilog/work/rv.v' to AST representation. +Generating RTLIL representation for module `\rv'. +Successfully finished Verilog frontend. + +263. Executing Verilog-2005 frontend: ../verilog/work/rv_axu0_rvs.v +Parsing Verilog input from `../verilog/work/rv_axu0_rvs.v' to AST representation. +Generating RTLIL representation for module `\rv_axu0_rvs'. +Successfully finished Verilog frontend. + +264. Executing Verilog-2005 frontend: ../verilog/work/rv_barf.v +Parsing Verilog input from `../verilog/work/rv_barf.v' to AST representation. +Generating RTLIL representation for module `\rv_barf'. +Successfully finished Verilog frontend. + +265. Executing Verilog-2005 frontend: ../verilog/work/rv_cmpitag.v +Parsing Verilog input from `../verilog/work/rv_cmpitag.v' to AST representation. +Generating RTLIL representation for module `\rv_cmpitag'. +Successfully finished Verilog frontend. + +266. Executing Verilog-2005 frontend: ../verilog/work/rv_decode.v +Parsing Verilog input from `../verilog/work/rv_decode.v' to AST representation. +Generating RTLIL representation for module `\rv_decode'. +Successfully finished Verilog frontend. + +267. Executing Verilog-2005 frontend: ../verilog/work/rv_dep.v +Parsing Verilog input from `../verilog/work/rv_dep.v' to AST representation. +Generating RTLIL representation for module `\rv_dep'. +Successfully finished Verilog frontend. + +268. Executing Verilog-2005 frontend: ../verilog/work/rv_dep_scard.v +Parsing Verilog input from `../verilog/work/rv_dep_scard.v' to AST representation. +Generating RTLIL representation for module `\rv_dep_scard'. +Successfully finished Verilog frontend. + +269. Executing Verilog-2005 frontend: ../verilog/work/rv_deps.v +Parsing Verilog input from `../verilog/work/rv_deps.v' to AST representation. +Generating RTLIL representation for module `\rv_deps'. +Successfully finished Verilog frontend. + +270. Executing Verilog-2005 frontend: ../verilog/work/rv_fx0_rvs.v +Parsing Verilog input from `../verilog/work/rv_fx0_rvs.v' to AST representation. +Generating RTLIL representation for module `\rv_fx0_rvs'. +Successfully finished Verilog frontend. + +271. Executing Verilog-2005 frontend: ../verilog/work/rv_fx1_rvs.v +Parsing Verilog input from `../verilog/work/rv_fx1_rvs.v' to AST representation. +Generating RTLIL representation for module `\rv_fx1_rvs'. +Successfully finished Verilog frontend. + +272. Executing Verilog-2005 frontend: ../verilog/work/rv_lq_rvs.v +Parsing Verilog input from `../verilog/work/rv_lq_rvs.v' to AST representation. +Generating RTLIL representation for module `\rv_lq_rvs'. +Successfully finished Verilog frontend. + +273. Executing Verilog-2005 frontend: ../verilog/work/rv_perv.v +Parsing Verilog input from `../verilog/work/rv_perv.v' to AST representation. +Generating RTLIL representation for module `\rv_perv'. +Successfully finished Verilog frontend. + +274. Executing Verilog-2005 frontend: ../verilog/work/rv_pri.v +Parsing Verilog input from `../verilog/work/rv_pri.v' to AST representation. +Generating RTLIL representation for module `\rv_pri'. +Successfully finished Verilog frontend. + +275. Executing Verilog-2005 frontend: ../verilog/work/rv_primux.v +Parsing Verilog input from `../verilog/work/rv_primux.v' to AST representation. +Generating RTLIL representation for module `\rv_primux'. +Successfully finished Verilog frontend. + +276. Executing Verilog-2005 frontend: ../verilog/work/rv_prisel.v +Parsing Verilog input from `../verilog/work/rv_prisel.v' to AST representation. +Generating RTLIL representation for module `\rv_prisel'. +Successfully finished Verilog frontend. + +277. Executing Verilog-2005 frontend: ../verilog/work/rv_rf_byp.v +Parsing Verilog input from `../verilog/work/rv_rf_byp.v' to AST representation. +Generating RTLIL representation for module `\rv_rf_byp'. +Successfully finished Verilog frontend. + +278. Executing Verilog-2005 frontend: ../verilog/work/rv_rpri.v +Parsing Verilog input from `../verilog/work/rv_rpri.v' to AST representation. +Generating RTLIL representation for module `\rv_rpri'. +Successfully finished Verilog frontend. + +279. Executing Verilog-2005 frontend: ../verilog/work/rv_station.v +Parsing Verilog input from `../verilog/work/rv_station.v' to AST representation. +Generating RTLIL representation for module `\rv_station'. +Successfully finished Verilog frontend. + +280. Executing Verilog-2005 frontend: ../verilog/work/xu.v +Parsing Verilog input from `../verilog/work/xu.v' to AST representation. +Generating RTLIL representation for module `\xu'. +Successfully finished Verilog frontend. + +281. Executing Verilog-2005 frontend: ../verilog/work/xu0.v +Parsing Verilog input from `../verilog/work/xu0.v' to AST representation. +Generating RTLIL representation for module `\xu0'. +Successfully finished Verilog frontend. + +282. Executing Verilog-2005 frontend: ../verilog/work/xu0_bcd.v +Parsing Verilog input from `../verilog/work/xu0_bcd.v' to AST representation. +Generating RTLIL representation for module `\xu0_bcd'. +Successfully finished Verilog frontend. + +283. Executing Verilog-2005 frontend: ../verilog/work/xu0_bcd_bcdtd.v +Parsing Verilog input from `../verilog/work/xu0_bcd_bcdtd.v' to AST representation. +Generating RTLIL representation for module `\xu0_bcd_bcdtd'. +Successfully finished Verilog frontend. + +284. Executing Verilog-2005 frontend: ../verilog/work/xu0_bcd_dtbcd.v +Parsing Verilog input from `../verilog/work/xu0_bcd_dtbcd.v' to AST representation. +Generating RTLIL representation for module `\xu0_bcd_dtbcd'. +Successfully finished Verilog frontend. + +285. Executing Verilog-2005 frontend: ../verilog/work/xu0_bprm.v +Parsing Verilog input from `../verilog/work/xu0_bprm.v' to AST representation. +Generating RTLIL representation for module `\xu0_bprm'. +Successfully finished Verilog frontend. + +286. Executing Verilog-2005 frontend: ../verilog/work/xu0_br.v +Parsing Verilog input from `../verilog/work/xu0_br.v' to AST representation. +Generating RTLIL representation for module `\xu0_br'. +Successfully finished Verilog frontend. + +287. Executing Verilog-2005 frontend: ../verilog/work/xu0_byp.v +Parsing Verilog input from `../verilog/work/xu0_byp.v' to AST representation. +Generating RTLIL representation for module `\xu0_byp'. +Successfully finished Verilog frontend. + +288. Executing Verilog-2005 frontend: ../verilog/work/xu0_dec.v +Parsing Verilog input from `../verilog/work/xu0_dec.v' to AST representation. +Generating RTLIL representation for module `\xu0_dec'. +Successfully finished Verilog frontend. + +289. Executing Verilog-2005 frontend: ../verilog/work/xu0_div_r4.v +Parsing Verilog input from `../verilog/work/xu0_div_r4.v' to AST representation. +Generating RTLIL representation for module `\xu0_div_r4'. +Successfully finished Verilog frontend. + +290. Executing Verilog-2005 frontend: ../verilog/work/xu0_dlmzb.v +Parsing Verilog input from `../verilog/work/xu0_dlmzb.v' to AST representation. +Generating RTLIL representation for module `\xu0_dlmzb'. +Successfully finished Verilog frontend. + +291. Executing Verilog-2005 frontend: ../verilog/work/xu1.v +Parsing Verilog input from `../verilog/work/xu1.v' to AST representation. +Generating RTLIL representation for module `\xu1'. +Successfully finished Verilog frontend. + +292. Executing Verilog-2005 frontend: ../verilog/work/xu1_byp.v +Parsing Verilog input from `../verilog/work/xu1_byp.v' to AST representation. +Generating RTLIL representation for module `\xu1_byp'. +Successfully finished Verilog frontend. + +293. Executing Verilog-2005 frontend: ../verilog/work/xu1_dec.v +Parsing Verilog input from `../verilog/work/xu1_dec.v' to AST representation. +Generating RTLIL representation for module `\xu1_dec'. +Successfully finished Verilog frontend. + +294. Executing Verilog-2005 frontend: ../verilog/work/xu_alu.v +Parsing Verilog input from `../verilog/work/xu_alu.v' to AST representation. +Generating RTLIL representation for module `\xu_alu'. +Successfully finished Verilog frontend. + +295. Executing Verilog-2005 frontend: ../verilog/work/xu_alu_add.v +Parsing Verilog input from `../verilog/work/xu_alu_add.v' to AST representation. +Generating RTLIL representation for module `\xu_alu_add'. +Successfully finished Verilog frontend. + +296. Executing Verilog-2005 frontend: ../verilog/work/xu_alu_cmp.v +Parsing Verilog input from `../verilog/work/xu_alu_cmp.v' to AST representation. +Generating RTLIL representation for module `\xu_alu_cmp'. +Successfully finished Verilog frontend. + +297. Executing Verilog-2005 frontend: ../verilog/work/xu_fctr.v +Parsing Verilog input from `../verilog/work/xu_fctr.v' to AST representation. +Generating RTLIL representation for module `\xu_fctr'. +Successfully finished Verilog frontend. + +298. Executing Verilog-2005 frontend: ../verilog/work/xu_gpr.v +Parsing Verilog input from `../verilog/work/xu_gpr.v' to AST representation. +Generating RTLIL representation for module `\xu_gpr'. +Successfully finished Verilog frontend. + +299. Executing Verilog-2005 frontend: ../verilog/work/xu_rf.v +Parsing Verilog input from `../verilog/work/xu_rf.v' to AST representation. +Generating RTLIL representation for module `\xu_rf'. +Warning: Replacing memory \reg_d with list of registers. See ../verilog/work/xu_rf.v:229 +Successfully finished Verilog frontend. + +300. Executing Verilog-2005 frontend: ../verilog/work/xu_spr.v +Parsing Verilog input from `../verilog/work/xu_spr.v' to AST representation. +Generating RTLIL representation for module `\xu_spr'. +Successfully finished Verilog frontend. + +301. Executing Verilog-2005 frontend: ../verilog/work/xu_spr_cspr.v +Parsing Verilog input from `../verilog/work/xu_spr_cspr.v' to AST representation. +Generating RTLIL representation for module `\xu_spr_cspr'. +Successfully finished Verilog frontend. + +302. Executing Verilog-2005 frontend: ../verilog/work/xu_spr_tspr.v +Parsing Verilog input from `../verilog/work/xu_spr_tspr.v' to AST representation. +Generating RTLIL representation for module `\xu_spr_tspr'. +Successfully finished Verilog frontend. + +303. Executing HIERARCHY pass (managing design hierarchy). + +303.1. Analyzing design hierarchy.. +Top module: \c +Used module: \c_perv_rp +Used module: \tri_rlmreg_p +Used module: \tri_slat_scan +Used module: \tri_plat +Used module: \tri_lcbs +Used module: \tri_lcbor +Used module: \tri_lcbcntl_mac +Used module: \c_fu_pc +Used module: \fu +Used module: \fu_dcd +Used module: \tri_debug_mux4 +Used module: \tri_event_mux1t +Used module: \tri_ser_rlmreg_p +Used module: \tri_aoi22_nlats_wlcb +Used module: \tri_parity_recovery +Used module: \tri_direct_err_rpt +Used module: \tri_rlmlatch_p +Used module: \fu_mad +Used module: \fu_tbllut +Used module: \tri_lcbnd +Used module: \tri_inv_nlats +Used module: \tri_fu_tblmul +Used module: \tri_fu_csa22_h2 +Used module: \tri_csa32 +Used module: \tri_nand3 +Used module: \tri_nand2 +Used module: \tri_xor3 +Used module: \tri_csa42 +Used module: \tri_fu_tblmul_bthrow +Used module: \tri_fu_mul_bthmux +Used module: \tri_fu_tblmul_bthdcd +Used module: \fu_tblres +Used module: \fu_tblsqo +Used module: \fu_tblsqe +Used module: \fu_tblexp +Used module: \fu_oscr +Used module: \fu_cr2 +Used module: \fu_pic +Used module: \fu_divsqrt +Used module: \tri_xor2 +Used module: \fu_divsqrt_nq_table +Used module: \tri_inv +Used module: \tri_nand4 +Used module: \fu_divsqrt_q_table +Used module: \tri_nor2 +Used module: \tri_nor3 +Used module: \fu_divsqrt_add4 +Used module: \tri_aoi21 +Used module: \tri_oai21 +Used module: \fu_gst +Used module: \fu_gst_add11 +Used module: \fu_gst_loa +Used module: \fu_gst_inc19 +Used module: \fu_rnd +Used module: \fu_nrm +Used module: \tri_nand2_nlats +Used module: \fu_nrm_or16 +Used module: \fu_nrm_sh +Used module: \fu_lza +Used module: \fu_lza_clz +Used module: \fu_lza_ej +Used module: \fu_lze +Used module: \fu_add +Used module: \fu_add_glbc +Used module: \fu_hc16pp_lsb +Used module: \fu_hc16pp +Used module: \fu_hc16pp_msb +Used module: \fu_loc8inc +Used module: \fu_loc8inc_lsb +Used module: \fu_add_all1 +Used module: \fu_sa3 +Used module: \fu_alg +Used module: \fu_alg_bypmux +Used module: \fu_alg_sh16 +Used module: \fu_alg_or16 +Used module: \fu_alg_sh4 +Used module: \fu_alg_add +Used module: \tri_fu_mul +Used module: \tri_fu_mul_62 +Used module: \tri_fu_mul_92 +Used module: \tri_fu_mul_bthrow +Used module: \tri_fu_mul_bthdcd +Used module: \fu_eov +Used module: \fu_eie +Used module: \fu_fmt +Used module: \fu_byp +Used module: \fu_sto +Used module: \fu_fpr +Used module: \tri_lcbcntl_array_mac +Used module: \tri_144x78_2r4w +Used module: \fu_perv +Used module: \pcq +Used module: \pcq_clks +Used module: \pcq_clks_stg +Used module: \pcq_clks_ctrl +Used module: \pcq_spr +Used module: \pcq_dbg +Used module: \tri_debug_mux8 +Used module: \pcq_ctrl +Used module: \pcq_regs +Used module: \pcq_regs_fir +Used module: \tri_nlat_scan +Used module: \tri_err_rpt +Used module: \pcq_local_fir2 +Used module: \tri_nlat +Used module: \tri_scom_addr_decode +Used module: \tri_serial_scom2 +Used module: \mmq +Used module: \tri_128x16_1r1w_1 +Used module: \tri_128x168_1w_0 +Used module: \mmq_htw +Used module: \mmq_tlb_lrat +Used module: \mmq_tlb_lrat_matchline +Used module: \mmq_tlb_cmp +Used module: \tri_regk +Used module: \mmq_tlb_matchline +Used module: \mmq_tlb_ctl +Used module: \mmq_tlb_req +Used module: \mmq_perv +Used module: \mmq_perf +Used module: \mmq_dbg +Used module: \tri_debug_mux16 +Used module: \mmq_spr +Used module: \mmq_inval +Used module: \lq +Used module: \lq_perv +Used module: \tri_debug_mux32 +Used module: \lq_lsq +Used module: \tri_64x34_8w_1r1w +Used module: \lq_arb +Used module: \lq_imq +Used module: \lq_stq +Used module: \lq_stq_rot +Used module: \tri_aoi22 +Used module: \tri_addrcmp +Used module: \lq_spr_dvccmp +Used module: \tri_agecmp +Used module: \lq_ldq +Used module: \lq_ldq_relq +Used module: \lq_ldq_rot +Used module: \tri_rot16_lu +Used module: \lq_odq +Used module: \lq_data +Used module: \tri_256x144_8w_1r1w +Used module: \lq_data_ld +Used module: \tri_rot16_ru +Used module: \tri_rot16s_ru +Used module: \lq_data_st +Used module: \tri_lq_rmw +Used module: \lq_ctl +Used module: \lq_pfetch +Used module: \tri_32x70_2w_1r1w +Used module: \lq_derat +Used module: \tri_cam_32x143_1r1w1c +Used module: \tri_cam_32x143_1r1w1c_matchline +Used module: \lq_dir +Used module: \lq_agen +Used module: \lq_agen_lo +Used module: \tri_xnor2 +Used module: \lq_agen_csmuxe +Used module: \lq_agen_csmux +Used module: \lq_agen_glbglb +Used module: \lq_agen_glbloc_lsb +Used module: \lq_agen_glbloc +Used module: \lq_agen_locae +Used module: \lq_agen_loca +Used module: \lq_dir_tag +Used module: \lq_dir_tag_arr +Used module: \lq_dir_lru +Used module: \lq_dir_val +Used module: \lq_spr +Used module: \lq_spr_tspr +Used module: \lq_spr_cspr +Used module: \lq_spr_dacen +Used module: \lq_dcc +Used module: \lq_fgen +Used module: \lq_byp +Used module: \lq_dec +Used module: \lq_axu_dec +Used module: \rv +Used module: \rv_perv +Used module: \rv_rf_byp +Used module: \rv_pri +Used module: \rv_axu0_rvs +Used module: \rv_station +Used module: \rv_cmpitag +Used module: \rv_prisel +Used module: \rv_rpri +Used module: \rv_primux +Used module: \rv_barf +Used module: \rv_lq_rvs +Used module: \rv_fx1_rvs +Used module: \rv_fx0_rvs +Used module: \rv_deps +Used module: \rv_decode +Used module: \rv_dep +Used module: \rv_dep_scard +Used module: \xu +Used module: \xu_spr +Used module: \xu_spr_tspr +Used module: \tri_regs +Used module: \tri_64x72_1r1w +Used module: \xu_spr_cspr +Used module: \xu_fctr +Used module: \tri_eccgen +Used module: \tri_eccchk +Used module: \xu_gpr +Used module: \xu_rf +Used module: \xu1 +Used module: \xu1_dec +Used module: \xu1_byp +Used module: \xu_alu +Used module: \xu_alu_cmp +Used module: \tri_st_or3232 +Used module: \tri_st_rot +Used module: \tri_st_or3232_b +Used module: \tri_st_rot_rol64 +Used module: \tri_st_rot_ins +Used module: \tri_st_rot_mask +Used module: \tri_st_rot_dec +Used module: \xu_alu_add +Used module: \tri_st_add +Used module: \tri_st_add_csmux +Used module: \tri_st_add_glbglbci +Used module: \tri_st_add_glbloc +Used module: \tri_st_add_loc +Used module: \xu0 +Used module: \xu0_bprm +Used module: \xu0_dec +Used module: \tri_pri +Used module: \xu0_byp +Used module: \xu0_br +Used module: \tri_st_mult +Used module: \tri_st_mult_core +Used module: \tri_csa22 +Used module: \tri_st_mult_boothrow +Used module: \tri_bthmx +Used module: \tri_st_mult_boothdcd +Used module: \xu0_div_r4 +Used module: \xu0_dlmzb +Used module: \xu0_bcd +Used module: \xu0_bcd_dtbcd +Used module: \xu0_bcd_bcdtd +Used module: \tri_st_cntlz +Used module: \tri_st_cntlz_8b +Used module: \tri_st_popcnt +Used module: \tri_st_popcnt_byte +Used module: \tri_st_popcnt_word +Used module: \iuq +Used module: \iuq_cpl_top +Used module: \iuq_dbg +Used module: \iuq_cpl +Used module: \tri_iuq_cpl_arr +Used module: \iuq_cpl_ctrl +Used module: \iuq_cpl_itag +Used module: \iuq_cpl_table +Used module: \iuq_cpl_dec +Used module: \iuq_slice_top +Used module: \iuq_dispatch +Used module: \iuq_slice +Used module: \iuq_rn_top +Used module: \iuq_axu_fu_rn +Used module: \iuq_rn_map +Used module: \iuq_rn_map_inc +Used module: \iuq_rn +Used module: \iuq_cpl_ctrl_inc +Used module: \iuq_dec_top +Used module: \iuq_axu_fu_dec +Used module: \iuq_idec +Used module: \iuq_ibuf +Used module: \tri_bht_512x4_1r1w +Used module: \tri_512x16_1r1w_1 +Used module: \tri_bht_1024x8_1r1w +Used module: \iuq_ifetch +Used module: \iuq_uc +Used module: \iuq_uc_rom_odd +Used module: \iuq_uc_rom_even +Used module: \iuq_uc_control +Used module: \iuq_uc_cplbuffer +Used module: \iuq_uc_buffer +Used module: \iuq_bp +Used module: \iuq_ram +Used module: \iuq_ic +Used module: \iuq_ic_miss +Used module: \iuq_ic_miss_table +Used module: \iuq_bd +Used module: \iuq_ic_dir +Used module: \tri_512x162_4w_0 +Used module: \tri_128x34_4w_1r1w +Used module: \iuq_ic_select +Used module: \iuq_ic_ierat +Used module: \tri_cam_16x143_1r1w1c +Used module: \tri_cam_16x143_1r1w1c_matchline +Used module: \iuq_spr +Used module: \iuq_btb +Parameter \WIDTH = 136 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.2. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 136 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$94953c4e8d41c8a82cad16afc857bcd81a5879a1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.3. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.4. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$5f5963a8c9b38b74f9c392a01f96c63bcea9481f\tri_rlmreg_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5f5963a8c9b38b74f9c392a01f96c63bcea9481f\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.5. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5f5963a8c9b38b74f9c392a01f96c63bcea9481f\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.6. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5f5963a8c9b38b74f9c392a01f96c63bcea9481f\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5f5963a8c9b38b74f9c392a01f96c63bcea9481f\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 78 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5f5963a8c9b38b74f9c392a01f96c63bcea9481f\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.7. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110100010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8c106316bf3723c41b94cb54231a0d509894e197\tri_inv_nlats'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.8. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Reprocessing module tri_256x144_8w_1r1w because instantiated module tri_inv_nlats has become available. +Generating RTLIL representation for module `\tri_256x144_8w_1r1w'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.9. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$fca630cf56c7547559b6971fc0fa25e8343d9ee2\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fca630cf56c7547559b6971fc0fa25e8343d9ee2\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.10. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.11. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.12. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_regk'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_regk'. +Parameter \WIDTH = 1 + +303.13. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 1 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 648 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.14. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 648 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$1fac2a6f9a7ee724fab4b672508746821ac878c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 272 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.15. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 272 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$7ec28192059c7ba5eb55880e1e247617fea5e668\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 + +303.16. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 + +303.17. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 + +303.18. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 + +303.19. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \INIT = 0 + +303.20. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmlatch_p'. +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 + +303.21. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 + +303.22. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 + +303.23. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Generating RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_16x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 + +303.24. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Generating RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \HAVE_XBIT = 1 +Parameter \NUM_PGSIZES = 5 +Parameter \HAVE_CMPMASK = 1 +Parameter \CMPMASK_WIDTH = 4 +Found cached RTLIL representation for module `$paramod$c13b6a0a23793bad94671c1a74102d1f5f91e930\tri_cam_32x143_1r1w1c_matchline'. +Parameter \float_type = 1 + +303.25. Executing AST frontend in derive mode using pre-parsed AST for module `\c_fu_pc'. +Parameter \float_type = 1 +Generating RTLIL representation for module `$paramod\c_fu_pc\float_type=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 + +303.26. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat_scan'. +Parameter \inst = 0 + +303.27. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_fu_mul_92'. +Parameter \inst = 0 +Generating RTLIL representation for module `$paramod\tri_fu_mul_92\inst=s32'00000000000000000000000000000000'. +Parameter \inst = 1 + +303.28. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_fu_mul_92'. +Parameter \inst = 1 +Generating RTLIL representation for module `$paramod\tri_fu_mul_92\inst=s32'00000000000000000000000000000001'. +Parameter \inst = 2 + +303.29. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_fu_mul_92'. +Parameter \inst = 2 +Generating RTLIL representation for module `$paramod\tri_fu_mul_92\inst=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 + +303.30. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$dc51ee1c22d3854a177550990723aa69d95e564c\tri_rlmreg_p'. +Parameter \WIDTH = 71 +Parameter \NEEDS_SRESET = 0 + +303.31. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 71 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$4e18ee5a8ecf2a76457c692a35982cc8b4c917b5\tri_inv_nlats'. +Parameter \WIDTH = 73 +Parameter \NEEDS_SRESET = 0 + +303.32. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 73 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$c00135faf44c57203253a717f1253601e344d0c6\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.33. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.34. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.35. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_rlmreg_p'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 + +303.36. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_direct_err_rpt'. +Parameter \WIDTH = 2 +Generating RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 + +303.37. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 31 +Parameter \INIT = 0 + +303.38. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 31 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$65bbe9eae0e710410de627977402915d38827da2\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 4 + +303.39. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 4 +Generating RTLIL representation for module `$paramod$04a45485d1ecdf3181501464f2473125a1932e31\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 + +303.40. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 16 + +303.41. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 16 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 + +303.42. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi22'. +Parameter \WIDTH = 16 +Generating RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 + +303.43. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 16 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.44. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$20f18def66c68f37ac0d0fc3323dabca0b19bf31\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.45. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7ba4767c4179b3f56907ca2d1f0aaf626a0cfb19\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7ba4767c4179b3f56907ca2d1f0aaf626a0cfb19\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.46. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$4ad8598ddeec1374931cc327c9add27332ce07ab\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4ad8598ddeec1374931cc327c9add27332ce07ab\tri_inv_nlats'. +Parameter \WIDTH = 1 +Parameter \INIT = 1'0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.47. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 1 +Parameter \INIT = 1'0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$a6ce607e577401e20502da2f474acf2cc5989c1b\tri_inv_nlats'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 4 + +303.48. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi22'. +Parameter \WIDTH = 4 +Generating RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 + +303.49. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 4 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7ba4767c4179b3f56907ca2d1f0aaf626a0cfb19\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4ad8598ddeec1374931cc327c9add27332ce07ab\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7ba4767c4179b3f56907ca2d1f0aaf626a0cfb19\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4ad8598ddeec1374931cc327c9add27332ce07ab\tri_inv_nlats'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$20f18def66c68f37ac0d0fc3323dabca0b19bf31\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7ba4767c4179b3f56907ca2d1f0aaf626a0cfb19\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7ba4767c4179b3f56907ca2d1f0aaf626a0cfb19\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4ad8598ddeec1374931cc327c9add27332ce07ab\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4ad8598ddeec1374931cc327c9add27332ce07ab\tri_inv_nlats'. +Parameter \WIDTH = 1 +Parameter \INIT = 1'0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$a6ce607e577401e20502da2f474acf2cc5989c1b\tri_inv_nlats'. +Parameter \WIDTH = 6 + +303.50. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 6 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 + +303.51. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 6 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 + +303.52. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi22'. +Parameter \WIDTH = 6 +Generating RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 8 + +303.53. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 8 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 + +303.54. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi22'. +Parameter \WIDTH = 8 +Generating RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 1 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \IBUF = 1'0 +Parameter \DUALSCAN = { } +Parameter \NEEDS_SRESET = 1 + +303.55. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi22_nlats_wlcb'. +Parameter \WIDTH = 1 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \IBUF = 1'0 +Parameter \DUALSCAN = { } +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$c112ca8bec6e25097f01c75ddb178ff7fc837051\tri_aoi22_nlats_wlcb'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 + +303.56. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 1 + +303.57. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$76fa76ab5391b108df7d449429f332daba3dbad1\tri_nlat_scan'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76fa76ab5391b108df7d449429f332daba3dbad1\tri_nlat_scan'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bcf79c9415814002fe29ea2804891d57bcc0d105\tri_nlat'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Parameter \NEEDS_SRESET = 1 + +303.58. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$b66b477d2f27ed0a3dd5cdb6d5d7a7427989ef53\tri_nlat_scan'. +Parameter \WIDTH = 13 +Parameter \INIT = 13'0000000000000 +Parameter \NEEDS_SRESET = 1 + +303.59. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 13 +Parameter \INIT = 13'0000000000000 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$b610fa48b5abb656c67e47e288cb53798b1a7d00\tri_nlat_scan'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 1 + +303.60. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$85766448eace62ba032b477332e9751307545bb2\tri_nlat_scan'. +Parameter \WIDTH = 64 +Parameter \NEEDS_SRESET = 1 + +303.61. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 64 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$9a93d85e878602f6752a4d0dda4ebe4c5b310791\tri_nlat_scan'. +Parameter \WIDTH = 7 +Parameter \INIT = 7'0000000 +Parameter \NEEDS_SRESET = 1 + +303.62. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nlat_scan'. +Parameter \WIDTH = 7 +Parameter \INIT = 7'0000000 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$c0cecc88f21cb8738eb3779885542b12a86f69db\tri_nlat_scan'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b66b477d2f27ed0a3dd5cdb6d5d7a7427989ef53\tri_nlat_scan'. +Parameter \WIDTH = 1 +Parameter \MASK_RESET_VALUE = 1'0 +Parameter \INLINE = 1'0 +Parameter \NEEDS_SRESET = 1 + +303.63. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_err_rpt'. +Parameter \WIDTH = 1 +Parameter \MASK_RESET_VALUE = 1'0 +Parameter \INLINE = 1'0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$1dea32e2fdf1d422277f79ef9785bc857f846f36\tri_err_rpt'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.64. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$7eb1dce228670199bb3cee814e4361f5f8bd3fb9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7eb1dce228670199bb3cee814e4361f5f8bd3fb9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.65. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.66. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.67. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.68. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.69. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 68 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.70. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 68 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$4e105288727f76d92b7402e213c8e944b259ceb3\tri_inv_nlats'. +Parameter \WIDTH = 69 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.71. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 69 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$d7b8faf610229160763f0f0258b65a2d1f987019\tri_inv_nlats'. +Parameter \WIDTH = 44 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.72. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 44 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$4aa2fbbf06d50b291d9c4caeae787a9da5b852b8\tri_inv_nlats'. +Parameter \WIDTH = 45 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.73. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 45 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$8e66c8f62f0f402fdf7ee7e936602de31d9d5637\tri_inv_nlats'. +Parameter \WIDTH = 45 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8e66c8f62f0f402fdf7ee7e936602de31d9d5637\tri_inv_nlats'. +Parameter \WIDTH = 47 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.74. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 47 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$67208169f8f70a8929719f6b0564994d42fe037a\tri_inv_nlats'. +Parameter \WIDTH = 43 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 + +303.75. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 43 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$36685472f23daa055a8e42f264c4d600444bd41d\tri_inv_nlats'. +Parameter \WIDTH = 45 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8e66c8f62f0f402fdf7ee7e936602de31d9d5637\tri_inv_nlats'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 + +303.76. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Generating RTLIL representation for module `$paramod$b8c30629401eedb379b4b782d4d6247be3bd15aa\tri_inv_nlats'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 + +303.77. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110010010111110100000100110001001100100101010001001000 +Generating RTLIL representation for module `$paramod$1e67232b25864060b6eb711e05050b53cd9b74cd\tri_inv_nlats'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \BTR = 128'01001110010011000100100100110000001100000011000000110001010111110101100000110001010111110100000100110001001100100101010001001000 +Found cached RTLIL representation for module `$paramod$b8c30629401eedb379b4b782d4d6247be3bd15aa\tri_inv_nlats'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 15 + +303.78. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 15 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001111'. +Reprocessing module iuq because instantiated module iuq_cpl_top has become available. +Generating RTLIL representation for module `\iuq'. +Parameter \WIDTH = 64 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.79. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$d412adf6af8c0d59d891d9adc67423b740348572\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.80. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$5e4b50cfe0d93dca5bb92eb69884e3169ed86c4f\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \OFFSET = 0 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$d412adf6af8c0d59d891d9adc67423b740348572\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \hvmode = 1 +Parameter \a2mode = 1 + +303.81. Executing AST frontend in derive mode using pre-parsed AST for module `\xu_spr'. +Parameter \hvmode = 1 +Parameter \a2mode = 1 +Generating RTLIL representation for module `$paramod$9f74ae68d5b9be52dd994f498b1d9eb79e9eb110\xu_spr'. +Parameter \PAR_WIDTH = 8 +Parameter \WIDTH = 64 +Parameter \POOL_ENC = 3 +Parameter \POOL = 8 +Parameter \RD_PORTS = 1 +Parameter \WR_PORTS = 1 +Parameter \BYPASS = 1 + +303.82. Executing AST frontend in derive mode using pre-parsed AST for module `\xu_rf'. +Parameter \PAR_WIDTH = 8 +Parameter \WIDTH = 64 +Parameter \POOL_ENC = 3 +Parameter \POOL = 8 +Parameter \RD_PORTS = 1 +Parameter \WR_PORTS = 1 +Parameter \BYPASS = 1 +Generating RTLIL representation for module `$paramod$017ec315f894598bfc5a3640aba9589c79f02a1c\xu_rf'. +Warning: Replacing memory \reg_d with list of registers. See ../verilog/work/xu_rf.v:229 +Parameter \PAR_WIDTH = 8 +Parameter \WIDTH = 64 +Parameter \POOL_ENC = 3 +Parameter \POOL = 8 +Parameter \RD_PORTS = 2 +Parameter \WR_PORTS = 1 +Parameter \BYPASS = 1 + +303.83. Executing AST frontend in derive mode using pre-parsed AST for module `\xu_rf'. +Parameter \PAR_WIDTH = 8 +Parameter \WIDTH = 64 +Parameter \POOL_ENC = 3 +Parameter \POOL = 8 +Parameter \RD_PORTS = 2 +Parameter \WR_PORTS = 1 +Parameter \BYPASS = 1 +Generating RTLIL representation for module `$paramod$bacce616c073c619a3ec25a7d760867eda722364\xu_rf'. +Warning: Replacing memory \reg_d with list of registers. See ../verilog/work/xu_rf.v:229 +Parameter \PAR_WIDTH = 2 +Parameter \WIDTH = 10 +Parameter \POOL_ENC = 4 +Parameter \POOL = 12 +Parameter \RD_PORTS = 4 +Parameter \WR_PORTS = 2 +Parameter \BYPASS = 1 + +303.84. Executing AST frontend in derive mode using pre-parsed AST for module `\xu_rf'. +Parameter \PAR_WIDTH = 2 +Parameter \WIDTH = 10 +Parameter \POOL_ENC = 4 +Parameter \POOL = 12 +Parameter \RD_PORTS = 4 +Parameter \WR_PORTS = 2 +Parameter \BYPASS = 1 +Generating RTLIL representation for module `$paramod$97af005d4bd1a23d2b101ae0483ea20803e7b62e\xu_rf'. +Warning: Replacing memory \reg_d with list of registers. See ../verilog/work/xu_rf.v:229 +Parameter \PAR_WIDTH = 1 +Parameter \WIDTH = 4 +Parameter \POOL_ENC = 5 +Parameter \POOL = 24 +Parameter \RD_PORTS = 4 +Parameter \WR_PORTS = 5 +Parameter \BYPASS = 1 + +303.85. Executing AST frontend in derive mode using pre-parsed AST for module `\xu_rf'. +Parameter \PAR_WIDTH = 1 +Parameter \WIDTH = 4 +Parameter \POOL_ENC = 5 +Parameter \POOL = 24 +Parameter \RD_PORTS = 4 +Parameter \WR_PORTS = 5 +Parameter \BYPASS = 1 +Generating RTLIL representation for module `$paramod$c874fdc2948ff437e701f5cb76dabfe02bec76cf\xu_rf'. +Warning: Replacing memory \reg_d with list of registers. See ../verilog/work/xu_rf.v:229 +Parameter \WAYDATASIZE = 34 +Parameter \XU0_PIPE_START = 2 +Parameter \XU0_PIPE_END = 8 +Parameter \XU1_PIPE_START = 2 +Parameter \XU1_PIPE_END = 5 + +303.86. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_ctl'. +Parameter \WAYDATASIZE = 34 +Parameter \XU0_PIPE_START = 2 +Parameter \XU0_PIPE_END = 8 +Parameter \XU1_PIPE_START = 2 +Parameter \XU1_PIPE_END = 5 +Generating RTLIL representation for module `$paramod$2fde90457072c331057072946b695e5da0395f2c\lq_ctl'. +Parameter \MMQ_TLB_CMP_CSWITCH_0TO7 = 0 + +303.87. Executing AST frontend in derive mode using pre-parsed AST for module `\mmq_tlb_cmp'. +Parameter \MMQ_TLB_CMP_CSWITCH_0TO7 = 0 +Generating RTLIL representation for module `$paramod$a15f48a0f0e3729271924cb2a8b8789ca296faec\mmq_tlb_cmp'. +Parameter \BCFG_MMUCR1_VALUE = 201326592 +Parameter \BCFG_MMUCR2_VALUE = 685361 +Parameter \BCFG_MMUCR3_VALUE = 15 +Parameter \BCFG_MMUCFG_VALUE = 3 +Parameter \BCFG_TLB0CFG_VALUE = 7 +Parameter \MMQ_SPR_CSWITCH_0TO3 = 8 + +303.88. Executing AST frontend in derive mode using pre-parsed AST for module `\mmq_spr'. +Parameter \BCFG_MMUCR1_VALUE = 201326592 +Parameter \BCFG_MMUCR2_VALUE = 685361 +Parameter \BCFG_MMUCR3_VALUE = 15 +Parameter \BCFG_MMUCFG_VALUE = 3 +Parameter \BCFG_TLB0CFG_VALUE = 7 +Parameter \MMQ_SPR_CSWITCH_0TO3 = 8 +Generating RTLIL representation for module `$paramod$dc56c1928e33f110109cea051664fedad9c43281\mmq_spr'. +Parameter \MMQ_INVAL_CSWITCH_0TO3 = 0 + +303.89. Executing AST frontend in derive mode using pre-parsed AST for module `\mmq_inval'. +Parameter \MMQ_INVAL_CSWITCH_0TO3 = 0 +Generating RTLIL representation for module `$paramod\mmq_inval\MMQ_INVAL_CSWITCH_0TO3=s32'00000000000000000000000000000000'. +Reprocessing module mmq because instantiated module mmq_spr has become available. +Generating RTLIL representation for module `\mmq'. +Parameter \WIDTH = 23 +Parameter \INIT = 0 + +303.90. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 23 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$8aed2b06a53bd806ef63ebe68f92da85a6fbe912\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 3'000 + +303.91. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 3 +Parameter \INIT = 3'000 +Generating RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000011\INIT=3'000'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 + +303.92. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 5 +Parameter \INIT = 5'00000 +Generating RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000101\INIT=5'00000'. +Parameter \WIDTH = 8 +Parameter \INIT = 8'00000000 + +303.93. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 8 +Parameter \INIT = 8'00000000 +Generating RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000001000\INIT=8'00000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 + +303.94. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Generating RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000100\INIT=4'0000'. +Parameter \WIDTH = 2 +Parameter \INIT = 2'00 + +303.95. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 2 +Parameter \INIT = 2'00 +Generating RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000010\INIT=2'00'. +Parameter \WIDTH = 15 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001111'. +Parameter \WIDTH = 16 + +303.96. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 16 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 15 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001111'. +Parameter \WIDTH = 16 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000010000'. +Parameter \WIDTH = 6 + +303.97. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 6 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000110'. +Parameter \EFF_IFAR = 20 +Parameter \ITAG_SIZE_ENC = 7 +Parameter \THREAD_POOL_ENC = 0 +Parameter \CR_POOL_ENC = 5 +Parameter \REGMODE = 6 + +303.98. Executing AST frontend in derive mode using pre-parsed AST for module `\fu_dcd'. +Parameter \EFF_IFAR = 20 +Parameter \ITAG_SIZE_ENC = 7 +Parameter \THREAD_POOL_ENC = 0 +Parameter \CR_POOL_ENC = 5 +Parameter \REGMODE = 6 +Generating RTLIL representation for module `$paramod$a49292832bf9c8c58108ddcdf6096f5d4ae3bb7c\fu_dcd'. +Parameter \THREADS = 1 + +303.99. Executing AST frontend in derive mode using pre-parsed AST for module `\fu_mad'. +Parameter \THREADS = 1 +Generating RTLIL representation for module `$paramod\fu_mad\THREADS=s32'00000000000000000000000000000001'. +Parameter \fpr_pool = 64 +Parameter \fpr_pool_enc = 6 +Parameter \axu_spare_enc = 3 + +303.100. Executing AST frontend in derive mode using pre-parsed AST for module `\fu_fpr'. +Parameter \fpr_pool = 64 +Parameter \fpr_pool_enc = 6 +Parameter \axu_spare_enc = 3 +Generating RTLIL representation for module `$paramod$5bedeb075378eb26329c41fc0b388a3e5b70e296\fu_fpr'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 3 + +303.101. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 3 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 12 + +303.102. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 12 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001100'. +Parameter \WIDTH = 12 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001100'. +Parameter \WIDTH = 134 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.103. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 134 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$ab10c698f9199261049b5746ae6cead04bc27094\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.104. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$9d132bc191266c0c45acedbed9a847e4533828f6\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9d132bc191266c0c45acedbed9a847e4533828f6\tri_rlmreg_p'. +Parameter \WIDTH = 34 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.105. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 34 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$9e9febce8400b5aefc50d142ad7c476046cb5d14\tri_rlmreg_p'. +Parameter \WIDTH = 53 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.106. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 53 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$36aa71e1cb17d5d0aa5f1dda127adf976bf0dd66\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.107. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$d803e41f6e1527a5c1bdc98c766e9816d64bec06\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$d803e41f6e1527a5c1bdc98c766e9816d64bec06\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 + +303.108. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$f8ce279040df485fc256fcdb356d80795e0ee55d\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 + +303.109. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 4 + +303.110. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 4 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 73 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 + +303.111. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 73 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7d410ddf8e5d03ef21b961b475345ad1b8fda2bd\tri_rlmreg_p'. +Parameter \WIDTH = 65 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 + +303.112. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 65 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$11c8d685e24e21e0985b3c44cfbadc010f3ad337\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \IBUF = 1'1 + +303.113. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \IBUF = 1'1 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000011\IBUF=1'1'. +Parameter \WIDTH = 4 + +303.114. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000100'. +Parameter \THREADS = 2 + +303.115. Executing AST frontend in derive mode using pre-parsed AST for module `\fu_oscr'. +Parameter \THREADS = 2 +Generating RTLIL representation for module `$paramod\fu_oscr\THREADS=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 + +303.116. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$739721ac507a179deb44c4be36f911697f76c5bc\tri_rlmreg_p'. +Parameter \DBG_WIDTH = 32 + +303.117. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_debug_mux4'. +Parameter \DBG_WIDTH = 32 +Generating RTLIL representation for module `$paramod\tri_debug_mux4\DBG_WIDTH=s32'00000000000000000000000000100000'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 + +303.118. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 35 +Parameter \INIT = 0 + +303.119. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 35 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$2666e019b96a9ab4ba549a316649689b4cb2baa9\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \EVENTS_IN = 16 +Parameter \EVENTS_OUT = 4 + +303.120. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_event_mux1t'. +Parameter \EVENTS_IN = 16 +Parameter \EVENTS_OUT = 4 +Generating RTLIL representation for module `$paramod$4530470fed79629d5f3df6032d7f682052b511b6\tri_event_mux1t'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 65 +Parameter \INIT = 0 + +303.121. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 65 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$ecdabfd97873ac813472d39cbca64edc3be49b4f\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 + +303.122. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_ser_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 + +303.123. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$3ef9d3e055ac8a131a39b848dee8e704d4c1ccd8\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 + +303.124. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$d8319dfb252b4d3ad702e2c5adbd775d0686f2fd\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 + +303.125. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$580c91c0fff81d4df005362df7d3dadbd9433e6d\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 + +303.126. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 23 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8aed2b06a53bd806ef63ebe68f92da85a6fbe912\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_rlmreg_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 + +303.127. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$7f82fb572b34062a75f39ed522dd674a023773bd\tri_rlmreg_p'. +Parameter \WIDTH = 21 +Parameter \INIT = 0 + +303.128. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 21 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$5e97b12d8584e411e954401c107979088e363e72\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$7f82fb572b34062a75f39ed522dd674a023773bd\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 + +303.129. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$3689278a1e6b815ea49e2bd754f531a62fcae723\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 + +303.130. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 + +303.131. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$83c38f83a70f44efb2d8facd81e87723536de458\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 + +303.132. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 + +303.133. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 21 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$5e97b12d8584e411e954401c107979088e363e72\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$580c91c0fff81d4df005362df7d3dadbd9433e6d\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$83c38f83a70f44efb2d8facd81e87723536de458\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.134. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$988c1cccef7c15033463f1e6b6507051eecaab7e\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.135. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$10116eab85ef7af4e49dbd47ab4d1dbd5d1e2c00\tri_slat_scan'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 10 +Parameter \NEEDS_SRESET = 0 + +303.136. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 10 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$fa9fcf60f511bf0874dd45643a21493c34666e4f\tri_inv_nlats'. +Parameter \WIDTH = 110 +Parameter \NEEDS_SRESET = 0 + +303.137. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 110 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$941369425d8da2d21b9201fa4c2dd0ef77d22a88\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 + +303.138. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_inv_nlats'. +Parameter \WIDTH = 9 +Parameter \NEEDS_SRESET = 0 + +303.139. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$09531b493daf1b08f335a7f8a103f105d2997171\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \NEEDS_SRESET = 0 + +303.140. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$a54ab8e278a929c754b61067bade66c81e2283d5\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \NEEDS_SRESET = 0 + +303.141. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 15 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$f969a678abff986f3d39cd56e752088a7330e43a\tri_inv_nlats'. +Parameter \WIDTH = 25 +Parameter \NEEDS_SRESET = 0 + +303.142. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 25 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$1b26efe972e28cc9546687ae781a4b389c646811\tri_inv_nlats'. +Parameter \WIDTH = 68 +Parameter \NEEDS_SRESET = 0 + +303.143. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 68 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$69eb84ecca20bcd7ca74476fd52f8f599218bb4d\tri_inv_nlats'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 + +303.144. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 + +303.145. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 + +303.146. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_inv_nlats'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_inv_nlats'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_inv_nlats'. +Parameter \WIDTH = 55 +Parameter \NEEDS_SRESET = 0 + +303.147. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 55 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$91670ac8a4e63758eb54aa6f69d2b295fd7b3380\tri_inv_nlats'. +Parameter \WIDTH = 54 +Parameter \NEEDS_SRESET = 0 + +303.148. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 54 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$adf9d038cc72290d3dcef169d035e8b7971a288f\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_inv_nlats'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$dc51ee1c22d3854a177550990723aa69d95e564c\tri_rlmreg_p'. +Parameter \WIDTH = 8 + +303.149. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 5 + +303.150. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 5 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 5 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 25 + +303.151. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 25 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011001'. +Parameter \WIDTH = 25 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011001'. +Parameter \WIDTH = 34 + +303.152. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 34 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000100010'. +Parameter \WIDTH = 7 +Parameter \NEEDS_SRESET = 0 + +303.153. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$fd7e97932ff3025ad74229af7bdb68db2bc1160c\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$d803e41f6e1527a5c1bdc98c766e9816d64bec06\tri_rlmreg_p'. +Parameter \WIDTH = 66 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.154. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 66 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7a292b6f4e0c01bebd2a2dd37a08c16bd1a9579a\tri_rlmreg_p'. +Parameter \WIDTH = 163 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.155. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 163 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$d237f00d42d8393dad5517360659b05af70ea643\tri_rlmreg_p'. +Parameter \WIDTH = 96 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.156. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 96 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$b52cda713a8ae70d0c6b75e74260e6f2154f6531\tri_rlmreg_p'. +Parameter \WIDTH = 27 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.157. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 27 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bd0c231d1b02012669f3c2b738514adcdc60b2c7\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.158. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$6c7a2ec9cc6f50517039cb2d268cfa81903ee100\tri_rlmreg_p'. +Parameter \WIDTH = 57 + +303.159. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xor2'. +Parameter \WIDTH = 57 +Generating RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 57 +Found cached RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 56 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.160. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 56 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$8a54771090c53785798a3882abdc2d778ed0f8ab\tri_rlmreg_p'. +Parameter \WIDTH = 168 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.161. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 168 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$3d08ad750ae4835e7c7bf5ecfb691efe2460797e\tri_rlmreg_p'. +Parameter \WIDTH = 114 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.162. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 114 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$ec4b172bf4a54fd4ef8c0bbdbeb674f37c687663\tri_rlmreg_p'. +Parameter \WIDTH = 114 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$ec4b172bf4a54fd4ef8c0bbdbeb674f37c687663\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.163. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$8221002bede1e44d9df095fc966da9fa6f9d93bc\tri_rlmreg_p'. +Parameter \WIDTH = 114 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$ec4b172bf4a54fd4ef8c0bbdbeb674f37c687663\tri_rlmreg_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.164. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.165. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$b5bc5eec2225401e2c5955b79e05313daa736fef\tri_rlmreg_p'. +Parameter \WIDTH = 71 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.166. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 71 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$1d5de8534873b5f468a2a988cb3849a81dab4658\tri_rlmreg_p'. +Parameter \WIDTH = 71 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$1d5de8534873b5f468a2a988cb3849a81dab4658\tri_rlmreg_p'. +Parameter \WIDTH = 28 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.167. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 28 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$e22c8cb49c8f7f30220668e7cfc10400193b135c\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.168. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$54279aa8da8b466ff79ad1f35f3c4c178207b6e6\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.169. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$3a613ee6b8c10f2e32e0afa60592505972fd6a53\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.170. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$c3d2aa7ba9d5c468c28bb23261c978ec72f547ab\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$8221002bede1e44d9df095fc966da9fa6f9d93bc\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01011000010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 + +303.171. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01011000010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$e85aa75132150dad3a2e6affe746cad140c959ac\tri_xor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01011000010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 +Found cached RTLIL representation for module `$paramod$e85aa75132150dad3a2e6affe746cad140c959ac\tri_xor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01011000010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 +Found cached RTLIL representation for module `$paramod$e85aa75132150dad3a2e6affe746cad140c959ac\tri_xor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110110010011010101111101000001001110010101010001001000 + +303.172. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110110010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$27f3ae01cab76c8fcb5b68cd2b2cdb9219290c0a\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100000101001111010010010011001000110001010111110101100000110100010011010101111101000001001110010101010001001000 + +303.173. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi21'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100000101001111010010010011001000110001010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$4c5ef7afee0a6df87dd1b77590492b7d0eb4e2db\tri_aoi21'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110010010011010101111101000001001110010101010001001000 + +303.174. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110010010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$f764f543588b87a6155df205398bd64c944a7ddf\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111101000001010010010011001000110001010111110101100000110100010011010101111101000001001110010101010001001000 + +303.175. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_oai21'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111101000001010010010011001000110001010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$2ad124bbefdc4afac7f80b6760e84c88e9fc7806\tri_oai21'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111101000001010010010011001000110001010111110101100000110011010011010101111101000001001110010101010001001000 + +303.176. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_oai21'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111101000001010010010011001000110001010111110101100000110011010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$4a1a5ae6409555e38370bff2fceb5668ea04b50a\tri_oai21'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110110010011010101111101000001001110010101010001001000 +Found cached RTLIL representation for module `$paramod$27f3ae01cab76c8fcb5b68cd2b2cdb9219290c0a\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110100010011010101111101000001001110010101010001001000 + +303.177. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$d5ee8d3cba05b814ca2be8f2f52c4bbbee7d319b\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110010010011010101111101000001001110010101010001001000 + +303.178. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110010010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$8a7da16c8f0f9f7dc004cd7316a98161f2d65412\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110001010011010101111101000001001110010101010001001000 + +303.179. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110001010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$47348a0da0921c56d586d666e6c7f732a0b9640a\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110010010011010101111101000001001110010101010001001000 +Found cached RTLIL representation for module `$paramod$f764f543588b87a6155df205398bd64c944a7ddf\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 + +303.180. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$7f4a39689004c8cd43a6cbceb34aad62736d5645\tri_nor2'. +Parameter \WIDTH = 4 +Parameter \BTR = 104'01011000010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 + +303.181. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xor2'. +Parameter \WIDTH = 4 +Parameter \BTR = 104'01011000010011110101001000110010010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$6048c7629198e832a21ab3721ec46c158e106054\tri_xor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000111000010000010101111101000001001110010101010001001000 + +303.182. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000111000010000010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$77ee8adca347b3b36436c2a6281bcc7bb32032ca\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110011010111110101100000110110010011010101111101000001001110010101010001001000 + +303.183. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand3'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110011010111110101100000110110010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$ee0ffcd5dbe91f37c0289482265039bfcbff94bb\tri_nand3'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110100010000100101111101000001001110010101010001001000 + +303.184. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000110100010000100101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$da8337f7097f88eddbba3ebc3be99e4ed2bc0dc6\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000111000010000100101111101000001001110010101010001001000 + +303.185. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110010010111110101100000111000010000100101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$4f2e7b125724672dbdf82c9080f1f5079534d3d6\tri_nor2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110100010000010101111101000001001110010101010001001000 + +303.186. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110100010000010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$95abdd82a29a8ddcee49d5da1e461348e9207699\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110101010000100101111101000001001110010101010001001000 + +303.187. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110101010000100101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$df184cedd7fa62a421f4431ff6b7a20aca0a9ca1\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110011010011010101111101000001001110010101010001001000 + +303.188. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 96'010010010100111001010110010111110101100000110011010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$d90c61742e32c67c1d7d73a89ed982f9a5552fa5\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110011010111110101100000110100010011010101111101000001001110010101010001001000 + +303.189. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor3'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001110010011110101001000110011010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$8d8efc4b7cd0c8bcf674ee1e1a4061c0634de575\tri_nor3'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001001010011100101011001011111010110000011000100110001010011010101111101000001001110010101010001001000 + +303.190. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 104'01001001010011100101011001011111010110000011000100110001010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$557b4a7624713f422c0535c4448b4e7d03d46037\tri_inv'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110110010000010101111101000001001110010101010001001000 + +303.191. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110010010111110101100000110110010000010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$a5b43989651aa2ad885435c8a5eebee414df2cfe\tri_nand2'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110100010111110101100000110100010011010101111101000001001110010101010001001000 + +303.192. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand4'. +Parameter \WIDTH = 1 +Parameter \BTR = 112'0100111001000001010011100100010000110100010111110101100000110100010011010101111101000001001110010101010001001000 +Generating RTLIL representation for module `$paramod$82bfa3a10545af4efbfe54153b40d46f23680b6b\tri_nand4'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 + +303.193. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$fd7e97932ff3025ad74229af7bdb68db2bc1160c\tri_rlmreg_p'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 + +303.194. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_rlmreg_p'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \NEEDS_SRESET = 0 + +303.195. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2_nlats'. +Parameter \WIDTH = 3 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$f52e85c8bc2546556cdfc2fc6de1454c35a7a1d5\tri_nand2_nlats'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 + +303.196. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2_nlats'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_nand2_nlats'. +Parameter \WIDTH = 13 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$c3202b32ecdfce43590b109a7efb76e57b9bdb60\tri_nand2_nlats'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 + +303.197. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$d2d24642db673ca8abf121f467b6a0b88d3e3d66\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 80 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 + +303.198. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 80 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7b9698e450e6ded08f14453985d723434cf208a4\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$09531b493daf1b08f335a7f8a103f105d2997171\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$fd7e97932ff3025ad74229af7bdb68db2bc1160c\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \NEEDS_SRESET = 0 + +303.199. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$9de7f64219561e931a129cb0eef2ac724d911a60\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 0 + +303.200. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$e142e84eebaae3ceec9a7057745d1cfe064af707\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \NEEDS_SRESET = 0 + +303.201. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$1f8161a026df7a0232d29dfb421686087967730a\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$dc51ee1c22d3854a177550990723aa69d95e564c\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \NEEDS_SRESET = 0 + +303.202. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$101c2ec7be195dc31b9a15e05368487683c73e74\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$e142e84eebaae3ceec9a7057745d1cfe064af707\tri_rlmreg_p'. +Parameter \WIDTH = 33 +Parameter \NEEDS_SRESET = 0 + +303.203. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 33 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$e9e9ba0aece2fa61263b628c6ce6e7db320e8ede\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$e142e84eebaae3ceec9a7057745d1cfe064af707\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \NEEDS_SRESET = 0 + +303.204. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$5801f4b4eb8b1769b73cbb7574c5440f6e43700c\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 + +303.205. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2_nlats'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$d2d24642db673ca8abf121f467b6a0b88d3e3d66\tri_nand2_nlats'. +Parameter \WIDTH = 9 +Parameter \NEEDS_SRESET = 0 + +303.206. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 9 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$09531b493daf1b08f335a7f8a103f105d2997171\tri_inv_nlats'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 0 + +303.207. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 1 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$13ab58566572e0b02b7f3ff6d183d1fd2a2265c1\tri_inv_nlats'. +Parameter \WIDTH = 163 +Parameter \NEEDS_SRESET = 0 + +303.208. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 163 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$28415d9a4e55fefba35b6fd15a78c88ca4bee352\tri_inv_nlats'. +Parameter \WIDTH = 6 +Parameter \NEEDS_SRESET = 0 + +303.209. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$15e0c3e3a091c24df98f9d8ade378bc94cccffdf\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$09531b493daf1b08f335a7f8a103f105d2997171\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 109 +Parameter \NEEDS_SRESET = 0 + +303.210. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 109 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$1bedb4f63370efc652915b3072e923529fdce36c\tri_inv_nlats'. +Parameter \WIDTH = 110 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$941369425d8da2d21b9201fa4c2dd0ef77d22a88\tri_inv_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_inv_nlats'. +Parameter \WIDTH = 36 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 1 + +303.211. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 36 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$521ae53502a1b6149ea6198f1a98bc994210810a\tri_rlmreg_p'. +Parameter \WIDTH = 13 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 + +303.212. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 13 +Parameter \IBUF = 1'1 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$9912e156b477950bc863ee92b0bb548d830dc1e9\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$f52e85c8bc2546556cdfc2fc6de1454c35a7a1d5\tri_nand2_nlats'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 + +303.213. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2_nlats'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$dc51ee1c22d3854a177550990723aa69d95e564c\tri_nand2_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 + +303.214. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2_nlats'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_nand2_nlats'. +Parameter \WIDTH = 4 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$dc51ee1c22d3854a177550990723aa69d95e564c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \NEEDS_SRESET = 1 + +303.215. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$d64283da5f87def083ff58280a5ceb9876725d1b\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$9cfe836321654c18f3554ae91f21ea04ed33dd14\tri_rlmreg_p'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 + +303.216. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 53 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$107718f9a4bc1101ed73af3a9eee80205aff4622\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$d2d24642db673ca8abf121f467b6a0b88d3e3d66\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$4a5da33d7ac7584145887f75d1fc8623567b0937\tri_rlmreg_p'. +Parameter \WIDTH = 42 + +303.217. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 42 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000101010'. +Parameter \WIDTH = 38 + +303.218. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 38 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000100110'. +Parameter \WIDTH = 29 + +303.219. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 29 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011101'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 47 + +303.220. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 47 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000101111'. +Parameter \WIDTH = 34 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000100010'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 18 + +303.221. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000010010'. +Parameter \WIDTH = 57 + +303.222. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 57 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000111001'. +Parameter \WIDTH = 45 + +303.223. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 45 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000101101'. +Parameter \WIDTH = 21 + +303.224. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 21 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000010101'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 36 + +303.225. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 36 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000100100'. +Parameter \WIDTH = 640 + +303.226. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 640 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000001010000000'. +Parameter \WIDTH = 640 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000001010000000'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 36 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000100100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 28 + +303.227. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 28 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011100'. +Parameter \WIDTH = 28 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011100'. +Parameter \WIDTH = 36 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000100100'. +Parameter \WIDTH = 27 + +303.228. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 27 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011011'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 25 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011001'. +Parameter \WIDTH = 25 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011001'. +Parameter \WIDTH = 25 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011001'. +Parameter \WIDTH = 14 + +303.229. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000001110'. +Parameter \WIDTH = 20 + +303.230. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000010100'. +Parameter \WIDTH = 5 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 7 + +303.231. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 28 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000011100'. +Parameter \WIDTH = 80 +Parameter \NEEDS_SRESET = 0 + +303.232. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 80 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$14bbde4f2a8fa4933c9a848a2d2085a366a2aef7\tri_inv_nlats'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 + +303.233. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 16 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$d2d24642db673ca8abf121f467b6a0b88d3e3d66\tri_inv_nlats'. +Parameter \WIDTH = 15 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$f969a678abff986f3d39cd56e752088a7330e43a\tri_inv_nlats'. +Parameter \WIDTH = 20 +Parameter \NEEDS_SRESET = 0 + +303.234. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv_nlats'. +Parameter \WIDTH = 20 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$101c2ec7be195dc31b9a15e05368487683c73e74\tri_inv_nlats'. +Parameter \WIDTH = 6 + +303.235. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 43 +Parameter \INIT = 0 + +303.236. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 43 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$b76968876cfd136fbf0b634f0c67b7459b5ec9a6\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 43 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$b76968876cfd136fbf0b634f0c67b7459b5ec9a6\tri_rlmreg_p'. +Reprocessing module iuq_ifetch because instantiated module iuq_uc has become available. +Generating RTLIL representation for module `\iuq_ifetch'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 2 + +303.237. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 2 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 1 +Parameter \REGISTER_RENAME_DEPTH = 32 +Parameter \STORAGE_WIDTH = 5 + +303.238. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 1 +Parameter \REGISTER_RENAME_DEPTH = 32 +Parameter \STORAGE_WIDTH = 5 +Generating RTLIL representation for module `$paramod$0f965faa24c90815429696d3554e355650f6a704\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \ARCHITECTED_REGISTER_DEPTH = 36 +Parameter \REGISTER_RENAME_DEPTH = 64 +Parameter \STORAGE_WIDTH = 6 + +303.239. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 36 +Parameter \REGISTER_RENAME_DEPTH = 64 +Parameter \STORAGE_WIDTH = 6 +Generating RTLIL representation for module `$paramod$a31b2e7d1b2644a0d5eb98b2fb5b28bdbcba2be2\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \WIDTH = 6 +Parameter \INIT = 63 + +303.240. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 63 +Generating RTLIL representation for module `$paramod$1113e09aef599ede4d8999e4bd89fb08a818406d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 62 + +303.241. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 62 +Generating RTLIL representation for module `$paramod$3a932fc058ba713b30baf77096485ea89638ab0c\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 61 + +303.242. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 61 +Generating RTLIL representation for module `$paramod$f98695f13796fd091b5ca2ca9668ca9524b59c5e\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 60 + +303.243. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 60 +Generating RTLIL representation for module `$paramod$ca20dfaa17b76155c65fbc2b6b435a3f17d29ba8\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 59 + +303.244. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 59 +Generating RTLIL representation for module `$paramod$a7578155ce45e6c0cd7f6d5c5fb42724e46b80fa\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 58 + +303.245. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 58 +Generating RTLIL representation for module `$paramod$64347c810762a3f6c78369af542f690c44d989d6\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 57 + +303.246. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 57 +Generating RTLIL representation for module `$paramod$534e2b025d8e4897d477c6883764b1700bd566f9\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 56 + +303.247. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 56 +Generating RTLIL representation for module `$paramod$5470d4015c968972919da9305a05485164395561\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 55 + +303.248. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 55 +Generating RTLIL representation for module `$paramod$b2e3cf1004d84234e6fd0f8840a1c8600a3e6a66\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 54 + +303.249. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 54 +Generating RTLIL representation for module `$paramod$f01500254a1468263fb2627c1efa76cd47800691\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 53 + +303.250. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 53 +Generating RTLIL representation for module `$paramod$38fbb0c6ec7b4a934ddba6b981bac4d4ccf77e57\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 52 + +303.251. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 52 +Generating RTLIL representation for module `$paramod$a4515d1f727eaa009e3a4dd200caa05c838c57db\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 51 + +303.252. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 51 +Generating RTLIL representation for module `$paramod$0d1443350fa83a6d73fdfaeb41454e7033c4703c\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 50 + +303.253. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 50 +Generating RTLIL representation for module `$paramod$bb500b9fb6ddb9814f043ed479300c72351f2609\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 49 + +303.254. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 49 +Generating RTLIL representation for module `$paramod$fca04d5aa67e8b9e4d28bfc24515df7167dad108\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 48 + +303.255. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 48 +Generating RTLIL representation for module `$paramod$b62e85cba3b16d764bacefc4f526f74f64c142b6\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 47 + +303.256. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 47 +Generating RTLIL representation for module `$paramod$7b57297d8596cd82d13b123c9c780221d21df7e5\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 46 + +303.257. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 46 +Generating RTLIL representation for module `$paramod$d6ce12fec8a268f6b1ebef2047f29e768fc21d76\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 45 + +303.258. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 45 +Generating RTLIL representation for module `$paramod$537ac436eac5af61e075e0c7c3f2936b5a9e6d4d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 44 + +303.259. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 44 +Generating RTLIL representation for module `$paramod$68e2b8f109c3c09ad3e5a61aaf8c43107fb24db2\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 43 + +303.260. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 43 +Generating RTLIL representation for module `$paramod$bcf7658964dd12b2555bf0ff4d4c1b1f3359457e\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 42 + +303.261. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 42 +Generating RTLIL representation for module `$paramod$28eff6741763ba652236f757d9131d445c0487eb\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 41 + +303.262. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 41 +Generating RTLIL representation for module `$paramod$cade5a16c52c0fc7025d1c2bb52ee61365971dfe\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 40 + +303.263. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 40 +Generating RTLIL representation for module `$paramod$210ab89a94300b36fdea6ce2343fa7ebd9daee59\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 39 + +303.264. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 39 +Generating RTLIL representation for module `$paramod$80e0959daa160b23ad6ec2a8709b65f4c7e838b8\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 38 + +303.265. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 38 +Generating RTLIL representation for module `$paramod$30c4a41318f3310b2f4d5922ab44facb810207f8\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 37 + +303.266. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 37 +Generating RTLIL representation for module `$paramod$d5786892fed2d94fb6e1d1476e7d44f02528d2f9\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 36 + +303.267. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 36 +Generating RTLIL representation for module `$paramod$0fbda4b625773bc9530b08ac953bb99014a2eb51\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 35 + +303.268. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 35 +Generating RTLIL representation for module `$paramod$485890755efc7e87c5337ef633c9ab4896f6d76d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 35 + +303.269. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 35 +Generating RTLIL representation for module `$paramod$95caaae7f1bc1371fdf07b8dc3aa3eaa132fae1b\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 34 + +303.270. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 34 +Generating RTLIL representation for module `$paramod$e80cad5cfc5b2bc01da3c0cb04dc7bf6a4b9f865\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 34 + +303.271. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 34 +Generating RTLIL representation for module `$paramod$9a2958a93e0d8a8d74ee8ec79481ebf0676c9a41\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 33 + +303.272. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 33 +Generating RTLIL representation for module `$paramod$97c7f340dae91c9fdd183e829d07adc201d51670\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 33 + +303.273. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 33 +Generating RTLIL representation for module `$paramod$5fc67b01dea30821d7be519f427213d0a920ef70\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 32 + +303.274. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 32 +Generating RTLIL representation for module `$paramod$75f6ac5c1a4702c6351da2cc49c81c0bbc474076\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 32 + +303.275. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 32 +Generating RTLIL representation for module `$paramod$6bc66b2e6b2e17a15e8101c411e128f6c1aae316\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 31 + +303.276. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 31 +Generating RTLIL representation for module `$paramod$228b673815df58603a2210c7d03da1d6d346baf5\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 31 + +303.277. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 31 +Generating RTLIL representation for module `$paramod$1ccd517ee57d82b1447fb1823236da90b73e5974\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 30 + +303.278. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 30 +Generating RTLIL representation for module `$paramod$b41a16d4af0f91de84bc291d36f6dae70a33e7e5\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 30 + +303.279. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 30 +Generating RTLIL representation for module `$paramod$303664eaa9944e30461aa0eff65a217ecf918c8a\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 29 + +303.280. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 29 +Generating RTLIL representation for module `$paramod$d4f29724b5c5be8b66e3757d12d1a3993aab8d26\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 29 + +303.281. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 29 +Generating RTLIL representation for module `$paramod$24fc9336650e35e388c27cce874c5c7c77ccfe4e\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 28 + +303.282. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 28 +Generating RTLIL representation for module `$paramod$792ff4205c70f825245d49b7bf862ece964ad877\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 28 + +303.283. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 28 +Generating RTLIL representation for module `$paramod$e7e89f6df79cb408e3f5f8d535b97fa3cb3ac1c3\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 27 + +303.284. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 27 +Generating RTLIL representation for module `$paramod$dfb596dcd8cec334bd13f8df834bf747cbcdc038\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 27 + +303.285. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 27 +Generating RTLIL representation for module `$paramod$2989aa9295e063576facca2b52d9b114a029ffac\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 26 + +303.286. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 26 +Generating RTLIL representation for module `$paramod$77eec30e16242f0a821be28f198cc720724a9fd2\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 26 + +303.287. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 26 +Generating RTLIL representation for module `$paramod$2f9cbd13b59cbaec2373b5daeb49bf9b02498631\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 25 + +303.288. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 25 +Generating RTLIL representation for module `$paramod$cd7abd51c5033faa6cba18dbfc9ccd99c51c13b5\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 25 + +303.289. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 25 +Generating RTLIL representation for module `$paramod$411dfb3d6d917562ef59519d9d07b188721fc8e0\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 24 + +303.290. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 24 +Generating RTLIL representation for module `$paramod$838ce5e465ca2decfaf4fe0dd86161b3c1cef8e6\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 24 + +303.291. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 24 +Generating RTLIL representation for module `$paramod$9ae805f5b665b27108caefe60551012d86671554\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 23 + +303.292. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 23 +Generating RTLIL representation for module `$paramod$434c7c4bfa22be356f1d59d2647cff28823b5798\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 23 + +303.293. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 23 +Generating RTLIL representation for module `$paramod$d64e9b0aa4bad81fef28e739af0acb3a5c42aae9\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 22 + +303.294. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 22 +Generating RTLIL representation for module `$paramod$e6ff36d661d34d96e9e8261ac7b51918001e9db9\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 22 + +303.295. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 22 +Generating RTLIL representation for module `$paramod$b366964be93f8048447f495750622303865668a4\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 21 + +303.296. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 21 +Generating RTLIL representation for module `$paramod$0613e94663060a38a1f6706df0e6e8357f328cfe\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 21 + +303.297. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 21 +Generating RTLIL representation for module `$paramod$bc0b4db2ff7f4a2bf0214b81577d9caa8976d4aa\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 20 + +303.298. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 20 +Generating RTLIL representation for module `$paramod$87b800ecd81e369023c70f5007d53e12ed052abd\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 20 + +303.299. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 20 +Generating RTLIL representation for module `$paramod$84ececaf4bd7a98b4f719fe82f70be8d37c22623\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 19 + +303.300. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 19 +Generating RTLIL representation for module `$paramod$a61e3cda02a7ca27e84d496e45ef9419288bdb09\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 19 + +303.301. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 19 +Generating RTLIL representation for module `$paramod$2864e8e7ebd01939fb48fdae605df4497e28f624\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 18 + +303.302. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 18 +Generating RTLIL representation for module `$paramod$c70071c320e503b682e9c483339a34b0c2260f79\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 18 + +303.303. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 18 +Generating RTLIL representation for module `$paramod$3b3be9c93024e6b13673409b02deef7ef5c75a56\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 17 + +303.304. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 17 +Generating RTLIL representation for module `$paramod$075f66b65d0e3e02aa6de6ce5512347d38e85416\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 17 + +303.305. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 17 +Generating RTLIL representation for module `$paramod$a5d1cf144f5702038c8bf9696ddee3e3af6fc8f2\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 16 + +303.306. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 16 +Generating RTLIL representation for module `$paramod$c1f1f63ed25e37e985870ff561a3e944e5947ca1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 16 + +303.307. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 16 +Generating RTLIL representation for module `$paramod$b967efc5dd0129342807801652d15f609342bbaf\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 15 + +303.308. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 15 +Generating RTLIL representation for module `$paramod$b978584df9507ea4fe2c927690ba352df672fc80\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 15 + +303.309. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 15 +Generating RTLIL representation for module `$paramod$e258063f80707c220c3c42ce2d272bfa339545e2\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 14 + +303.310. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 14 +Generating RTLIL representation for module `$paramod$20e27184d6d6763ea0dd733ed0eab39afc75f655\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 14 + +303.311. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 14 +Generating RTLIL representation for module `$paramod$58ed63299c66ea78491c142ae59a8fb67f86e2be\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 13 + +303.312. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 13 +Generating RTLIL representation for module `$paramod$f435813a988d4598901477963e42f7f4349b821d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 13 + +303.313. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 13 +Generating RTLIL representation for module `$paramod$bb934a5a0a1954354b052c35e634d34ad64bb5d8\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 12 + +303.314. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 12 +Generating RTLIL representation for module `$paramod$394534393110e30496efd80870d1f70c258b5184\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 12 + +303.315. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 12 +Generating RTLIL representation for module `$paramod$f9158d8073e14382c80fec64407f9bde639f1ed3\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 11 + +303.316. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 11 +Generating RTLIL representation for module `$paramod$5be4aa3ae0ad6da744ec5d08a61330d857424706\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 11 + +303.317. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 11 +Generating RTLIL representation for module `$paramod$79cd2de0df36719768ff3fc263b6b60d41642728\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 10 + +303.318. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 10 +Generating RTLIL representation for module `$paramod$1fe595a961c419507d0c06a2b16bc14b24bb2b5d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 10 + +303.319. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 10 +Generating RTLIL representation for module `$paramod$4908abaa6f0b54fb3d3eab614f5fd48321258257\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 9 + +303.320. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 9 +Generating RTLIL representation for module `$paramod$ce4da550b322d8957edd7c46b66b04626ee0bf4a\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 9 + +303.321. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 9 +Generating RTLIL representation for module `$paramod$5c93786560071d3d602fce15bd947031b60fb70e\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 8 + +303.322. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 8 +Generating RTLIL representation for module `$paramod$ff27f1bfd7fea6c3e37fee6d10eead897f8750b7\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 8 + +303.323. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 8 +Generating RTLIL representation for module `$paramod$18786743b43750c0a5d9bf7ac855ed015353c466\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 7 + +303.324. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 7 +Generating RTLIL representation for module `$paramod$d164c706f586b43c350775036489c8bfa4bc7210\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 7 + +303.325. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 7 +Generating RTLIL representation for module `$paramod$e230e1002a90eb5ced74226662a506cc3bd03e54\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 6 + +303.326. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 6 +Generating RTLIL representation for module `$paramod$7ac87facb4917359375b9f0ce5b699748f0eead7\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 6 + +303.327. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 6 +Generating RTLIL representation for module `$paramod$e5569d9780d4e47a0f9163d53dc2e5b513eba66d\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 5 + +303.328. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 5 +Generating RTLIL representation for module `$paramod$7ca7c0bee433a03f684bd72754a0542da265fe79\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 5 + +303.329. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 5 +Generating RTLIL representation for module `$paramod$6872a9bf99666627bec17b9af257f9e18ac7c203\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 4 + +303.330. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 4 +Generating RTLIL representation for module `$paramod$54ea4787829feeb426e5ded0bcc03410e086d6eb\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 4 + +303.331. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 4 +Generating RTLIL representation for module `$paramod$afade4774219dd65deb7b0f57554b9a75b1e2dbb\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 3 + +303.332. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 3 +Generating RTLIL representation for module `$paramod$36edf14deb0867a1b92be95e2b3f7edd5bc5bc38\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 3 + +303.333. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 3 +Generating RTLIL representation for module `$paramod$bc15c42c833e46b5295b9dccc67d1b46b048ee6d\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 2 + +303.334. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 2 +Generating RTLIL representation for module `$paramod$7f3ca248027c45ac4539394fb8f1133e66d4a0fc\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 2 + +303.335. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 2 +Generating RTLIL representation for module `$paramod$b0255abb3600d3c98900bccd88ac6da48ce500ca\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 1 + +303.336. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 1 +Generating RTLIL representation for module `$paramod$a727ef1349d6bead0d3d171948c16ff9ddb189f9\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 1 + +303.337. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 1 +Generating RTLIL representation for module `$paramod$4345abbd1bbe487f4d161e60d17a59b6f2a1d872\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 35 +Found cached RTLIL representation for module `$paramod$95caaae7f1bc1371fdf07b8dc3aa3eaa132fae1b\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 34 +Found cached RTLIL representation for module `$paramod$9a2958a93e0d8a8d74ee8ec79481ebf0676c9a41\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 33 +Found cached RTLIL representation for module `$paramod$5fc67b01dea30821d7be519f427213d0a920ef70\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 32 +Found cached RTLIL representation for module `$paramod$6bc66b2e6b2e17a15e8101c411e128f6c1aae316\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 31 +Found cached RTLIL representation for module `$paramod$1ccd517ee57d82b1447fb1823236da90b73e5974\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 30 +Found cached RTLIL representation for module `$paramod$303664eaa9944e30461aa0eff65a217ecf918c8a\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 29 +Found cached RTLIL representation for module `$paramod$24fc9336650e35e388c27cce874c5c7c77ccfe4e\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 28 +Found cached RTLIL representation for module `$paramod$e7e89f6df79cb408e3f5f8d535b97fa3cb3ac1c3\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 27 +Found cached RTLIL representation for module `$paramod$2989aa9295e063576facca2b52d9b114a029ffac\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 26 +Found cached RTLIL representation for module `$paramod$2f9cbd13b59cbaec2373b5daeb49bf9b02498631\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 25 +Found cached RTLIL representation for module `$paramod$411dfb3d6d917562ef59519d9d07b188721fc8e0\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 24 +Found cached RTLIL representation for module `$paramod$9ae805f5b665b27108caefe60551012d86671554\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 23 +Found cached RTLIL representation for module `$paramod$d64e9b0aa4bad81fef28e739af0acb3a5c42aae9\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 22 +Found cached RTLIL representation for module `$paramod$b366964be93f8048447f495750622303865668a4\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 21 +Found cached RTLIL representation for module `$paramod$bc0b4db2ff7f4a2bf0214b81577d9caa8976d4aa\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 20 +Found cached RTLIL representation for module `$paramod$84ececaf4bd7a98b4f719fe82f70be8d37c22623\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 19 +Found cached RTLIL representation for module `$paramod$2864e8e7ebd01939fb48fdae605df4497e28f624\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 18 +Found cached RTLIL representation for module `$paramod$3b3be9c93024e6b13673409b02deef7ef5c75a56\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 17 +Found cached RTLIL representation for module `$paramod$a5d1cf144f5702038c8bf9696ddee3e3af6fc8f2\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 16 +Found cached RTLIL representation for module `$paramod$b967efc5dd0129342807801652d15f609342bbaf\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 15 +Found cached RTLIL representation for module `$paramod$e258063f80707c220c3c42ce2d272bfa339545e2\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 14 +Found cached RTLIL representation for module `$paramod$58ed63299c66ea78491c142ae59a8fb67f86e2be\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 13 +Found cached RTLIL representation for module `$paramod$bb934a5a0a1954354b052c35e634d34ad64bb5d8\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 12 +Found cached RTLIL representation for module `$paramod$f9158d8073e14382c80fec64407f9bde639f1ed3\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 11 +Found cached RTLIL representation for module `$paramod$79cd2de0df36719768ff3fc263b6b60d41642728\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 10 +Found cached RTLIL representation for module `$paramod$4908abaa6f0b54fb3d3eab614f5fd48321258257\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 9 +Found cached RTLIL representation for module `$paramod$5c93786560071d3d602fce15bd947031b60fb70e\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 8 +Found cached RTLIL representation for module `$paramod$18786743b43750c0a5d9bf7ac855ed015353c466\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 7 +Found cached RTLIL representation for module `$paramod$e230e1002a90eb5ced74226662a506cc3bd03e54\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 6 +Found cached RTLIL representation for module `$paramod$e5569d9780d4e47a0f9163d53dc2e5b513eba66d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 5 +Found cached RTLIL representation for module `$paramod$6872a9bf99666627bec17b9af257f9e18ac7c203\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 4 +Found cached RTLIL representation for module `$paramod$afade4774219dd65deb7b0f57554b9a75b1e2dbb\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 3 +Found cached RTLIL representation for module `$paramod$bc15c42c833e46b5295b9dccc67d1b46b048ee6d\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 2 +Found cached RTLIL representation for module `$paramod$b0255abb3600d3c98900bccd88ac6da48ce500ca\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 1 +Found cached RTLIL representation for module `$paramod$4345abbd1bbe487f4d161e60d17a59b6f2a1d872\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 28 +Found cached RTLIL representation for module `$paramod$e7e89f6df79cb408e3f5f8d535b97fa3cb3ac1c3\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \SIZE = 6 +Parameter \WRAP = 27 + +303.338. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map_inc'. +Parameter \SIZE = 6 +Parameter \WRAP = 27 +Generating RTLIL representation for module `$paramod$b65c0bf1195b385da8a47f7a208f11e5131fdb86\iuq_rn_map_inc'. +Parameter \SIZE = 6 +Parameter \WRAP = 27 +Found cached RTLIL representation for module `$paramod$b65c0bf1195b385da8a47f7a208f11e5131fdb86\iuq_rn_map_inc'. +Reprocessing module iuq_rn_map because instantiated module $paramod$1113e09aef599ede4d8999e4bd89fb08a818406d\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 + +303.339. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 128 + +303.340. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 128 +Generating RTLIL representation for module `$paramod$8b211c131b8d8dc15a710f668960d6ca40692267\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 + +303.341. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$94167d423b055590434bd98cbc7ca883a48a9e47\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 128 +Found cached RTLIL representation for module `$paramod$8b211c131b8d8dc15a710f668960d6ca40692267\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 61 +Parameter \INIT = 0 + +303.342. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 61 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$163fa971fb479095ddadc0469c401fe91f6f12fc\tri_rlmreg_p'. +Parameter \WIDTH = 61 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$163fa971fb479095ddadc0469c401fe91f6f12fc\tri_rlmreg_p'. +Parameter \WIDTH = 61 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$163fa971fb479095ddadc0469c401fe91f6f12fc\tri_rlmreg_p'. +Parameter \WIDTH = 61 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$163fa971fb479095ddadc0469c401fe91f6f12fc\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 + +303.343. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$94167d423b055590434bd98cbc7ca883a48a9e47\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \ADDRESSABLE_PORTS = 64 +Parameter \ADDRESSBUS_WIDTH = 6 +Parameter \PORT_BITWIDTH = 143 +Parameter \LATCHED_READ = 1'1 +Parameter \LATCHED_READ_DATA = 1'1 +Parameter \LATCHED_WRITE = 1'1 + +303.344. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_iuq_cpl_arr'. +Parameter \ADDRESSABLE_PORTS = 64 +Parameter \ADDRESSBUS_WIDTH = 6 +Parameter \PORT_BITWIDTH = 143 +Parameter \LATCHED_READ = 1'1 +Parameter \LATCHED_READ_DATA = 1'1 +Parameter \LATCHED_WRITE = 1'1 +Generating RTLIL representation for module `$paramod$4ff189b92e8676c02570ccfc5e3a837386806ee6\tri_iuq_cpl_arr'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.345. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.346. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.347. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.348. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.349. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$988c1cccef7c15033463f1e6b6507051eecaab7e\tri_rlmreg_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.350. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$a843b3cf7cfb867eed17aefd5180985fd47950aa\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.351. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$1a121129d066a3a15e306affd2df760e4252f570\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1a121129d066a3a15e306affd2df760e4252f570\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ed35a67a3a94884fd77d0ef93a0c3ffa9a4f5c19\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.352. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$66da01a3adba30ef0f752975215c89fae1afeea8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.353. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$5eba8a9409c770cbf68c71fa1f88c9d9442f1f86\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.354. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$ee6ab1e637f216030d17b24b5df851e6a31bbbe2\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.355. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bf032fe91afd2717960ccb2f5628756fde2af36d\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5eba8a9409c770cbf68c71fa1f88c9d9442f1f86\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 31 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.356. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 31 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$991fc95d6f5308ae81783b9b6d256dd6efbca1e4\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.357. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$d56c69aa3ef56e22a64f13595e5bd685d591b43a\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.358. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$f61b692a046330b5c38e3c59524fe79173d9b087\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \EVENTS_IN = 16 +Parameter \EVENTS_OUT = 4 +Found cached RTLIL representation for module `$paramod$4530470fed79629d5f3df6032d7f682052b511b6\tri_event_mux1t'. +Parameter \SIZE = 7 +Parameter \WRAP = 31 + +303.359. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_cpl_itag'. +Parameter \SIZE = 7 +Parameter \WRAP = 31 +Generating RTLIL representation for module `$paramod$95b64968687f119e354d345aa72b7eb5f018a2fc\iuq_cpl_itag'. +Parameter \SIZE = 7 +Parameter \WRAP = 31 +Found cached RTLIL representation for module `$paramod$95b64968687f119e354d345aa72b7eb5f018a2fc\iuq_cpl_itag'. +Parameter \SIZE = 7 + +303.360. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_agecmp'. +Parameter \SIZE = 7 +Generating RTLIL representation for module `$paramod\tri_agecmp\SIZE=s32'00000000000000000000000000000111'. +Parameter \SIZE = 7 +Found cached RTLIL representation for module `$paramod\tri_agecmp\SIZE=s32'00000000000000000000000000000111'. +Parameter \SIZE = 7 +Found cached RTLIL representation for module `$paramod\tri_agecmp\SIZE=s32'00000000000000000000000000000111'. +Parameter \SIZE = 7 +Found cached RTLIL representation for module `$paramod\tri_agecmp\SIZE=s32'00000000000000000000000000000111'. +Parameter \SIZE = 7 +Found cached RTLIL representation for module `$paramod\tri_agecmp\SIZE=s32'00000000000000000000000000000111'. +Parameter \SIZE = 7 +Found cached RTLIL representation for module `$paramod\tri_agecmp\SIZE=s32'00000000000000000000000000000111'. +Reprocessing module iuq_cpl_ctrl because instantiated module $paramod$1104711058ec2c005227e917698bcb0e62b60e2d\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_cpl_ctrl'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 + +303.361. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$fc46983bfa0f2d294b902322957eac56fa5325fb\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 6 + +303.362. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 6 +Generating RTLIL representation for module `$paramod$d3d57cdac4faefb276e4a62bc16ef3ce1b6b465d\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 6 +Found cached RTLIL representation for module `$paramod$d3d57cdac4faefb276e4a62bc16ef3ce1b6b465d\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 8 + +303.363. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 8 +Generating RTLIL representation for module `$paramod$77d55efba97ddc2d5fcd84ceb4528cbc8d2716a1\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 6 +Found cached RTLIL representation for module `$paramod$d3d57cdac4faefb276e4a62bc16ef3ce1b6b465d\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 6 +Found cached RTLIL representation for module `$paramod$d3d57cdac4faefb276e4a62bc16ef3ce1b6b465d\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 32'11111111111111111111111111111110 + +303.364. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 32'11111111111111111111111111111110 +Generating RTLIL representation for module `$paramod$496670812fb5fbf3d2b5e59a7897cb079846ffbf\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 10 + +303.365. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 10 +Generating RTLIL representation for module `$paramod$eedd54ce52d385dfedf9e8aa4bbce57b07f68685\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 10 +Found cached RTLIL representation for module `$paramod$eedd54ce52d385dfedf9e8aa4bbce57b07f68685\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 14 + +303.366. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 14 +Generating RTLIL representation for module `$paramod$fe15e9f7999a79b456e3a21ad59d758e2a50bc97\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 10 +Found cached RTLIL representation for module `$paramod$eedd54ce52d385dfedf9e8aa4bbce57b07f68685\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 10 +Found cached RTLIL representation for module `$paramod$eedd54ce52d385dfedf9e8aa4bbce57b07f68685\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 1 + +303.367. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 1 +Generating RTLIL representation for module `$paramod$0e078873fe7f07336b14c85dfaa6a5269317296b\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 12 + +303.368. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 12 +Generating RTLIL representation for module `$paramod$9df38b308ef1c3f573501069223f2372f3fa1328\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 12 +Found cached RTLIL representation for module `$paramod$9df38b308ef1c3f573501069223f2372f3fa1328\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 16 + +303.369. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 16 +Generating RTLIL representation for module `$paramod$70fe1f24c2d73359a566cb290b8e55cb102181dd\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 12 +Found cached RTLIL representation for module `$paramod$9df38b308ef1c3f573501069223f2372f3fa1328\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 12 +Found cached RTLIL representation for module `$paramod$9df38b308ef1c3f573501069223f2372f3fa1328\tri_rlmreg_p'. +Reprocessing module iuq_dispatch because instantiated module $paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_dispatch'. +Warning: Replacing memory \fu1_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2289 +Warning: Replacing memory \fu1_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2288 +Warning: Replacing memory \fu0_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2257 +Warning: Replacing memory \fu0_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2256 +Warning: Replacing memory \sq_cmdq_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2225 +Warning: Replacing memory \sq_cmdq_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2224 +Warning: Replacing memory \lq_cmdq_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2193 +Warning: Replacing memory \lq_cmdq_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2192 +Warning: Replacing memory \fx1_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2160 +Warning: Replacing memory \fx1_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2159 +Warning: Replacing memory \fx0_med_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2128 +Warning: Replacing memory \fx0_high_credit_cnt_d with list of registers. See ../verilog/work/iuq_dispatch.v:2127 +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 + +303.370. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$5ed935c594a78e1b6d14d059a0f539c82e16612a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$5ed935c594a78e1b6d14d059a0f539c82e16612a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 110 +Parameter \INIT = 0 + +303.371. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 110 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$c5aa563511e7c9e763e9cfaa7317ba95a92cee28\tri_rlmreg_p'. +Parameter \WIDTH = 110 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c5aa563511e7c9e763e9cfaa7317ba95a92cee28\tri_rlmreg_p'. +Parameter \WIDTH = 1760 +Parameter \INIT = 0 + +303.372. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 1760 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$6e7e0b9fb718827278def02cf3367cf7fab91233\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 1 + +303.373. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 1 +Generating RTLIL representation for module `$paramod$e395152872a40a9c4f6b53cea8919c2375af9c7c\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 1 +Found cached RTLIL representation for module `$paramod$e395152872a40a9c4f6b53cea8919c2375af9c7c\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 11 + +303.374. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 11 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001011'. +Parameter \WIDTH = 11 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001011'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \EVENTS_IN = 64 +Parameter \EVENTS_OUT = 4 + +303.375. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_event_mux1t'. +Parameter \EVENTS_IN = 64 +Parameter \EVENTS_OUT = 4 +Generating RTLIL representation for module `$paramod$74f654efe1505fbb5c8e656eb3c8f20a4c51d543\tri_event_mux1t'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.376. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.377. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$5e65f5ca7cb793b8b03c1d7b93a788374a1650a6\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.378. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$db6257b43e9a2c8ab6a9f6c9317dce0a4a651405\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 15 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.379. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 15 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$c9f9022ef8163f29cc302b8f31367f1065338ec9\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.380. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$47d429b688788098bc6d68dab0f2bec550ef6d04\tri_slat_scan'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 + +303.381. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Generating RTLIL representation for module `$paramod$e092d5125e05a02f5483345591e893023dcb8651\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 15 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$c9f9022ef8163f29cc302b8f31367f1065338ec9\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$47d429b688788098bc6d68dab0f2bec550ef6d04\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a843b3cf7cfb867eed17aefd5180985fd47950aa\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.382. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$cb1feb5bdcccca22afbc2410c098ee780ec04072\tri_rlmreg_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.383. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$2bb9ea0e9bcb5abf3d4e792545fcaa2b2b25d71f\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 26 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.384. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 26 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$fcfa54a2fb55c33e0d6dbd1ffea3cd16426e12d2\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.385. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$55bc0ed1c929d1cb038f281af486ed8bafc0f1ed\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$988c1cccef7c15033463f1e6b6507051eecaab7e\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 13 +Parameter \NEEDS_SRESET = 1 + +303.386. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 13 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$29ef704d2fc381b3d4b1d6ba6cb4a8dd0d029ffb\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.387. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.388. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$6cb6d74810fe940ebb6f800501ad76dfc8e1ed8a\tri_rlmreg_p'. +Parameter \WIDTH = 84 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.389. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 84 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$d1724e8c6033ac657bfdaf6991f81a11e51e7e64\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$6cb6d74810fe940ebb6f800501ad76dfc8e1ed8a\tri_rlmreg_p'. +Parameter \WIDTH = 84 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$d1724e8c6033ac657bfdaf6991f81a11e51e7e64\tri_rlmreg_p'. +Parameter \WIDTH = 15 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$988c1cccef7c15033463f1e6b6507051eecaab7e\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.390. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$d56c69aa3ef56e22a64f13595e5bd685d591b43a\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 + +303.391. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_direct_err_rpt'. +Parameter \WIDTH = 1 +Generating RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Reprocessing module iuq_ic_ierat because instantiated module $paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_ic_ierat'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 + +303.392. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$a7148e5d92b9abd61e5e63d4577b5c3c8b15ae85\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 + +303.393. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$31fe6d6fb21b54cd707461aac373e440f89bedfa\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a7148e5d92b9abd61e5e63d4577b5c3c8b15ae85\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.394. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7a9283cd54c63739b290315339eae36c34cb752d\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$31fe6d6fb21b54cd707461aac373e440f89bedfa\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Reprocessing module iuq_ic_select because instantiated module $paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_ic_select'. +Warning: Replacing memory \iu0_ifar_temp with list of registers. See ../verilog/work/iuq_ic_select.v:712 +Warning: Replacing memory \iu0_sent_d with list of registers. See ../verilog/work/iuq_ic_select.v:619 +Warning: Replacing memory \sent_proc.any_sent with list of registers. See ../verilog/work/iuq_ic_select.v:612, ../verilog/work/iuq_ic_select.v:609 +Warning: Replacing memory \shift2_sent with list of registers. See ../verilog/work/iuq_ic_select.v:607, ../verilog/work/iuq_ic_select.v:606 +Warning: Replacing memory \shift1_sent with list of registers. See ../verilog/work/iuq_ic_select.v:603, ../verilog/work/iuq_ic_select.v:602 +Warning: Replacing memory \next_fetch with list of registers. See ../verilog/work/iuq_ic_select.v:602, ../verilog/work/iuq_ic_select.v:588 +Warning: Replacing memory \need_fetch with list of registers. See ../verilog/work/iuq_ic_select.v:588, ../verilog/work/iuq_ic_select.v:586 +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$83c38f83a70f44efb2d8facd81e87723536de458\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 41 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.395. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 41 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7ac90a9227a17326350c2460fa887ec026502b93\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7a9283cd54c63739b290315339eae36c34cb752d\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.396. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$60c2a32b651165e48eac1fb41959cb328d7e0cae\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.397. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$daa769ddf4a9d1b1d53bb110f7d98564abae8ece\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.398. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$7f547f9b0e2fc4232d72f54553e5d1eece74e894\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b5bc5eec2225401e2c5955b79e05313daa736fef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.399. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$bbc8661c84175bca875d3b022b21057190bf06d6\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Reprocessing module iuq_ic_dir because instantiated module $paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_ic_dir'. +Warning: Replacing memory \dir_lru_write with list of registers. See ../verilog/work/iuq_ic_dir.v:1129 +Warning: Replacing memory \dir_lru_read with list of registers. See ../verilog/work/iuq_ic_dir.v:1128 +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 40 +Parameter \INIT = 0 + +303.400. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 40 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$737ad8cbfbf3dbdfc7b0f84b870d44ce34e243ea\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 40 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$737ad8cbfbf3dbdfc7b0f84b870d44ce34e243ea\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 6'100000 + +303.401. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 6'100000 +Generating RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000110\INIT=6'100000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 6'100000 +Found cached RTLIL representation for module `$paramod\tri_rlmreg_p\WIDTH=s32'00000000000000000000000000000110\INIT=6'100000'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \WIDTH = 38 +Parameter \INIT = 0 + +303.402. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 38 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$12ff0b52d99c8a7c77eabf63210cb13e49a4eb11\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$94167d423b055590434bd98cbc7ca883a48a9e47\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$4cfd30ab2764971adf606fc14bd0a9f5ee973dd9\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Reprocessing module iuq_ic_miss because instantiated module $paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_ic_miss'. +Parameter \WIDTH = 32 +Parameter \INIT = 393232 + +303.403. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 393232 +Generating RTLIL representation for module `$paramod$f59a557fe17ab7a2569e7b7c7180bfd5caf98588\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 101058566 + +303.404. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 101058566 +Generating RTLIL representation for module `$paramod$5a185d355abdc45d0278935423d6aa42336aa697\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 655392 + +303.405. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 655392 +Generating RTLIL representation for module `$paramod$37c9083f315aef6418bc36d59a5da68a3da4bfc0\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 168431114 + +303.406. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 168431114 +Generating RTLIL representation for module `$paramod$7d8ed0d380086f3fd20af1b3d6bad26c1a863d19\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 3 + +303.407. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 3 +Generating RTLIL representation for module `$paramod$a5a7ea3f863b90894f2e37ede844438efeda16cb\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$816bd8801543ded25453197a2176491759fe2859\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 4096 + +303.408. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 4096 +Generating RTLIL representation for module `$paramod$4595dd0113417d9abc50b20011762907d79186b1\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 + +303.409. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_ser_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 + +303.410. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_ser_rlmreg_p'. +Parameter \WIDTH = 24 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$85ede8ffb279c419da455148d6824422a8b71662\tri_ser_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_ser_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_ser_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 + +303.411. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_ser_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_ser_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_ser_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_ser_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 131136 + +303.412. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 131136 +Generating RTLIL representation for module `$paramod$700023484c60c8c9045d5493326762825ae9f9fe\tri_ser_rlmreg_p'. +Parameter \WIDTH = 29 +Parameter \INIT = 0 + +303.413. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 29 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$d17b4197fa37dfbc027c19060d2e33183b0d5c4a\tri_ser_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 + +303.414. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$fc46983bfa0f2d294b902322957eac56fa5325fb\tri_ser_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 + +303.415. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$7957a955388e36b536b992b3927aa49fa147612a\tri_ser_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 26 + +303.416. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 26 +Generating RTLIL representation for module `$paramod$a91b848c6efbe572d55b0055c22acc620229bcd3\tri_ser_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a7148e5d92b9abd61e5e63d4577b5c3c8b15ae85\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a7148e5d92b9abd61e5e63d4577b5c3c8b15ae85\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a7148e5d92b9abd61e5e63d4577b5c3c8b15ae85\tri_rlmreg_p'. +Parameter \WIDTH = 62 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a7148e5d92b9abd61e5e63d4577b5c3c8b15ae85\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 789504 + +303.417. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 789504 +Generating RTLIL representation for module `$paramod$ca501e5f9af3a068834573f281df491eb8274eb8\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 202117132 + +303.418. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 202117132 +Generating RTLIL representation for module `$paramod$9ccbed458d3ba76c8d27066e357062032df5b452\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 16'0000000011111010 + +303.419. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 16'0000000011111010 +Generating RTLIL representation for module `$paramod$c1861d321a2d10c5319536ae04052c7b0f3faee7\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 + +303.420. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Generating RTLIL representation for module `$paramod$a7d1f07b1cc41a192ddcacd70ab5f6d7e15d5e12\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Found cached RTLIL representation for module `$paramod$a7d1f07b1cc41a192ddcacd70ab5f6d7e15d5e12\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 + +303.421. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$d1d7f4e071bffecfccf4b1ce799f02ef69db4e07\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$d1d7f4e071bffecfccf4b1ce799f02ef69db4e07\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$3ef9d3e055ac8a131a39b848dee8e704d4c1ccd8\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a3ef2a758cda09d9af2e33787800b667c0c1f871\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Reprocessing module iuq_spr because instantiated module $paramod$f59a557fe17ab7a2569e7b7c7180bfd5caf98588\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_spr'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$31fe6d6fb21b54cd707461aac373e440f89bedfa\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$6c7a2ec9cc6f50517039cb2d268cfa81903ee100\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$6c7a2ec9cc6f50517039cb2d268cfa81903ee100\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.422. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$60c2a32b651165e48eac1fb41959cb328d7e0cae\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$6c7a2ec9cc6f50517039cb2d268cfa81903ee100\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$6c7a2ec9cc6f50517039cb2d268cfa81903ee100\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$60c2a32b651165e48eac1fb41959cb328d7e0cae\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.423. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$efde5e5c2840143d4755af1bf1e434c7039084aa\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 136 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$94953c4e8d41c8a82cad16afc857bcd81a5879a1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$60c2a32b651165e48eac1fb41959cb328d7e0cae\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000010'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$0eb4720d52d3587d9d29802dd7665ce088394b51\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 18 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$93c3fe6f2c37e7d3a0c067b7c94c4252fb786906\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$06d3b41689a7262b09fe229b6c57f6f66b1d1867\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 + +303.424. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 19 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$69582c978ab42fbed90a9d19c32ec25e72c12c1b\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 16 +Found cached RTLIL representation for module `$paramod$c1f1f63ed25e37e985870ff561a3e944e5947ca1\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 32 +Found cached RTLIL representation for module `$paramod$75f6ac5c1a4702c6351da2cc49c81c0bbc474076\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 32 +Found cached RTLIL representation for module `$paramod$75f6ac5c1a4702c6351da2cc49c81c0bbc474076\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 32 +Found cached RTLIL representation for module `$paramod$75f6ac5c1a4702c6351da2cc49c81c0bbc474076\tri_rlmreg_p'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 1 +Parameter \REGISTER_RENAME_DEPTH = 12 +Parameter \STORAGE_WIDTH = 4 + +303.425. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 1 +Parameter \REGISTER_RENAME_DEPTH = 12 +Parameter \STORAGE_WIDTH = 4 +Generating RTLIL representation for module `$paramod$4efa46117ff856dd85b8b88a817dc9c92e8dcac4\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \ARCHITECTED_REGISTER_DEPTH = 1 +Parameter \REGISTER_RENAME_DEPTH = 8 +Parameter \STORAGE_WIDTH = 3 + +303.426. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 1 +Parameter \REGISTER_RENAME_DEPTH = 8 +Parameter \STORAGE_WIDTH = 3 +Generating RTLIL representation for module `$paramod$07dafcc305e2b9f1a15b511faf44f7a454d65d5a\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \ARCHITECTED_REGISTER_DEPTH = 2 +Parameter \REGISTER_RENAME_DEPTH = 8 +Parameter \STORAGE_WIDTH = 3 + +303.427. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 2 +Parameter \REGISTER_RENAME_DEPTH = 8 +Parameter \STORAGE_WIDTH = 3 +Generating RTLIL representation for module `$paramod$ce466000330c6804eac4fa186d65bb7a11af8c60\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \ARCHITECTED_REGISTER_DEPTH = 9 +Parameter \REGISTER_RENAME_DEPTH = 24 +Parameter \STORAGE_WIDTH = 5 + +303.428. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_rn_map'. +Parameter \ARCHITECTED_REGISTER_DEPTH = 9 +Parameter \REGISTER_RENAME_DEPTH = 24 +Parameter \STORAGE_WIDTH = 5 +Generating RTLIL representation for module `$paramod$4f88f4da98d56b7f3ea2a91685dbf57c2d1ebc2e\iuq_rn_map'. +Warning: Replacing memory \buffer_pool_d with list of registers. See ../verilog/work/iuq_rn_map.v:360 +Warning: Replacing memory \spec_map_itag_d with list of registers. See ../verilog/work/iuq_rn_map.v:315 +Warning: Replacing memory \spec_map_arc_d with list of registers. See ../verilog/work/iuq_rn_map.v:304 +Warning: Replacing memory \comp_map_d with list of registers. See ../verilog/work/iuq_rn_map.v:266 +Parameter \ARCHITECTED_REGISTER_DEPTH = 36 +Parameter \REGISTER_RENAME_DEPTH = 64 +Parameter \STORAGE_WIDTH = 6 +Found cached RTLIL representation for module `$paramod$a31b2e7d1b2644a0d5eb98b2fb5b28bdbcba2be2\iuq_rn_map'. +Parameter \SIZE = 7 +Parameter \WRAP = 31 + +303.429. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_cpl_ctrl_inc'. +Parameter \SIZE = 7 +Parameter \WRAP = 31 +Generating RTLIL representation for module `$paramod$95b64968687f119e354d345aa72b7eb5f018a2fc\iuq_cpl_ctrl_inc'. +Parameter \SIZE = 7 +Parameter \WRAP = 31 +Found cached RTLIL representation for module `$paramod$95b64968687f119e354d345aa72b7eb5f018a2fc\iuq_cpl_ctrl_inc'. +Parameter \FPR_POOL = 64 +Parameter \FPR_UCODE_POOL = 4 +Parameter \FPSCR_POOL_ENC = 5 + +303.430. Executing AST frontend in derive mode using pre-parsed AST for module `\iuq_axu_fu_rn'. +Parameter \FPR_POOL = 64 +Parameter \FPR_UCODE_POOL = 4 +Parameter \FPSCR_POOL_ENC = 5 +Generating RTLIL representation for module `$paramod$65fc5210a2073cb2b2142f153d6840e371e0c73f\iuq_axu_fu_rn'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 20 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$60c2a32b651165e48eac1fb41959cb328d7e0cae\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.431. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$49e7f2e169da76aecff92bac2244755aca3105d4\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$54279aa8da8b466ff79ad1f35f3c4c178207b6e6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.432. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$743389ab1c0f5682479fceefa7f065704ccca725\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 + +303.433. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Generating RTLIL representation for module `$paramod$2e9023b0d27e5f13a23eb10842991aa3bd8574e5\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$b8d73cba6f0afa3e69cc8bedc1d449a2b16796fe\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$08b32c39f55be48b728a70e83badf158e2b48bbd\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7a9283cd54c63739b290315339eae36c34cb752d\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7f547f9b0e2fc4232d72f54553e5d1eece74e894\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 0 +Found cached RTLIL representation for module `$paramod$7f547f9b0e2fc4232d72f54553e5d1eece74e894\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod\tri_rlmlatch_p\INIT=s32'00000000000000000000000000000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8e06d52df2bace784b45cb91057fb19e798d60a\tri_rlmreg_p'. +Reprocessing module iuq_uc_cplbuffer because instantiated module $paramod$a734803f1dcac5b98a505a661a7d77856a8bdc90\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\iuq_uc_cplbuffer'. +Warning: Replacing memory \xer_d with list of registers. See ../verilog/work/iuq_uc_cplbuffer.v:182 +Warning: Replacing memory \buffer_d with list of registers. See ../verilog/work/iuq_uc_cplbuffer.v:180 +Parameter \addressable_ports = 64 +Parameter \addressbus_width = 6 +Parameter \port_bitwidth = 34 +Parameter \ways = 8 + +303.434. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_64x34_8w_1r1w'. +Parameter \addressable_ports = 64 +Parameter \addressbus_width = 6 +Parameter \port_bitwidth = 34 +Parameter \ways = 8 +Generating RTLIL representation for module `$paramod$c427193f0beb815d7fdac7be392d5008d52c193e\tri_64x34_8w_1r1w'. +Parameter \WIDTH = 14 +Parameter \INIT = 14'00000000000000 + +303.435. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 14 +Parameter \INIT = 14'00000000000000 +Generating RTLIL representation for module `$paramod$6e02b82491586ae47cbbeee4f09abd0a4e671953\tri_slat_scan'. +Parameter \WIDTH = 22 +Parameter \INIT = 22'0000000000000000000000 + +303.436. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_slat_scan'. +Parameter \WIDTH = 22 +Parameter \INIT = 22'0000000000000000000000 +Generating RTLIL representation for module `$paramod$dab9c4894dd62457dd168aeec6a16f5b10462dd1\tri_slat_scan'. +Parameter \WIDTH = 3 +Parameter \INIT = 3'000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000011\INIT=3'000'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000100\INIT=4'0000'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000100\INIT=4'0000'. +Parameter \WIDTH = 15 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001111'. +Parameter \WIDTH = 15 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001111'. +Parameter \WIDTH = 25 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.437. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 25 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$25d915b8fda368a0d138ec3209e7ccb973bdb3ed\tri_rlmreg_p'. +Parameter \WAYDATASIZE = 34 +Parameter \PARBITS = 4 + +303.438. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_dir'. +Parameter \WAYDATASIZE = 34 +Parameter \PARBITS = 4 +Generating RTLIL representation for module `$paramod$8e9d2b5c4e5e3234706aefd651dec5b139803719\lq_dir'. +Parameter \PARBITS = 4 + +303.439. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_dcc'. +Parameter \PARBITS = 4 +Generating RTLIL representation for module `$paramod\lq_dcc\PARBITS=s32'00000000000000000000000000000100'. +Parameter \addressable_ports = 256 +Parameter \addressbus_width = 8 +Parameter \port_bitwidth = 144 +Parameter \bit_write_type = 9 +Parameter \ways = 8 + +303.440. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_256x144_8w_1r1w'. +Parameter \addressable_ports = 256 +Parameter \addressbus_width = 8 +Parameter \port_bitwidth = 144 +Parameter \bit_write_type = 9 +Parameter \ways = 8 +Generating RTLIL representation for module `$paramod$f326f62b776a694dfa5ec37ccc59f37ef7d9765c\tri_256x144_8w_1r1w'. +Parameter \WIDTH = 14 +Parameter \INIT = 14'00000000000000 +Found cached RTLIL representation for module `$paramod$6e02b82491586ae47cbbeee4f09abd0a4e671953\tri_slat_scan'. +Parameter \WIDTH = 2 +Parameter \INIT = 2'00 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000010\INIT=2'00'. +Parameter \WIDTH = 2 +Parameter \INIT = 2'00 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000010\INIT=2'00'. +Parameter \WIDTH = 8 +Parameter \INIT = 8'00000000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000001000\INIT=8'00000000'. +Parameter \WIDTH = 9 + +303.441. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 9 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001001'. +Parameter \WIDTH = 9 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001001'. +Parameter \WIDTH = 29 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.442. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 29 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$3dcd0c669aad88b1c58fbaff36c168c8c1ee8ff0\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.443. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \addressable_ports = 64 +Parameter \addressbus_width = 6 +Parameter \port_bitwidth = 34 +Parameter \ways = 8 +Found cached RTLIL representation for module `$paramod$c427193f0beb815d7fdac7be392d5008d52c193e\tri_64x34_8w_1r1w'. +Parameter \WIDTH = 14 +Parameter \INIT = 14'00000000000000 +Found cached RTLIL representation for module `$paramod$6e02b82491586ae47cbbeee4f09abd0a4e671953\tri_slat_scan'. +Parameter \WIDTH = 3 +Parameter \INIT = 3'000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000011\INIT=3'000'. +Parameter \WIDTH = 3 +Parameter \INIT = 3'000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000011\INIT=3'000'. +Parameter \WIDTH = 4 +Parameter \INIT = 4'0000 +Found cached RTLIL representation for module `$paramod\tri_slat_scan\WIDTH=s32'00000000000000000000000000000100\INIT=4'0000'. +Parameter \WIDTH = 10 + +303.444. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 10 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001010'. +Parameter \WIDTH = 10 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000001010'. +Parameter \WIDTH = 25 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$25d915b8fda368a0d138ec3209e7ccb973bdb3ed\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 42 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.445. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 42 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$73c30faf76285c7895e09d04b0bb16651c92ee13\tri_rlmreg_p'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.446. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$ecaa87b5a162a4f7fdbc6a76a7d10f27c246f249\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.447. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$d9147babbf688846a1f5f84bcfaf5c961b18b532\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 38 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.448. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 38 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$5eb1f182bfbb63a225b44c0749cc3ded4a924758\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \EVENTS_IN = 64 + +303.449. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_event_mux1t'. +Parameter \EVENTS_IN = 64 +Generating RTLIL representation for module `$paramod\tri_event_mux1t\EVENTS_IN=s32'00000000000000000000000001000000'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb1feb5bdcccca22afbc2410c098ee780ec04072\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb1feb5bdcccca22afbc2410c098ee780ec04072\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 18 + +303.450. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_plat'. +Parameter \WIDTH = 18 +Generating RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000010010'. +Reprocessing module lq_perv because instantiated module $paramod\tri_event_mux1t\EVENTS_IN=s32'00000000000000000000000001000000 has become available. +Generating RTLIL representation for module `\lq_perv'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 52 + +303.451. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 52 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000110100'. +Parameter \WIDTH = 20 + +303.452. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 20 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000010100'. +Parameter \WIDTH = 32 + +303.453. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 32 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000100000'. +Parameter \WIDTH = 52 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000110100'. +Parameter \WIDTH = 52 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000110100'. +Parameter \WIDTH = 64 + +303.454. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 64 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000001000000'. +Parameter \WIDTH = 64 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000001000000'. +Parameter \WIDTH = 7 + +303.455. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi22'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 + +303.456. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 3 + +303.457. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_oai21'. +Parameter \WIDTH = 3 +Generating RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 2 + +303.458. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 2 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 + +303.459. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi21'. +Parameter \WIDTH = 2 +Generating RTLIL representation for module `$paramod\tri_aoi21\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 3 + +303.460. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 3 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 5 + +303.461. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi21'. +Parameter \WIDTH = 5 +Generating RTLIL representation for module `$paramod\tri_aoi21\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 5 + +303.462. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 5 +Generating RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 6 + +303.463. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_oai21'. +Parameter \WIDTH = 6 +Generating RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 8 + +303.464. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 8 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 + +303.465. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xnor2'. +Parameter \WIDTH = 8 +Generating RTLIL representation for module `$paramod\tri_xnor2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 7 + +303.466. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 + +303.467. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_aoi22\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_aoi21\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 5 +Found cached RTLIL representation for module `$paramod\tri_aoi21\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 5 +Found cached RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 6 +Found cached RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000000110'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 + +303.468. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xnor2'. +Parameter \WIDTH = 4 +Generating RTLIL representation for module `$paramod\tri_xnor2\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 + +303.469. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 8 +Generating RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 3 + +303.470. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 3 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 3 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000011'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 8 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001000'. +Parameter \WIDTH = 4 + +303.471. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 4 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 7 +Found cached RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000000111'. +Parameter \WIDTH = 2 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000010'. +Parameter \WIDTH = 9 + +303.472. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_oai21'. +Parameter \WIDTH = 9 +Generating RTLIL representation for module `$paramod\tri_oai21\WIDTH=s32'00000000000000000000000000001001'. +Parameter \WIDTH = 9 + +303.473. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 9 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001001'. +Parameter \WIDTH = 10 + +303.474. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_aoi21'. +Parameter \WIDTH = 10 +Generating RTLIL representation for module `$paramod\tri_aoi21\WIDTH=s32'00000000000000000000000000001010'. +Parameter \WIDTH = 5 + +303.475. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 5 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000000101'. +Parameter \WIDTH = 12 + +303.476. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_inv'. +Parameter \WIDTH = 12 +Generating RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001100'. +Parameter \WIDTH = 12 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001100'. +Parameter \WIDTH = 11 + +303.477. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xor2'. +Parameter \WIDTH = 11 +Generating RTLIL representation for module `$paramod\tri_xor2\WIDTH=s32'00000000000000000000000000001011'. +Parameter \WIDTH = 12 +Found cached RTLIL representation for module `$paramod\tri_inv\WIDTH=s32'00000000000000000000000000001100'. +Parameter \WIDTH = 12 + +303.478. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_xnor2'. +Parameter \WIDTH = 12 +Generating RTLIL representation for module `$paramod\tri_xnor2\WIDTH=s32'00000000000000000000000000001100'. +Parameter \WIDTH = 10 + +303.479. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nand2'. +Parameter \WIDTH = 10 +Generating RTLIL representation for module `$paramod\tri_nand2\WIDTH=s32'00000000000000000000000000001010'. +Parameter \WIDTH = 11 + +303.480. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_nor2'. +Parameter \WIDTH = 11 +Generating RTLIL representation for module `$paramod\tri_nor2\WIDTH=s32'00000000000000000000000000001011'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ecaa87b5a162a4f7fdbc6a76a7d10f27c246f249\tri_rlmreg_p'. +Parameter \WIDTH = 27 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd0c231d1b02012669f3c2b738514adcdc60b2c7\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 4 +Parameter \NEEDS_SRESET = 1 + +303.481. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 4 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$6fa0e013330a5612acce026b20d1356ee6809c16\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 8 +Parameter \NEEDS_SRESET = 1 + +303.482. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 8 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$83a76c74bfe5a655a2b1f27db00cf66e5382580a\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.483. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$c53946f07c0fa31bb5528b57d2c2dd2c0d87fa7b\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 42 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$73c30faf76285c7895e09d04b0bb16651c92ee13\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 72 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.484. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 72 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$d95d2fca716b0264f3b3dcd7ba6d297e153fcd53\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb1feb5bdcccca22afbc2410c098ee780ec04072\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb1feb5bdcccca22afbc2410c098ee780ec04072\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \REGSIZE = 64 + +303.485. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_spr_dvccmp'. +Parameter \REGSIZE = 64 +Generating RTLIL representation for module `$paramod\lq_spr_dvccmp\REGSIZE=s32'00000000000000000000000001000000'. +Parameter \REGSIZE = 64 +Found cached RTLIL representation for module `$paramod\lq_spr_dvccmp\REGSIZE=s32'00000000000000000000000001000000'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 58 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.486. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 58 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$32d226f644f987659e9b73ea90c01db6c70c12db\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 36 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$d9147babbf688846a1f5f84bcfaf5c961b18b532\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.487. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_ser_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.488. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_regk'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_regk'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 25 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.489. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 25 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$25d915b8fda368a0d138ec3209e7ccb973bdb3ed\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.490. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.491. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.492. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.493. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_regk'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_regk'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.494. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_regk'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.495. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$ee6ab1e637f216030d17b24b5df851e6a31bbbe2\tri_ser_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.496. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_ser_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.497. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_ser_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_ser_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.498. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_regk'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_regk'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_regk'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_regk'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_regk'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_regk'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_regk'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Reprocessing module lq_dcc because instantiated module $paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_ser_rlmreg_p has become available. +Generating RTLIL representation for module `\lq_dcc'. +Parameter \hvmode = 1 +Parameter \a2mode = 1 + +303.499. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_spr_tspr'. +Parameter \hvmode = 1 +Parameter \a2mode = 1 +Generating RTLIL representation for module `$paramod$9f74ae68d5b9be52dd994f498b1d9eb79e9eb110\lq_spr_tspr'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \hvmode = 1 +Parameter \a2mode = 1 + +303.500. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_spr_cspr'. +Parameter \hvmode = 1 +Parameter \a2mode = 1 +Generating RTLIL representation for module `$paramod$9f74ae68d5b9be52dd994f498b1d9eb79e9eb110\lq_spr_cspr'. +Reprocessing module lq_spr because instantiated module lq_spr_tspr has become available. +Generating RTLIL representation for module `\lq_spr'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WAYDATASIZE = 34 +Parameter \PARBITS = 4 + +303.501. Executing AST frontend in derive mode using pre-parsed AST for module `\lq_dir_tag'. +Parameter \WAYDATASIZE = 34 +Parameter \PARBITS = 4 +Generating RTLIL representation for module `$paramod$8e9d2b5c4e5e3234706aefd651dec5b139803719\lq_dir_tag'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 4 +Found cached RTLIL representation for module `$paramod\tri_plat\WIDTH=s32'00000000000000000000000000000100'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$5e65f5ca7cb793b8b03c1d7b93a788374a1650a6\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$db6257b43e9a2c8ab6a9f6c9317dce0a4a651405\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 15 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$c9f9022ef8163f29cc302b8f31367f1065338ec9\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$47d429b688788098bc6d68dab0f2bec550ef6d04\tri_slat_scan'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$e092d5125e05a02f5483345591e893023dcb8651\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 15 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$c9f9022ef8163f29cc302b8f31367f1065338ec9\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 65535 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$47d429b688788098bc6d68dab0f2bec550ef6d04\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \RESET_INVERTS_SCAN = 1'1 +Found cached RTLIL representation for module `$paramod$f4b09619791fbf539acce8c3b5851aaef7f76980\tri_slat_scan'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 26 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fcfa54a2fb55c33e0d6dbd1ffea3cd16426e12d2\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2bb9ea0e9bcb5abf3d4e792545fcaa2b2b25d71f\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.502. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 132 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2bb9ea0e9bcb5abf3d4e792545fcaa2b2b25d71f\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 52 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p'. +Parameter \WIDTH = 26 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fcfa54a2fb55c33e0d6dbd1ffea3cd16426e12d2\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 41 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.503. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 41 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$8cc62098426372685c4ae0d5f3bbbd060b62756c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 31 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$991fc95d6f5308ae81783b9b6d256dd6efbca1e4\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 29 +Parameter \NEEDS_SRESET = 1 + +303.504. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 29 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$319405a90eb6f98a01e2b8b73a0646b1a60fc05c\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 84 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$d1724e8c6033ac657bfdaf6991f81a11e51e7e64\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$6cb6d74810fe940ebb6f800501ad76dfc8e1ed8a\tri_rlmreg_p'. +Parameter \WIDTH = 68 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$6cb6d74810fe940ebb6f800501ad76dfc8e1ed8a\tri_rlmreg_p'. +Parameter \WIDTH = 84 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$d1724e8c6033ac657bfdaf6991f81a11e51e7e64\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ee6ab1e637f216030d17b24b5df851e6a31bbbe2\tri_rlmreg_p'. +Parameter \WIDTH = 30 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ee6ab1e637f216030d17b24b5df851e6a31bbbe2\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 17 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a843b3cf7cfb867eed17aefd5180985fd47950aa\tri_rlmreg_p'. +Parameter \WIDTH = 11 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb1feb5bdcccca22afbc2410c098ee780ec04072\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 31 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$991fc95d6f5308ae81783b9b6d256dd6efbca1e4\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$8ef857d20eefcb59ae4d11cb8cdd2332b8d73a48\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \WIDTH = 10 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$13dd46c3c0b360cd2c14cbc511fe29671e9e3a0c\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 14 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$f0788f800afe6921b0ea20d741cf3c845afb4312\tri_rlmreg_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$402124cb7ce5551fc9b2810eac7e45005d98a3fe\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$76e650ff9f45d33b37927ea26a74ba3642490fe2\tri_rlmlatch_p'. +Parameter \WIDTH = 4 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$bd081d766540370ec72d3f1690bd044e2072d309\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Reprocessing module lq_derat because instantiated module $paramod$fc62d22c53fc27197c93fa0c5c358c3e158088c9\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\lq_derat'. +Warning: Replacing memory \eratm_entry_nxt_state with list of registers. See ../verilog/work/lq_derat.v:4485 +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.505. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.506. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 + +303.507. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Generating RTLIL representation for module `$paramod$a54065fad61edd9f6203fa22e41d85545922077c\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 1 + +303.508. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 1 +Generating RTLIL representation for module `$paramod$e41da141affabc88e6dcb65f9f9767a35b62c0c3\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 1 + +303.509. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 1 +Generating RTLIL representation for module `$paramod$b26508249bdf8d87aa174e8bead0c56ae5ef923e\tri_rlmreg_p'. +Parameter \WIDTH = 32 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$8800beae12ebb5b31535bdf2112de4e2d75d2273\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8ce279040df485fc256fcdb356d80795e0ee55d\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a54065fad61edd9f6203fa22e41d85545922077c\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$3689278a1e6b815ea49e2bd754f531a62fcae723\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$40f82f8753c7f461c8fe11b7e49bf70fa68b8d68\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$cec3ff55261d2e40d9ee2fc4dbffbf009ab04cf9\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$ea4de3ebd94569b6d28e7dde10703171d3bbb3ef\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$f8ce279040df485fc256fcdb356d80795e0ee55d\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$a54065fad61edd9f6203fa22e41d85545922077c\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$3689278a1e6b815ea49e2bd754f531a62fcae723\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$3689278a1e6b815ea49e2bd754f531a62fcae723\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Found cached RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000001'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 22 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$58922ad178a4884ed57f9057db60ad0246ca1579\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fca630cf56c7547559b6971fc0fa25e8343d9ee2\tri_rlmreg_p'. +Parameter \WIDTH = 70 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fca630cf56c7547559b6971fc0fa25e8343d9ee2\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 2 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$e1ce24e69a27e081b68942c3df21d92d1634f3e8\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 60 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$b46fe1df728d78e4d22a38b8fa1769de6d07902b\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Found cached RTLIL representation for module `$paramod$c2f6791a1079fa9136aaceca5c8f2aab92c23737\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \WIDTH = 12 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0f5835220393a01e7fbc8dd033079af2b7be946c\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Reprocessing module lq_pfetch because instantiated module $paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\lq_pfetch'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.510. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_regk'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_regk'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_regk'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.511. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$ecaa87b5a162a4f7fdbc6a76a7d10f27c246f249\tri_regk'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.512. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 144 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$04d7c1799e8e716b696abd77c97c089d6a7528dd\tri_regk'. +Parameter \WIDTH = 16 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$9ae2182b2a85c87f5d31ca047065b5eff9c0aba0\tri_rlmreg_p'. +Parameter \WIDTH = 128 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$ecaa87b5a162a4f7fdbc6a76a7d10f27c246f249\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 + +303.513. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 136 +Parameter \NEEDS_SRESET = 1 + +303.514. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 136 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$fe4fb102f7e3888229606485ca87503e4fed7138\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 136 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$fe4fb102f7e3888229606485ca87503e4fed7138\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 170 +Parameter \NEEDS_SRESET = 1 + +303.515. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_regk'. +Parameter \WIDTH = 8 +Parameter \INIT = 170 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$73b357fee10495c00134c37465248658d2216831\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 170 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$73b357fee10495c00134c37465248658d2216831\tri_regk'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 5 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$0d80a9441dc4fea3ac06fb53f5091d4f48fbee80\tri_rlmreg_p'. +Parameter \WIDTH = 64 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cebc0153da901928838ecb810a9483236a9fd1e6\tri_regk'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 + +303.516. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Generating RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 9 +Parameter \INIT = 1 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 8 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$7d70d64e65096de50c492b7e16a5a1d1835dd8c6\tri_rlmreg_p'. +Parameter \WIDTH = 7 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$91d87a53b8377cdf22314162fe318e577cbaec93\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 6 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$2430f5819870a5095be5fe258e84c2ef19e3d2c1\tri_rlmreg_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$cb12a78708a1dc52ee894fac4efbaaea152ed6dc\tri_rlmlatch_p'. +Parameter \WIDTH = 7 + +303.517. Executing AST frontend in derive mode using pre-parsed AST for module `\tri_direct_err_rpt'. +Parameter \WIDTH = 7 +Generating RTLIL representation for module `$paramod\tri_direct_err_rpt\WIDTH=s32'00000000000000000000000000000111'. +Reprocessing module lq_fgen because instantiated module $paramod$5ea097507c8a975dca342ca3e8e19f29ae2c77fa\tri_rlmreg_p has become available. +Generating RTLIL representation for module `\lq_fgen'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 1 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$a23eee606c49003f5eceddd2e21d0fc4b58a0a90\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_regk'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL representation for module `$paramod$c728ed5e9086242ea976c55244849e776ba76538\tri_rlmreg_p'. +Parameter \WIDTH = 3 +Parameter \INIT = 0 +Parameter \NEEDS_SRESET = 1 +Found cached RTLIL re