From 737d0ddafb39c313c3dd22cdf007023f36c7137f Mon Sep 17 00:00:00 2001
From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com>
Date: Sun, 14 Aug 2022 14:05:44 -0500
Subject: [PATCH] cleanup

---
 dev/verilog/trilib/tri_st_mult_core.v | 2 +-
 dev/verilog/work/pcq_local_fir2.v     | 1 +
 dev/verilog/work/pcq_regs_fir.v       | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/dev/verilog/trilib/tri_st_mult_core.v b/dev/verilog/trilib/tri_st_mult_core.v
index 3805b49..35489be 100755
--- a/dev/verilog/trilib/tri_st_mult_core.v
+++ b/dev/verilog/trilib/tri_st_mult_core.v
@@ -102,7 +102,7 @@ module tri_st_mult_core(
    //wire [0:`NCLK_WIDTH-1] ex4_lclk;
    //wire [0:`NCLK_WIDTH-1] ex5_lclk;
    wire             ex4_lclk;
-   wire             ex6_lclk;
+   wire             ex5_lclk;
 
    wire [198:240]   ex4_pp2_0c_din;
    wire [198:240]   ex4_pp2_0c;
diff --git a/dev/verilog/work/pcq_local_fir2.v b/dev/verilog/work/pcq_local_fir2.v
index dc1a4d0..6a0f6a2 100755
--- a/dev/verilog/work/pcq_local_fir2.v
+++ b/dev/verilog/work/pcq_local_fir2.v
@@ -134,6 +134,7 @@ module pcq_local_fir2(
    wire                           func_d1clk;
    wire                           func_d2clk;
    //wire  [0:`NCLK_WIDTH-1]        func_lclk;
+   wire                           func_lclk;
    wire                           mode_d1clk;
    wire                           mode_d2clk;
    //wire  [0:`NCLK_WIDTH-1]        mode_lclk;
diff --git a/dev/verilog/work/pcq_regs_fir.v b/dev/verilog/work/pcq_regs_fir.v
index 84962f4..1abc63b 100755
--- a/dev/verilog/work/pcq_regs_fir.v
+++ b/dev/verilog/work/pcq_regs_fir.v
@@ -219,6 +219,7 @@ module pcq_regs_fir(
    wire                           func_d1clk;
    wire                           func_d2clk;
    //wire [0:`NCLK_WIDTH-1]         func_lclk;
+   wire                           func_lclk;
    wire                           func_thold_b;
    wire                           func_force;
    // SCOM