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//--------------------------------------------------------------------------------
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// Auto-generated by LiteX (6932fc51) on 2022-08-04 07:49:47
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//--------------------------------------------------------------------------------
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#ifndef __GENERATED_MEM_H
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#define __GENERATED_MEM_H
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#ifndef ROM_BASE
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#define ROM_BASE 0x00000000L
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#define ROM_SIZE 0x00010000
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#endif
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#ifndef SRAM_BASE
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#define SRAM_BASE 0x00010000L
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#define SRAM_SIZE 0x00010000
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#endif
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#ifndef MAIN_RAM_BASE
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#define MAIN_RAM_BASE 0x00100000L
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#define MAIN_RAM_SIZE 0x00000100
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#endif
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#ifndef CSR_BASE
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#define CSR_BASE 0xfff00000L
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#define CSR_SIZE 0x00010000
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#endif
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#ifndef MEM_REGIONS
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#define MEM_REGIONS "ROM 0x00000000 0x10000 \nSRAM 0x00010000 0x10000 \nMAIN_RAM 0x00100000 0x100 \nCSR 0xfff00000 0x10000 "
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#endif
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#endif
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