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234 lines
9.5 KiB
VHDL
234 lines
9.5 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ibm, ieee, work, tri, support;
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use ibm.std_ulogic_support.all;
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use ibm.std_ulogic_function_support.all;
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use ibm.std_ulogic_unsigned.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use tri.tri_latches_pkg.all;
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use support.power_logic_pkg.all;
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entity xuq_lsu_data_rot32_lu is
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generic(l_endian_m : integer := 1);
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port(
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vdd :inout power_logic;
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gnd :inout power_logic;
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rot_sel1 :in std_ulogic_vector(0 to 31);
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rot_sel2 :in std_ulogic_vector(0 to 31);
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rot_sel3 :in std_ulogic_vector(0 to 31);
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rot_sel2_le :in std_ulogic_vector(0 to 31);
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rot_sel3_le :in std_ulogic_vector(0 to 31);
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rot_data :in std_ulogic_vector(0 to 127);
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data256_rot_le :out std_ulogic_vector(0 to 127);
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data256_rot :out std_ulogic_vector(0 to 127)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end xuq_lsu_data_rot32_lu;
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architecture xuq_lsu_data_rot32_lu of xuq_lsu_data_rot32_lu is
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signal rot3210 :std_ulogic_vector(0 to 127);
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signal rotC840 :std_ulogic_vector(0 to 127);
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signal rot10 :std_ulogic_vector(0 to 127);
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signal le_rot_data :std_ulogic_vector(0 to 127);
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signal le_rotC840 :std_ulogic_vector(0 to 127);
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signal le_rot3210 :std_ulogic_vector(0 to 127);
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begin
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le_mode_on : if l_endian_m = 1 generate begin
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lvl1rot: for byte in 0 to 31 generate begin
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bit: for b in 0 to 3 generate
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signal muxIn :std_ulogic_vector(0 to 3);
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signal muxSel :std_ulogic_vector(0 to 3);
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begin
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muxIn <= rot_data(byte+(b*32)) & rot_data((((16+byte) mod 32))+(b*32)) &
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rot_data(((31 - byte))+(b*32)) & rot_data(((31 - ((16+byte) mod 32)))+(b*32));
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muxSel <= rot_sel1(4*(byte/4) to (4*(byte/4))+3);
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mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41)
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port map ( vdd => vdd,
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gnd => gnd,
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d0 => muxIn(0),
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d1 => muxIn(1),
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d2 => muxIn(2),
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d3 => muxIn(3),
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s0 => muxSel(0),
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s1 => muxSel(1),
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s2 => muxSel(2),
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s3 => muxSel(3),
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y => rot10(byte+(b*32)));
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end generate;
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end generate lvl1rot;
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bitSwap : for bit in 0 to 3 generate begin
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byteSwap : for byte in 0 to 31 generate begin
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le_rot_data(byte+(bit*32)) <= rot_data((31-byte)+(bit*32));
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end generate byteSwap;
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end generate bitSwap;
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lvl2rot: for byte in 0 to 31 generate begin
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bit: for b in 0 to 3 generate
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signal muxIn :std_ulogic_vector(0 to 3);
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signal muxSel :std_ulogic_vector(0 to 3);
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begin
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muxIn <= le_rot_data(byte+(b*32)) & le_rot_data(((4+byte) mod 32)+(b*32)) &
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le_rot_data(((8+byte) mod 32)+(b*32)) & le_rot_data(((12+byte) mod 32)+(b*32));
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muxSel <= rot_sel2_le(4*(byte/4) to (4*(byte/4))+3);
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mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41)
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port map ( vdd => vdd,
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gnd => gnd,
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d0 => muxIn(0),
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d1 => muxIn(1),
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d2 => muxIn(2),
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d3 => muxIn(3),
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s0 => muxSel(0),
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s1 => muxSel(1),
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s2 => muxSel(2),
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s3 => muxSel(3),
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y => le_rotC840(byte+(b*32)));
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end generate;
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end generate lvl2rot;
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lvl3rot: for byte in 0 to 31 generate begin
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bit: for b in 0 to 3 generate
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signal muxIn :std_ulogic_vector(0 to 3);
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signal muxSel :std_ulogic_vector(0 to 3);
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begin
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muxIn <= le_rotC840(byte+(b*32)) & le_rotC840(((1+byte) mod 32)+(b*32)) &
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le_rotC840(((2+byte) mod 32)+(b*32)) & le_rotC840(((3+byte) mod 32)+(b*32));
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muxSel <= rot_sel3_le(4*(byte/4) to (4*(byte/4))+3);
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mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41)
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port map ( vdd => vdd,
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gnd => gnd,
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d0 => muxIn(0),
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d1 => muxIn(1),
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d2 => muxIn(2),
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d3 => muxIn(3),
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s0 => muxSel(0),
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s1 => muxSel(1),
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s2 => muxSel(2),
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s3 => muxSel(3),
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y => le_rot3210(byte+(b*32)));
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end generate;
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end generate lvl3rot;
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data256_rot_le <= le_rot3210;
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end generate le_mode_on;
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le_mode_off : if l_endian_m = 0 generate begin
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lvl1rot: for byte in 0 to 31 generate begin
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bit: for b in 0 to 3 generate
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signal muxIn :std_ulogic_vector(0 to 3);
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signal muxSel :std_ulogic_vector(0 to 3);
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begin
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muxIn <= rot_data(byte+(b*32)) & rot_data(((16+byte) mod 32)+(b*32)) &
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rot_data((31 - byte)+(b*32)) & rot_data((31 - ((16+byte) mod 32))+(b*32));
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muxSel <= rot_sel1(4*(byte/4) to (4*(byte/4))+3);
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rot10(byte+(b*32)) <= (rot_data(byte+(b*32)) and rot_sel1(b*4*(byte/16))) or
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(rot_data(((16+byte) mod 32)+(b*32)) and rot_sel1((b*4*(byte/16))+1));
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end generate;
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end generate lvl1rot;
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le_rot_data <= (others=>'0');
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le_rotC840 <= (others=>'0');
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le_rot3210 <= (others=>'0');
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data256_rot_le <= (others=>'0');
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end generate le_mode_off;
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lvl2rot: for byte in 0 to 31 generate begin
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bit: for b in 0 to 3 generate
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signal muxIn :std_ulogic_vector(0 to 3);
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signal muxSel :std_ulogic_vector(0 to 3);
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begin
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muxIn <= rot10(byte+(b*32)) & rot10(((4+byte) mod 32)+(b*32)) &
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rot10(((8+byte) mod 32)+(b*32)) & rot10(((12+byte) mod 32)+(b*32));
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muxSel <= rot_sel2(4*(byte/4) to (4*(byte/4))+3);
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mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41)
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port map ( vdd => vdd,
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gnd => gnd,
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d0 => muxIn(0),
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d1 => muxIn(1),
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d2 => muxIn(2),
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d3 => muxIn(3),
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s0 => muxSel(0),
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s1 => muxSel(1),
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s2 => muxSel(2),
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s3 => muxSel(3),
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y => rotC840(byte+(b*32)));
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end generate;
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end generate lvl2rot;
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lvl3rot: for byte in 0 to 31 generate begin
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bit: for b in 0 to 3 generate
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signal muxIn :std_ulogic_vector(0 to 3);
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signal muxSel :std_ulogic_vector(0 to 3);
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begin
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muxIn <= rotC840(byte+(b*32)) & rotC840(((1+byte) mod 32)+(b*32)) &
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rotC840(((2+byte) mod 32)+(b*32)) & rotC840(((3+byte) mod 32)+(b*32));
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muxSel <= rot_sel3(4*(byte/4) to (4*(byte/4))+3);
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mux4sel: entity work.xuq_lsu_mux41(xuq_lsu_mux41)
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port map ( vdd => vdd,
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gnd => gnd,
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d0 => muxIn(0),
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d1 => muxIn(1),
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d2 => muxIn(2),
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d3 => muxIn(3),
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s0 => muxSel(0),
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s1 => muxSel(1),
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s2 => muxSel(2),
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s3 => muxSel(3),
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y => rot3210(byte+(b*32)));
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end generate;
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end generate lvl3rot;
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data256_rot <= rot3210;
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end xuq_lsu_data_rot32_lu;
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